CN110349617A - A kind of memory - Google Patents
A kind of memory Download PDFInfo
- Publication number
- CN110349617A CN110349617A CN201910639154.8A CN201910639154A CN110349617A CN 110349617 A CN110349617 A CN 110349617A CN 201910639154 A CN201910639154 A CN 201910639154A CN 110349617 A CN110349617 A CN 110349617A
- Authority
- CN
- China
- Prior art keywords
- memory
- redundant resource
- main array
- ecc area
- ecc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 60
- 238000012937 correction Methods 0.000 claims abstract description 8
- 230000007704 transition Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 10
- 238000000034 method Methods 0.000 description 11
- 230000008901 benefit Effects 0.000 description 7
- 230000008439 repair process Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 1
- 239000010893 paper waste Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
- G11C29/765—Masking faults in memories by using spares or by reconfiguring using address translation or modifications in solid state disks
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
This application discloses a kind of memories, comprising: main array, for storing data to be stored；ECC area, for carrying out error coded correction to the main array；Redundant resource, for carrying out redundancy reparation to the main array and the ECC area；Wherein, the redundant resource, the main array and the ECC area are arranged sequentially together.The application realizes the access speed for improving RRAM memory, to reach the technical effect of best performance.
Description
Technical field
This application involves microelectronics technology more particularly to a kind of memories.
Background technique
RRAM (Resistance Random Access Memory, resistance-variable storing device) is a kind of novel non-volatile deposits
Reservoir technology has been widely used in Embedded Application and the inner tool of stand alone type application.
With the reduction of process node, the increase of chip area, the capacity of chip is obviously improved, and the yield of chip faces
Huge challenge.In present chip, there are thousands of to tens storage units, due to the inconsistency of technique, Yi Jiqi
His various extraneous factors, will inevitably cause individual storage units performance therein poor or even are not available.
Such case is encountered, if not having repair function to will lead to entire chip in chip can not work, is taken as waste paper.It is repaired when being added
After function, error unit can be replaced using redundant resource automatically, being automatically repaired for bad point be realized, thus the core that bad point is less
Piece becomes available normal chip, to improve the yield of product.
In the chip of RRAM, it usually needs be also added into error coded except redundancy (Redundancy) reparation and correct
(Error Correcting Code, ECC), to improve the reliability that chip reads data.The composition one of chip storage array
As shown in Figure 1, by main array, redundant resource and ECC area composition, wherein redundant resource is used to carry out redundancy to main array
It repairs.
But current RRAM memory has certain loss in access speed, can not reach the technology of optimal performance
Problem.
Summary of the invention
The embodiment of the present application solves RRAM memory in the prior art, there is access by providing a kind of memory
The technical issues of having certain loss in speed, being unable to reach best performance realizes the access speed for improving RRAM memory,
To reach the technical effect of best performance.
The application is provided the following technical solutions by the embodiment of the application:
A kind of memory, comprising:
Main array, for storing data to be stored；
ECC area, for carrying out error coded correction to the main array；
Redundant resource, for carrying out redundancy reparation to the main array and the ECC area；
Wherein, the redundant resource, the main array and the ECC area are located in the same region, and sequence arranges
Together.
Preferably, the redundant resource and the main array share the first erasable reading circuit in periphery.
Preferably, the redundant resource and the ECC area share the second erasable reading circuit in periphery.
Preferably, the redundant resource, comprising:
First part's redundant resource, the first logical address of first part's redundant resource is corresponding with the main array,
First part's redundant resource for being replaced to the erroneous memory cell in the main array, with to the main array into
Row redundancy reparation；
Second logical address of second part redundant resource, the second part redundant resource is corresponding with the ECC area,
The second part redundant resource is for being replaced the erroneous memory cell in the ECC area, to the ECC area
Carry out redundancy reparation.
Preferably, the memory is specially resistance-variable storing device RRAM.
Preferably, the memory is specially phase transition storage PRAM.
Preferably, the memory is specially magnetic memory MRAM.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
In the embodiment of the present application, a kind of memory is disclosed, comprising: main array, for storing data to be stored；
ECC area, for carrying out error coded correction to the main array；Redundant resource, for the main array and the ECC area
Domain carries out redundancy reparation；Wherein, the redundant resource, the main array and the ECC area are arranged sequentially together.By institute
It states redundant resource, the main array and the ECC area to be arranged sequentially together, bring benefit is exactly that access speed is fast, can
Chip performance to be maximized.So efficiently solving RRAM memory in the prior art, there are have one in access speed
The technical issues of setting loss is lost, and best performance is unable to reach realizes the access speed for improving RRAM memory, to reach performance most
Excellent technical effect.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is some embodiments of the present application, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is the schematic diagram of the chip storage array of RRAM reservoir in the prior art；
Fig. 2 is a kind of schematic diagram of the chip storage array of memory in the embodiment of the present application；
Fig. 3 is a kind of reparation structural schematic diagram of memory in the embodiment of the present application；
Fig. 4 is a kind of flow chart of the restorative procedure of memory in the embodiment of the present application.
Specific embodiment
The embodiment of the present application solves RRAM memory in the prior art, there is access by providing a kind of memory
The technical issues of having certain loss in speed, being unable to reach best performance realizes the access speed for improving RRAM memory,
To reach the technical effect of best performance.
The technical solution of the embodiment of the present application is in order to solve the above technical problems, general thought is as follows:
A kind of memory, comprising: main array, for storing data to be stored；ECC area, for the main array
Carry out error coded correction；Redundant resource, for carrying out redundancy reparation to the main array and the ECC area；Wherein, described
Redundant resource, the main array and the ECC area are located in the same region, and are arranged sequentially together.
In order to better understand the above technical scheme, in conjunction with appended figures and specific embodiments to upper
Technical solution is stated to be described in detail.
Illustrate first, herein presented term "and/or", only a kind of incidence relation for describing affiliated partner, table
Show there may be three kinds of relationships, for example, A and/or B, can indicate: individualism A exists simultaneously A and B, individualism B this three
Kind situation.In addition, character "/" herein, typicallys represent the relationship that forward-backward correlation object is a kind of "or".
Embodiment one
As shown in Fig. 2, present embodiments providing a kind of memory, comprising:
Main array, for storing data to be stored；
ECC (Error Correction Code, error correcting code) region, for carrying out error coded correction to main array；
Redundant resource, for carrying out redundancy reparation to main array and ECC area；
Wherein, redundant resource, main array and ECC area are located in the same region, and are arranged sequentially together.
In the specific implementation process, the memory is specifically as follows: RRAM (Resistance Random Access
Memory, resistance-variable storing device) or PRAM (Phase Change Random Access Memory, phase transition storage) or
MRAM (Magnetic Random Access Memory, magnetic memory).It is specifically which kind of memory for the memory,
The present embodiment is not specifically limited.
In the prior art, ECC area is not repaired usually, since it is desired that additional address choice, this will increase survey
Complexity is tried, is in addition exactly that those skilled in the art generally believe that ECC area is smaller, the probability to go wrong is little, for many years
This has become the mindset of those skilled in the art.But with the continuous development of technique, the probability of ECC area error exists
Increase, the ECC area and the main array of storing data for storing ECC redundant digit have identical error probability, to this this case
Inventor thinks ECC area, and also it is necessary to repair.
So in the embodiment of the present application, redundant resource may be used also other than it can carry out redundancy reparation to main array domain
To carry out redundancy reparation to ECC area, to improve the reliability of memory, reduces the data that chip is finally read out and occur
The probability of mistake.Further, since by the design of redundant resource, main array and ECC area in the same region, and be arranged sequentially
Together, the problem of also solving extra address.
Furthermore in the prior art, redundant resource (also cry and repair resource) and main array are separation, in physical Design
Belong to two different regions, certain loss is had in access speed, it is optimal to be unable to reach chip performance.
In order to solve the technical problem, in the embodiment of the present application, the design of redundant resource, main array and ECC area is existed
It in the same region, and is arranged sequentially together, bring benefit is exactly that access speed is fast, chip performance can be maximized.
So efficiently solving RRAM memory in the prior art, there are certain loss is had in access speed, it is unable to reach performance
Optimal technical problem realizes the access speed for improving RRAM memory, to reach the technical effect of best performance.
As a kind of optional embodiment, redundant resource and main array share the first erasable reading circuit in periphery, alternatively, superfluous
Remaining resource and ECC area share the second erasable reading circuit in periphery.
It is traditional in the prior art, need to be equipped with the special erasable reading circuit in periphery to redundant resource, increase electricity
Road complexity, and occupy chip area.
In order to solve the technical problem, in the embodiment of the present application, by redundant resource and main Array Design at one shared
The erasable reading circuit in periphery (that is: the first erasable reading circuit in periphery), ECC area oneself uses an erasable reading circuit in periphery
(that is: the second erasable reading circuit in periphery)；Alternatively, main array oneself uses an erasable reading circuit in periphery (that is: the first periphery
Erasable reading circuit), redundant resource and ECC area share the erasable reading circuit in periphery (that is: erasable reading electricity in the second periphery
Road).Since redundant resource and main array (or ECC area) share an erasable reading circuit in periphery, and not having to is redundant resource
The erasable reading circuit in special outfit periphery saves chip area in this way, reducing peripheral circuit complexity.
Preferred embodiment are as follows: redundant resource and main array share (that is: the first erasable reading in periphery of the erasable reading circuit in periphery
Sense circuit), ECC area oneself uses an erasable reading circuit in periphery (that is: the second erasable reading circuit in periphery)
As a kind of optional embodiment, as shown in figure 3, redundant resource, comprising:
First part's redundant resource (that is: redundant resource 1), the first logical address of first part's redundant resource and main array
Corresponding, first part's redundant resource is for being replaced the erroneous memory cell in main array, to carry out redundancy to main array
It repairs；
Second part redundant resource ((that is: redundant resource 2), the second logical address and ECC area of second part redundant resource
Domain is corresponding, and second part redundant resource is for being replaced the erroneous memory cell in ECC area, to carry out to ECC area
Redundancy reparation.
Using the scheme in the application, main array and ECC area can separately be handled in test phase.It ensure that first
In the mistake that main array and ECC area are not fixed, in this way when reading encounters random error, ECC perfect can play its work
With without causing to read error because of defect existing for its own.
Technical solution in above-mentioned the embodiment of the present application, at least have the following technical effects or advantages:
In the embodiment of the present application, a kind of memory is disclosed, comprising: main array, for storing data to be stored；
ECC area, for carrying out error coded correction to the main array；Redundant resource, for the main array and the ECC area
Domain carries out redundancy reparation；Wherein, the redundant resource, the main array and the ECC area are arranged sequentially together.By institute
It states redundant resource, the main array and the ECC area to be arranged sequentially together, bring benefit is exactly that access speed is fast, can
Chip performance to be maximized.So efficiently solving RRAM memory in the prior art, there are have one in access speed
The technical issues of setting loss is lost, and best performance is unable to reach realizes the access speed for improving RRAM memory, to reach performance most
Excellent technical effect.
Embodiment two
Based on the same inventive concept, it as shown in figure 4, the present embodiment additionally provides a kind of restorative procedure of memory, is used for
Memory provided by embodiment one is repaired, which comprises
Step S101: main array and/or ECC area are detected；
Step S102: it if detecting the storage unit of mistake, is carried out using storage unit of the redundant resource to mistake superfluous
Remaining reparation.
In the specific implementation process, the memory is specifically as follows:
RRAM (Resistance Random Access Memory, resistance-variable storing device) or PRAM (Phase Change
Random Access Memory, phase transition storage) or MRAM (Magnetic Random Access Memory, magnetic storage
Device).It is specifically which kind of memory for the memory, the present embodiment is not specifically limited.
Using the scheme in the application, main array and ECC area can separately be handled in test phase.It ensure that first
In the mistake that main array and ECC area are not fixed, in this way when reading encounters random error, ECC perfect can play its work
With without causing to read error because of defect existing for its own.
In the specific implementation process, lead to not just when defect occurs in some storage unit in main array or ECC area
Often when storage, this storage unit is just that a bad point (that is: the storage unit of mistake) at this moment can reflect the address of bad point
It is mapped in redundant resource, realizes replacement of the redundant resource to bad point, so that the storage unit progress redundancy completed to mistake is repaired
It is multiple.
In the specific implementation process, as shown in figure 3, redundant resource, comprising:
First part's redundant resource (that is: redundant resource 1), the first logical address of first part's redundant resource and main array
Corresponding, first part's redundant resource is used to be replaced the storage unit of the mistake in main array, superfluous to carry out to main array
Remaining reparation；
Second part redundant resource (that is: redundant resource 2), the second logical address and ECC area of second part redundant resource
Domain is corresponding, and second part redundant resource is used to be replaced the storage unit of the mistake in ECC area, with to ECC area into
Row redundancy reparation.
Specifically, when there is the storage unit of mistake in main array, then using first part's redundant resource to the mistake
Storage unit accidentally carries out redundancy reparation；When there is the storage unit of mistake in ECC area, then provided using second part redundancy
Source carries out redundancy reparation to the storage unit of the mistake.
In the prior art, ECC area is not repaired usually, since it is desired that additional address choice, this will increase survey
Complexity is tried, is in addition exactly that those skilled in the art generally believe that ECC area is smaller, the probability to go wrong is little, for many years
This has become the mindset of those skilled in the art.But with the continuous development of technique, the probability of ECC area error exists
Increase, the ECC area and the main array of storing data for storing ECC redundant digit have identical error probability, to this this case
Inventor thinks ECC area, and also it is necessary to repair.
So in the embodiment of the present application, redundant resource may be used also other than it can carry out redundancy reparation to main array domain
To carry out redundancy reparation to ECC area, to improve the reliability of memory, reduces the data that chip is finally read out and occur
The probability of mistake.Further, since by the design of redundant resource, main array and ECC area in the same region, and be arranged sequentially
Together, the problem of also solving extra address.
Technical solution in above-mentioned the embodiment of the present application, at least have the following technical effects or advantages:
Since the redundant resource, main array and ECC area are arranged sequentially together, bring benefit is exactly access speed
Fastly, chip performance can be maximized.So efficiently solving RRAM memory in the prior art, there are in access speed
The technical issues of having certain loss, being unable to reach best performance realizes the access speed for improving RRAM memory, to reach
The technical effect of best performance.
Although the preferred embodiment of the application has been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the application range.
Obviously, those skilled in the art can carry out various modification and variations without departing from the essence of the application to the application
Mind and range.In this way, if these modifications and variations of the application belong to the range of the claim of this application and its equivalent technologies
Within, then the application is also intended to include these modifications and variations.
Claims (7)
1. a kind of memory characterized by comprising
Main array；
ECC area, for carrying out error coded correction to the main array；
Redundant resource, for carrying out redundancy reparation to the main array and the ECC area；
Wherein, the redundant resource, the main array and the ECC area are located in the same region, and are arranged sequentially one
It rises.
2. memory as described in claim 1, which is characterized in that the redundant resource and the main array share the first periphery
Erasable reading circuit.
3. memory as described in claim 1, which is characterized in that the redundant resource and the ECC area share outside second
Enclose erasable reading circuit.
4. memory as described in claim 1, which is characterized in that the redundant resource, comprising:
First part's redundant resource, the first logical address of first part's redundant resource is corresponding with the main array, described
First part's redundant resource is superfluous to carry out to the main array for being replaced to the erroneous memory cell in the main array
Remaining reparation；
Second logical address of second part redundant resource, the second part redundant resource is corresponding with the ECC area, described
Second part redundant resource is for being replaced the erroneous memory cell in the ECC area, to carry out to the ECC area
Redundancy reparation.
5. the memory as described in Claims 1 to 4 is any, which is characterized in that the memory is specially resistance-variable storing device
RRAM。
6. the memory as described in Claims 1 to 4 is any, which is characterized in that the memory is specially phase transition storage
PRAM。
7. the memory as described in Claims 1 to 4 is any, which is characterized in that the memory is specially magnetic memory MRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910639154.8A CN110349617B (en) | 2019-07-16 | 2019-07-16 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910639154.8A CN110349617B (en) | 2019-07-16 | 2019-07-16 | Memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110349617A true CN110349617A (en) | 2019-10-18 |
| CN110349617B CN110349617B (en) | 2024-09-17 |
Family
ID=68176420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910639154.8A Active CN110349617B (en) | 2019-07-16 | 2019-07-16 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110349617B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110795037A (en) * | 2019-10-22 | 2020-02-14 | 广东高云半导体科技股份有限公司 | Unit connection method of memory and processor |
| WO2022041962A1 (en) * | 2020-08-27 | 2022-03-03 | 长鑫存储技术有限公司 | Data transmission circuit and memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100211853A1 (en) * | 2009-02-13 | 2010-08-19 | Texas Instruments Incorporated | High Reliability and Low Power Redundancy for Memory |
| US20140006902A1 (en) * | 2012-06-29 | 2014-01-02 | SK Hynix Inc. | Semiconductor device including ecc circuit |
| CN104900269A (en) * | 2014-03-04 | 2015-09-09 | 华邦电子股份有限公司 | Semiconductor memory device and redundancy method thereof |
| CN105206307A (en) * | 2014-06-12 | 2015-12-30 | 北京兆易创新科技股份有限公司 | Chip restoration method and device |
| CN210136722U (en) * | 2019-07-16 | 2020-03-10 | 中国科学院微电子研究所 | Memory device |
-
2019
- 2019-07-16 CN CN201910639154.8A patent/CN110349617B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100211853A1 (en) * | 2009-02-13 | 2010-08-19 | Texas Instruments Incorporated | High Reliability and Low Power Redundancy for Memory |
| US20140006902A1 (en) * | 2012-06-29 | 2014-01-02 | SK Hynix Inc. | Semiconductor device including ecc circuit |
| CN104900269A (en) * | 2014-03-04 | 2015-09-09 | 华邦电子股份有限公司 | Semiconductor memory device and redundancy method thereof |
| CN105206307A (en) * | 2014-06-12 | 2015-12-30 | 北京兆易创新科技股份有限公司 | Chip restoration method and device |
| CN210136722U (en) * | 2019-07-16 | 2020-03-10 | 中国科学院微电子研究所 | Memory device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110795037A (en) * | 2019-10-22 | 2020-02-14 | 广东高云半导体科技股份有限公司 | Unit connection method of memory and processor |
| WO2022041962A1 (en) * | 2020-08-27 | 2022-03-03 | 长鑫存储技术有限公司 | Data transmission circuit and memory |
| US11687402B2 (en) | 2020-08-27 | 2023-06-27 | Changxin Memory Technologies, Inc. | Data transmission circuit and memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110349617B (en) | 2024-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101772810B (en) | Block addressing for parallel memory arrays | |
| CN104778127B (en) | The method and apparatus that a kind of NAND FLASH write data | |
| US8341336B2 (en) | Region-based management method of non-volatile memory | |
| US9003153B2 (en) | Method of storing blocks of data in a plurality of memory devices in a redundant manner, a memory controller and a memory system | |
| CN103871447A (en) | NAND flash memory array, NAND flash memory chip, and methods for accessing, reading and managing NAND flash memory array | |
| TWI652685B (en) | Self-identifying memory errors | |
| CN109426441B (en) | Data storage device and operation method thereof | |
| US8074128B2 (en) | Block management and replacement method, flash memory storage system and controller using the same | |
| US9754682B2 (en) | Implementing enhanced performance with read before write to phase change memory | |
| CN110349617A (en) | A kind of memory | |
| US20100293434A1 (en) | Non-volatile memory with bi-directional error correction protection | |
| CN105206307B (en) | A kind of chip restorative procedure and device | |
| CN103106148B (en) | Block management method, storage controller and storage storing device | |
| CN104750577B (en) | Any multidigit fault-tolerance approach and device of Large Copacity buffer storage on towards piece | |
| US10552243B2 (en) | Corrupt logical block addressing recovery scheme | |
| CN210136722U (en) | Memory device | |
| CN105575439B (en) | Method for correcting failure of storage unit and memory | |
| US20210366567A1 (en) | Read/write method and memory | |
| JP2013131095A (en) | Memory controller, memory device and memory control method | |
| US11886287B2 (en) | Read and write methods and memory devices | |
| CN109726040B (en) | Small-capacity OTPROM memory with fault-tolerant mechanism and fault-tolerant control method thereof | |
| US11899971B2 (en) | Method for reading and writing and memory device | |
| WO2021196661A1 (en) | Read-write method and memory device | |
| CN113495674B (en) | Read-write method and memory device | |
| CN113495677B (en) | Read-write method and memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |