CN110348039A - A kind of decoupling capacitor design method for printed circuit board - Google Patents
A kind of decoupling capacitor design method for printed circuit board Download PDFInfo
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- CN110348039A CN110348039A CN201910362082.7A CN201910362082A CN110348039A CN 110348039 A CN110348039 A CN 110348039A CN 201910362082 A CN201910362082 A CN 201910362082A CN 110348039 A CN110348039 A CN 110348039A
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- G06F30/39—Circuit design at the physical level
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Abstract
The invention discloses a kind of decoupling capacitor design methods for printed circuit board.This method comprises: decoupling capacitor type choosing method, 5MHz or less decoupling capacitor design method, in 5MHz-200MHz decoupling capacitor design method, the quantity computation method of each frequency range decoupling capacitor;For the exceeded section f of impedance of 100KHz-5MHza~fb(wherein fa< fb), selection self-resonant frequency is faCapacitor as maximum capacitor, the smallest capacitor of capacitance is 1uF, and during which every 10 times of journeys choose a capacitor;In the range of 5MHz or more 200MHz or less, according to condenser impedance map, capacitor is chosen, and as frequency increases, when first capacitor is in perception, chooses second capacitor in capacitive, and so on;The present invention can use less decoupling capacitor quantity and realize power distribution network impedance optimization, and without carrying out complicated calculating process, design time can be saved, is all furthermore standard capacitance by the decoupling capacitor that this method selects, the Material Cost of capacitor can be reduced.
Description
Technical field
The present invention relates to printed circuit board field of electromagnetic compatibility, more particularly to a kind of decoupling electricity for printed circuit board
Hold design method.
Background technique
The performance of power distribution network directly affects the performance of system, such as system reliability, signal-to-noise ratio and the bit error rate, and
The important indicators such as Electro Magnetic Compatibility.Plate level power supply channel impedance is excessively high and simultaneous switching noise crosses conference and brings serious power supply complete
Whole property problem can bring fatal influence to device and system job stability, and serious power distribution network design defect is also
It will lead to electromagnetic interference and form electromagnetic radiation in the higher resonance point of impedance, influence the work of controller printed circuit board internal circuit
Or the external world is transmitted to by cable.In practical applications, it reduces the main thought of power distribution network and method is addition decoupling
Capacitor.Crystal oscillator frequency, chip dominant frequency be not high in traditional printed circuit board, also uses in Power Integrity design simplest
" 0.1uF capacitor " mentality of designing adds the decoupling capacitor of a 0.1uF in each power pin, but with electronic technology and
The development of the communication technology, the traffic rate on printed circuit board are getting faster, and thus the synchronous open pipe noise problem of bring is also more
Add serious, traditional decoupling capacitor mentality of designing is no longer satisfied the requirement of developer, therefore there is an urgent need to a kind of effects more
Good decoupling capacitor optimization method.
Currently, common decoupling capacitor design method has: 1) BIG-V method, this method are gone out by adjusting mould group in voltage
The several other body capacitances of hundred microfarad ranges of addition at mouthful, and one or several 0.1uF capacitors, the party are added in each power pin
The advantage of method is the capacitor of multiple identical capacitances and joint conference reduces total equivalent series inductance, and in the antiresonance of capacitor
Point has extremely low impedance.But this method capacitance is dull, is difficult to control parallel resonance spike.2) MP method, this method utilize
The Low ESR that different capacitance capacitor parallel connections generate reaches decoupling purpose, and there are three types of MP method, respectively each 10 times of quantity
Grade chooses 1,2,3 kind of capacitance.But the decoupling capacitor that this method needs is too many.3) decoupling capacitor is carried out using optimization algorithm to set
Meter, carries out decoupling capacitor design using by genetic algorithm, Nature-Inspired algorithm etc..This method is many emulation
Software is used, but this method calculates the overlong time of decoupling capacitor consumption, and its capacitance being calculated is also not
Common standard value will increase the Material Cost of capacitor in practical applications.This paper presents one kind to be suitable for wide band go
Coupling capacitor fast selecting method.
As it can be seen that current decoupling capacitor design method all has some problems, the decoupling electricity of overlong time, needs is such as calculated
It is nonstandard etc. to hold capacitance excessive, being calculated.How the heavy difficult point of decoupling capacitor design is that quickly using less
Standard capacitance realize reduce power distribution network impedance purpose.
Summary of the invention
Based on this, it is necessary to which providing a kind of quickly can be effectively reduced power distribution using less standard capacitance
The decoupling capacitor design method of network impedance.
To achieve the above object, the present invention provides following schemes:
Step 1: the target impedance of power channel is determined by calculation;
Step 2: emulating to the circuit for being fitted without decoupling capacitor, the exceeded frequency range of impedance is found out, if n-th section exceeded
Initial frequency be f (n)a, termination frequency is f (n)b。
Step 3: design decoupling capacitor capacitance type.In view of the influence of ESL, 1nF capacitor below does not consider to make
With.1uF ceramic disc capacitor used below, 1uF electrolytic capacitor used above.It is in every 10 times of journeys for the capacitor type used
The standard capacitance capacitor for being 1,2.2,3.3,4.7,6.8,10 including capacitance.According to the dead resistance of selected capacitor, parasitic electricity
Sense and installation inductance draw the frequency domain impedance curve map of all capacitors.
Step 4: successively calculating the self-resonant frequency of every kind of capacitor, and according to self-resonant frequency from low to high by capacitor
Device sorts C (m), and m is the total number of decoupling capacitor, and correspondence self-resonant frequency is fSRF(m)。
Step 5: 5MHz or less decoupling capacitor designs.For the exceeded section f of impedance of 100KHz-5MHza~fb(wherein fa
< fb), selection self-resonant frequency is faCapacitor as maximum capacitor, the smallest capacitor of capacitance is 1uF, during which every 10 times of journeys
Choose a capacitor.
Step 6: in the range of 5MHz or more 200MHz or less, according to condenser impedance map, in exceeded frequency zones
The interior capacitor for finding all impedance values and being lower than target impedance, determines that these capacitor direct impedances are less than the frequency of target impedance
Rate range.As frequency increases, when first capacitor is in perception, second capacitor in capacitive is chosen, and so on.
Step 7: calculating the quantity of each frequency range decoupling capacitor.According to the equivalent series of target impedance and single capacitor electricity
Sense calculates the quantity that each capacitance needs shunt capacitance according to the following formula.
In formula, ESLmaxFor total equivalent series inductance of the capacitor after in parallel, unit nH;ESL is the equivalent string of single capacitor
Join inductance, unit nH;N is the quantity with type capacitor;ZtargetFor target impedance, unit Ohm;F is type decoupling
The highest frequency of capacitor effect frequency range.
Step 8: the 5th step to the 7th step is repeated, until power distribution network impedance is substantially lower than target impedance.
Compared with existing design method, the beneficial effects of the present invention are:
The present invention proposes a kind of decoupling capacitor design method for printed circuit board.This method can be according to printed circuit
The power distribution network impedance curve of plate, is quickly found out a kind of decoupling capacitor side that power distribution network impedance can be effectively reduced
Case.This method can use less decoupling capacitor quantity and realize power distribution network impedance optimization, and complicated without carrying out
Calculating process, design time can be saved, furthermore by this method select decoupling capacitor be all standard capacitance, can reduce
The Material Cost of capacitor.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without any creative labor, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is original of embodiment of the present invention power distribution network impedance curve and target impedance;
Fig. 2 is 1uF of embodiment of the present invention above section nominal capacitance impedance curve;
Fig. 3 is the part 1uF of the embodiment of the present invention or less nominal capacitance impedance curve;
Fig. 4 is the decoupling capacitor scheme equivalent circuit diagram that the embodiment of the present invention is chosen;
Fig. 5 is the impedance inhibitory effect figure of decoupling capacitor of embodiment of the present invention scheme.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
Embodiment 1:
Fig. 1 is that the embodiment of the present invention implements power distribution network impedance curve and target impedance before decoupling capacitor scheme;
Fig. 2 is 1uF of embodiment of the present invention above section nominal capacitance impedance curve;Fig. 3 is that the part 1uF of the embodiment of the present invention or less is nominal
Condensance curve.
Referring to Fig. 1, for there are allowances, target impedance is 0.2Ohm after presetting optimization.It is as follows according to the nominal capacitance of selection
Shown in table:
1uF above section nominal capacitance impedance curve is drawn, referring to fig. 2;The nominal electricity in the part 1uF or less is drawn according to upper table
Hold impedance curve referring to Fig. 3;According to the exceeded situation of 10KHz-5MHz, 100uF electrolytic capacitor is chosen;According to 5MHz-200MHz
Exceeded situation, according to step 6 choose 1nF, 3.3nF, 4.7nF, 33nF, 100nF and 470nF capacitance capacitor, according to mesh
Mark impedance calculates the quantity of each capacitance capacitor according to step 7, calculate 1nF capacitor quantity be 3,3.3nF capacitor quantity is 2,
4.7nF capacitor quantity is 2, remaining capacitor quantity is 1.
Decoupling capacitor scheme is finally calculated to obtain according to this method, as shown in the table
The decoupling capacitor scheme equivalent circuit diagram that the embodiment of the present invention is chosen is referring to fig. 4.Referring to Fig. 5, the embodiment of the present invention
After applying decoupling capacitor scheme, the impedance of power distribution network entirety is all declined, and all exceeded sections of former impedance
All complex target resistance requirements.
Used herein a specific example illustrates the principle and implementation of the invention, and above embodiments are said
It is bright to be merely used to help understand method and its core concept of the invention;At the same time, for those skilled in the art, foundation
Thought of the invention, there will be changes in the specific implementation manner and application range.In conclusion the content of the present specification is not
It is interpreted as limitation of the present invention.
Claims (5)
1. a kind of decoupling capacitor design method for printed circuit board characterized by comprising decoupling capacitor type selection side
Method, 5MHz or less decoupling capacitor design method, in 5MHz-200MHz decoupling capacitor design method, each frequency range decoupling capacitor
Quantity computation method.
2. a kind of decoupling capacitor design method for printed circuit board according to claim 1, which is characterized in that 1uF
Ceramic disc capacitor used below, 1uF electrolytic capacitor used above are every 10 times of journey internal standards appearance for the capacitor type used
It is worth capacitor, the frequency of all capacitors is drawn according to the equivalent series resistance of selected capacitor, equivalent series inductance and installation inductance
Domain impedance curve map.
3. a kind of decoupling capacitor design method for printed circuit board according to claim 1, which is characterized in that be directed to
The exceeded section f of the impedance of 100KHz-5MHza~fb(wherein fa< fb), selection self-resonant frequency is faCapacitor as maximum electricity
Hold, the smallest capacitor of capacitance is 1uF, and during which every 10 times of journeys choose a capacitor.
4. a kind of decoupling capacitor design method for printed circuit board according to claim 1, which is characterized in that
In the range of 5MHz or more 200MHz or less, according to condenser impedance map, all impedances are found in exceeded frequency separation
Value is lower than the capacitor of target impedance, determines that these capacitor direct impedances are less than the frequency range of target impedance.With frequency
It increases, when first capacitor is in perception, chooses second capacitor in capacitive, and so on.
5. a kind of decoupling capacitor design method for printed circuit board according to claim 1, which is characterized in that according to
The equivalent series inductance of target impedance and single capacitor calculates the quantity that each capacitance needs shunt capacitance according to formula.
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Cited By (3)
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CN112069761A (en) * | 2020-08-20 | 2020-12-11 | 之江实验室 | BGA packaging design method combined with decoupling capacitor |
CN112668275A (en) * | 2020-12-31 | 2021-04-16 | 芯和半导体科技(上海)有限公司 | Method for searching optimal substitute target capacitance in given capacitance set |
CN114757143A (en) * | 2022-06-16 | 2022-07-15 | 飞腾信息技术有限公司 | Decoupling capacitor selection method and device, server and readable storage medium |
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