CN110323205A - Semiconductor structure and the method for forming semiconductor structure - Google Patents

Semiconductor structure and the method for forming semiconductor structure Download PDF

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Publication number
CN110323205A
CN110323205A CN201810823819.6A CN201810823819A CN110323205A CN 110323205 A CN110323205 A CN 110323205A CN 201810823819 A CN201810823819 A CN 201810823819A CN 110323205 A CN110323205 A CN 110323205A
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China
Prior art keywords
conductive component
resistance
dielectric
dielectric layer
semiconductor structure
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CN201810823819.6A
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Chinese (zh)
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CN110323205B (en
Inventor
陈品彣
赖加瀚
傅美惠
洪敏修
郑雅忆
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract

The embodiment of the present invention generally provides the example embodiment for being related to the conductive component of metal contact element, through-hole, line etc. and being used to form the method for these conductive components.In embodiment, a kind of semiconductor structure includes the first dielectric layer, the first conductive component in the first dielectric layer, the second dielectric layer, the second conductive component in the second dielectric layer and the Resistance being arranged between the first conductive component and the second conductive component positioned at the first dielectric layer above substrate.Second conductive component is arranged between the first side wall of the second dielectric layer and the second sidewall of the second dielectric layer and abuts the first side wall and second sidewall.Resistance at least extends laterally to the second sidewall of the second dielectric layer from the first side wall of the second dielectric layer.The embodiment of the present invention also provides another semiconductor structure and a kind of method for forming semiconductor structure.

Description

Semiconductor structure and the method for forming semiconductor structure
Technical field
The present invention relates to semiconductor fields, and in particular it relates to semiconductor structure and the method for forming semiconductor structure.
Background technique
Semiconductor integrated circuit (IC) industry experienced exponential increase.Technological progress on IC material and design produces more For IC, wherein every generation all has circuit smaller than first prior-generation and more complicated.In IC development process, functional density (example Such as, on unit chip area interconnection devices quantity) usually increasing, while geometric dimension (for example, can be used manufacturing process wound The minimal modules (or line) built) reduce.This scaled technique, which usually passes through, improves production efficiency and reduction relevant cost To provide benefit.
Scaled with device, manufacturer has begun the group using new and different materials and/or material Conjunction is scaled in order to device.It is scaled, individually and new and different materials is combined also to bring previous generation The challenge that may do not occur under bigger geometric dimension.
Summary of the invention
According to an aspect of the present invention, a kind of semiconductor structure is provided, comprising: the first dielectric layer is located above substrate； First conductive component is located in the first dielectric layer；Second dielectric layer is located on the first dielectric layer；Second conductive component is located at the In two dielectric layers, the second conductive component be arranged between the first side wall of the second dielectric layer and the second sidewall of the second dielectric layer and Adjacent the first side wall and second sidewall；And Resistance, it is arranged between the first conductive component and the second conductive component, Resistance The second sidewall of the second dielectric layer is at least extended laterally to from the first side wall of the second dielectric layer.
According to another aspect of the present invention, a kind of semiconductor structure is provided, comprising: the first dielectric is located above substrate； First conductive component, passes through the first dielectric, and the first conductive component includes the first metal；Resistance is located at the first conductive component On, Resistance includes the first metal and substance；Second dielectric is located above the first dielectric；And second conductive component, it wears It crosses the second dielectric and contacts Resistance, Resistance and the bottom of the second conductive component are laterally coextensive.
According to another aspect of the present invention, a kind of method for forming semiconductor structure is provided, comprising: in the first dielectric The first conductive component is formed, the first conductive component includes metal；Second is formed above the first conductive component and the first dielectric Dielectric；It is formed across the second dielectric to the opening of the first conductive component；Offer includes leading across being open and entering first Substance in the metal of electrical components forms Resistance on the first conductive component；And it is formed in the opening to the second of Resistance Conductive component.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.It should Note that according to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, various parts Size can be arbitrarily increased or decreased.
Fig. 1 to Figure 13 is each rank in accordance with some embodiments during being used to form the illustrative methods of conductive component The view of each intermediate structure at section.
Figure 14 is the flow chart of the illustrative methods in accordance with some embodiments for being used to form conductive component.
Figure 15 to Figure 18 is in accordance with some embodiments during being used to form the another exemplary method of conductive component The sectional view of each intermediate structure at each stage.
Figure 19 is the flow chart of the another exemplary method in accordance with some embodiments for being used to form conductive component.
Figure 20 is energy dispersion X-ray spectrum (EDX) analysis of exemplary structure in accordance with some embodiments.
Specific embodiment
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme. The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second The embodiment that component is formed in a manner of directly contacting, and also may include can be with shape between the first component and second component At additional component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be Repeat reference numerals and/or character in each example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated The relationship between each embodiment and/or configuration discussed.
Moreover, for ease of description, can be used herein such as " in ... lower section ", " ... below ", " lower part ", " ... On ", the spatially relative terms such as " top " to be to describe an element or component and another (or other) member as shown in the figure The relationship of part or component.Other than the orientation shown in figure, spatially relative term is intended to include device in use or operation Different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space phase as used herein Corresponding explanation can similarly be made to descriptor.
In general, the present invention relates to the exemplary embodiment of the conductive component of metal contact element, through-hole, line etc. with And the method for being used to form those conductive components.In some instances, the conductive component at the surface by modifying conductive component Component form Resistance on conductive component.The conductive component the upper surface of being formed in dielectric layer above is formed as hindering Keep off area.Among other benefits, Resistance can also provide protection against chemicals etch and be formed with barrier layer thereon Conductive component.For example, the technique implemented in forming conductive component above can be used can penetrate dielectric above and The chemicals at the interface between conductive component.Resistance can prevent the conductive component below chemicals etch.It may be implemented His benefit.
At the front-end process (FEOL) and/or interlude processing procedure (MEOL) for being used for fin formula field effect transistor (FinFET) The example embodiment as described herein of described in the text up and down of conductive component is formed in reason.It can such as imitated with such as flat field Answer transistor (FET), vertical loopful grid (VGAA) FET, horizontal loopful grid (HGAA) FET, bipolar junction transistor (BJT), Implement other embodiments in the context of the different devices of diode, capacitor, inductor, resistor etc..In some cases Under, conductive component can be the part of the device of the plate of such as capacitor or the line of inductor.Furthermore, it is possible in back-end process (BEOL) it in processing and/or is used to form in any conductive component and implements some embodiments.The realization of some aspects of the invention It can be used in other techniques and/or in other devices.
Describe some modifications of illustrative methods and structure.Those skilled in the art will readily appreciate that, can It is modified with other made it is contemplated that in the range of other embodiments.Although describing embodiment of the method in a particular order, Each others embodiment of the method can be implemented with any logical order, and may include than it is described herein less or more More steps.In some of the figures, it is convenient to omit there is shown with component or component some reference markers to avoid obscuring other Component or component；This is to scheme for ease of description.
Fig. 1 to Figure 13 shows in accordance with some embodiments each during being used to form the illustrative methods of conductive component The sectional view of each intermediate structure at stage.Fig. 1 shows the perspective view of the intermediate structure at a stage of illustrative methods. As described below, intermediate structure is used in the realization of FinFET.Other structures can be realized in other example embodiments.
Intermediate structure includes the first and second fins 46 to be formed on a semiconductor substrate 42, wherein is being located at adjacent fins 46 Between semiconductor substrate 42 on have corresponding isolated area 44.First and second dummy grid stacks along fin 46 corresponding side Wall is simultaneously located at 46 top of fin.First and second dummy grid stacks include interface dielectric 48, dummy grid 50 and mask 52.
The block that semiconductor substrate 42 can be or may include (for example, with p-type or the n-type dopant) of doping or undopes Shape semiconductor substrate, semiconductor-on-insulator (SOI) substrate etc..In some embodiments, the semiconductor material of semiconductor substrate It may include such as elemental semiconductor of silicon (Si) or germanium (Ge)；Compound semiconductor；Alloy semiconductor or their combination.
Fin 46 is formed in semiconductor substrate 42.For example, etching semiconductor substrate using photoetching appropriate and etch process 42, so that forming groove between adjacent pairs of fin 46, and so that fin 46 is prominent from semiconductor substrate 42.Isolation Area 44 is formed as each and is respectively positioned in corresponding groove.Isolated area 44 may include or can be such as oxide (such as oxygen SiClx), the insulating materials of nitride etc. or their combination, and depositing operation appropriate can be used to deposit insulation material Material.Insulating materials can be recessed after deposition to form isolated area 44.Recessed insulating materials, so that fin 46 is from adjacent Prominent between isolated area 44, fin 46 can be at least partly described as the active area in semiconductor substrate 42 by this.In addition, isolation The top surface in area 44 can have the flat surface as shown in the figure generated by etch process, nonreentrant surface, concave surface (such as are recessed ) or their combination.One ordinarily skilled in the art will readily appreciate that process described above is only how to form fin 46 Example.In other instances, fin 46 can be formed by other techniques and may include outside heteroepitaxial structure and/or homogeneity Prolong structure.
Dummy grid stack is formed on fin 46.In replacement grid technology as described herein, work appropriate can be passed through Skill is sequentially formed each layer, and is then stacked those pattern layers at dummy grid by photoetching appropriate and etch process Part is to form interface dielectric 48, dummy grid 50 and mask 52 for dummy grid stack.For example, interface dielectric 48 can be with Including or can be silica, silicon nitride etc. or their multilayer.Dummy grid 50 may include or to can be silicon (such as more Crystal silicon) or another material.Mask 52 may include or can be silicon nitride, silicon oxynitride, carbonitride of silicium etc. or their combination.
In other instances, instead of dummy grid stack and/or other than dummy grid stack, gate stack can be with It is the operable gate stack (or more generally, gate structure) in first grid technology.In first grid technology, interface Dielectric 48 can be gate dielectric, and dummy grid 50 can be gate electrode.Process sequence landform appropriate can be passed through Those pattern layers are used at gate stack to be formed by photoetching appropriate and etch process at each layer, and then Gate dielectric, gate electrode and the mask 52 of operable gate stack.For example, gate dielectric may include or can be Silica, silicon nitride, high-k dielectric material etc. or their multilayer.High-k dielectric material may include hafnium (Hf), aluminium (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), the metal oxide of lead (Pb) or metal silicate, they multilayer or Their combination.Gate electrode may include or can be silicon (for example, doping or undoped polysilicon), metal-containing material (titanium, tungsten, aluminium, ruthenium etc.), their combination (such as silicide (can be subsequently formed)) or their multilayer.Mask 52 can To include or can be silicon nitride, silicon oxynitride, carbonitride of silicium etc. or their combination.
Fig. 1 is also shown in used in subsequent figure with reference to section.Section A-A is located at along opposite source/drain regions Between fin 46 in such as channel plane in.Fig. 2 to Figure 13 and Figure 15 to Figure 18 is shown corresponding with section A-A each The sectional view at each processing stage in a illustrative methods.Fig. 2 shows cutting for the intermediate structure of Fig. 1 at section A-A Face figure.
Fig. 3 shows to form gate spacer 54.Along the side wall of dummy grid stack (for example, interface dielectric 48, pseudo- grid The side wall of pole 50 and mask 52) and the formation gate spacer 54 above fin 46.For example, being located at isolated area 44 according to fin 46 On height, remaining gate spacer 54 can also be formed along the side wall of fin 46.For example, can be by conformally depositing For gate spacer 54 one or more layers and be etched anisotropically through one or more layers and form gate spacer 54.It may include for one of gate spacer 54 or multilayer or can be silicon oxide carbide, silicon nitride, silicon oxynitride, carbon nitrogen SiClx etc., their multilayer or their combination, and can be deposited by CVD, ALD or another deposition technique.Etch work Skill may include RIE, NBE or another etch process.
Fig. 4 shows the formation epitaxial source/drain 56 in fin 46.In the fin on opposite sides for being located at dummy grid stack Groove is formed in 46.It can be recessed by etch process.Etch process can be it is isotropic or anisotropic, Either can relative to semiconductor substrate 42 one or more crystal faces it is selective.Therefore, groove can be based on institute The etch process of implementation and have various cross section profiles.
The source/drain regions 56 of extension are formed in a groove.Epitaxial source/drain 56 may include or can be silicon Germanium, silicon carbide, silicon phosphorus, silicon-carbon phosphorus, pure or substantially pure germanium, group Ⅲ-Ⅴ compound semiconductor, II-VI compounds of group are partly led Body etc..Such as by metallorganic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapour phase epitaxy (VPE), Selective epitaxial growth (SEG) etc. or their combination, form extension by epitaxial grown material in a groove in a groove Source/drain regions 56.In some instances, epitaxial source/drain 56 can increase relative to fin 46 and can have and half The corresponding facet of the crystrallographic plane of conductor substrate 42.
Those of ordinary skill in the art also will readily appreciate that, it is convenient to omit the recessed and epitaxial growth of Fig. 4, and can be with Dummy grid stack and gate spacer 54 is used to form source/drain by implanting a dopant into fin 46 as mask Area.In some examples for implementing epitaxial source/drain 56, can also such as it be adulterated by the original position in extension growth period And/or by being implanted a dopant into after epitaxial growth in epitaxial source/drain 56 come doped epitaxial source/drain regions 56.It therefore, if applicable, can be by doping (if applicable, such as by during injection and/or epitaxial growth Doping in situ) and/or source/drain regions delimited by epitaxial growth (if applicable), can further delimit In the active area for wherein delimiting source/drain regions.
Fig. 5 shows to form contact etch stop layer (CESL) 60 and form the first interlayer dielectric above CESL 60 (ILD)62.In general, etching stopping layer (ESL) can stop losing forming such as contact or when through-hole and provide a kind of mechanism Carving technology.ESL can be formed by the dielectric material with the etching selectivity different from adjacent layer or component.Epitaxial source/ On the top surface on the surface of drain region 56, the side wall of gate spacer 54 and top surface, the top surface of mask 52 and isolated area 44 conformally Deposit CESL 60.CESL 60 may include or can be silicon nitride, carbonitride of silicium, silicon oxide carbide, carbonitride etc. or they Combination, and can be deposited by CVD, PECVD, ALD or another deposition technique.First ILD 62 may include or can be with It is silica, such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organic silicate glass (OSG), SiOxCy、 Spin-coating glass, spin on polymers, silicon carbon material, their compound etc. or their combination low k dielectric (for example, tool There is the material of the dielectric constant lower than silica).Spin coating, CVD, FCVD, PECVD, PVD or another deposition technique can be passed through To deposit the first ILD 62.
The first ILD 62 can be such as planarized by CMP after depositing the first ILD 62.First grid technology In, the top surface of the first ILD 62 can be on the top of CESL 60 and gate stack, and can be omitted following opposite In the processing that Fig. 6 and Fig. 7 is described.Therefore, the top of CESL 60 and the first ILD 62 can be retained above gate stack.
Fig. 6 is shown with replacement gate structure replacement dummy grid stack.First ILD 62 and CESL 60 be formed to have with The coplanar top surface in the top surface of dummy grid 50.The flatening process of such as CMP can be implemented so that the first ILD 62 and CESL 60 Top surface is flushed with the top surface of dummy grid 50.CMP can also remove the mask 52 on dummy grid 50 (and in some cases Under, the top of gate spacer 54).Therefore, pass through the top surface of the first ILD 62 and CESL 60 exposure dummy grid 50.
Using the dummy grid 50 by the first ILD 62 and CESL 60 exposure, such as pass through one or more etch process Remove dummy grid 50.It can be by removing dummy grid 50 to the selective etch process of dummy grid 50, wherein interface electricity Medium 48 is used as ESL, and subsequently, can be by optional to the selective different etch process of interface dielectric 48 Ground removes interface dielectric 48.Etch process can be such as RIE, NBE, wet etching or another etch process.Removing pseudo- grid The position of pole stack, which is between gate spacer 54, forms groove, and passes through the channel region of groove exposure fin 46.
Replacement gate structure is formed in the groove at the position of removal dummy grid stack.As shown, replacement grid Structure includes interface dielectric 70, gate dielectric 72, one or more optional conforma layers 74 and gate electrode 76.Along ditch Road area forms interface dielectric 70 on the side wall of fin 46 and top surface.Interface dielectric 70 can be such as interface dielectric 48 If (not removing), the oxide (for example, silica) formed by the thermal oxide or chemical oxidation of fin 46 and/or passed through Oxide (such as silica) that CVD, ALD, MBD or another deposition technique are formed, nitride (such as silicon nitride) and/or another Dielectric layer.
Can removal dummy grid stack position at groove in (for example, on the top surface of isolated area 44, interface electricity be situated between In matter 70 and on the side wall of gate spacer 54) and on the top surface of the first ILD 62, CESL 60 and gate spacer 54 Conformally gate dielectric layer 72.Gate dielectric 72 can be or may include silica, silicon nitride, high-k dielectric material, Their multilayer or other dielectric materials.High-k dielectric material may include hafnium (Hf), aluminium (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), the metal oxide of lead (Pb) or metal silicate, their multilayer or their combination.It can be with By ALD, PECVD, MBD or another deposition technique come gate dielectric layer 72.
It is then possible to conformally (and if more than one sequentially) deposit one or more on gate dielectric 72 A optional conforma layer 74.One or more optional conforma layers 74 may include one or more barrier layers and/or coating And one or more work function adjustment layer.One or more barrier layers and/or coating may include the nitridation of tantalum and/or titanium Object, silicon nitride, carbonitride and/or aln precipitation；Nitride, carbonitride and/or the carbide of tungsten；Or their group It closes；And it can be deposited by ALD, PECVD, MBD or another deposition technique.One or more work function adjustment layer can wrap Include or can be nitride, silicon nitride, carbonitride, aln precipitation, aluminum oxide and/or the aluminium carbide of titanium and/or tantalum； Nitride, carbonitride and/or the carbide of tungsten；Cobalt；Platinum；Deng or their combination；And ALD, PECVD, MBD can be passed through Or another deposition technique deposits.In some instances, coating is conformally formed on gate dielectric 72 (for example, TiN Layer)；It is conformally formed barrier layer (for example, TaN layers) on the cover layer；And it is subsequent conformally to sequentially form one over the barrier layer A or multiple work function adjustment layer.
In one or more optional conforma layer 74 (for example, above one or more work function adjustment layer) (such as fruits Form now) and/or above gate dielectric 72 layer for being used for gate electrode 76.Layer for gate electrode 76 can fill removal Remaining groove at the position of dummy grid stack.Layer for gate electrode 76 can be or may include such as tungsten, cobalt, The metal-containing material of aluminium, ruthenium, copper, their multilayer or their combination etc..ALD, PECVD, MBD, PVD or another can be passed through Deposition technique deposits the layer for gate electrode 76.Layer, one or more optional conforma layer 74 of the removal for gate electrode 76 With the part on the top surface for being located at the first ILD 62, CESL 60 and gate spacer 54 of gate dielectric 72.For example, flat Smooth chemical industry skill (such as CMP) can remove the layer for gate electrode 76, one or more optional conforma layers 74 and gate dielectric Part on 72 top surface for being located at the first ILD 62, CESL 60 and gate spacer 54.Therefore, it can be formed such as Fig. 6 institute What is shown includes the replacement grid of gate electrode 76, one or more optional conforma layers 74, gate dielectric 72 and interface dielectric 70 Pole structure.
Fig. 7, which is shown, forms the 2nd ILD above the first ILD 62, CESL 60, gate spacer 54 and replacement gate structure 80., can be in disposed thereons ESL such as the first ILD 62 although it is not shown, in some instances, and it can be in ESL The 2nd ILD 80 of disposed thereon.If realize if, ESL may include or can be silicon nitride, carbonitride of silicium, silicon oxide carbide, Carbonitride etc. or their combination, and can be deposited by CVD, PECVD, ALD or another deposition technique.2nd ILD 80 may include or can be silica, such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin coating glass Glass, spin on polymers, silicon carbon material, they compound, they compound etc. or their combination low k dielectric. The 2nd ILD 80 can be deposited by spin coating, CVD, FCVD, PECVD, PVD or another deposition technique.
Fig. 8 shows to be formed across the 2nd ILD80, the first ILD 62 and CESL 60 to expose epitaxial source/drain 56 At least partly and the 2nd ILD80 is passed through at least part of corresponding opening 82 and 84 of exposure replacement gate structure.For example, can With use photoetching and one or more etch process by the 2nd ILD 80, the first ILD 62 and CESL 60 it is patterned have open Mouth 82 and 84.
Fig. 9, which is shown, to be formed in opening 82 and 84 respectively to epitaxial source/drain 56 and leading to replacement gate structure Electrical components 90 and 92.For example, in the example shown, conductive component 90 includes adhesion layer 94, the barrier layer on adhesion layer 94 96, the silicide area 98 on epitaxial source/drain 56 and the conductive filling material 100 on barrier layer 96.Example Such as, in the example shown, conductive component 92 including adhesion layer 94, the barrier layer 96 on adhesion layer 94 and is located at barrier layer Conductive filling material 100 on 96.
It can be in opening 82 and 84 (for example, in 82 and 84 side wall that is open, the exposure table of epitaxial source/drain 56 On the exposed surface of face and replacement gate structure) and conformally deposition of adhesion 94 above the 2nd ILD 80.Adhesion layer 94 It can be or may include titanium, tantalum etc. or their combination, and can be sunk by ALD, CVD, PVD or another deposition technique Product.Barrier layer 96 can be conformally deposited (such as in opening 82 and 84 and above the 2nd ILD 80) on adhesion layer 94. Barrier layer 96 can be or may include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide etc. or their combination, and can lead to ALD, CVD or another deposition technique are crossed to deposit.In some instances, it can handle at least partly hindering to be formed for adhesion layer 94 Barrier 96.For example, such as nitriding process including nitrogen plasma process can be implemented to adhesion layer 94 with by adhesion layer 94 At least partly it is transformed into barrier layer 96.In some instances, adhesion layer 94 can be converted completely, so that without adhesion layer 94 Retain, and barrier layer 96 is adhesion/barrier, and in other instances, the part of adhesion layer 94 keeps not changing, to make The part and the barrier layer 96 on adhesion layer 94 for obtaining adhesion layer 94 retain together.
By reacting the top of epitaxial source/drain 56 with adhesion layer 94 and possible barrier layer 96, Ke Yi Silicide area 98 is formed on epitaxial source/drain 56.Annealing can be implemented to promote epitaxial source/drain 56 and adhesion layer 94 and/or barrier layer 96 reaction.
Conductive filling material 100 can be deposited on barrier layer 96 and fill opening 82 and 84.Conductive filling material 100 can To be or may include cobalt, tungsten, copper, ruthenium, aluminium, gold, silver, their alloy etc. or their combination, and can by CVD, ALD, PVD or another deposition technique deposit.After depositing conductive filling material 100, such as can be by using planarization Technique (such as CMP) removes extra conductive filling material 100, barrier layer 96 and adhesion layer 94.Flatening process can be from Extra conductive filling material 100, barrier layer 96 and adhesion layer 94 are removed on the top surface of two ILD 80.Therefore, conductive component 90 and 92 top surface and the 2nd ILD 80 can be coplanar.Conductive component 90 and 92 can be or be properly termed as contact, inserts Plug etc..
Although Fig. 8 and Fig. 9 show the conductive component 90 being formed simultaneously to epitaxial source/drain 56 and extremely replacement grid knot The conductive component 92 of structure individually and can be sequentially formed corresponding conductive component 90 and 92.For example, as shown in figure 8, can be with It is initially formed to the opening 82 of epitaxial source/drain 56, and as shown in figure 9, filling is open to be formed to epitaxial source/leakage The conductive component 90 of polar region 56.Then, as shown in figure 8, can be formed to the opening 84 of replacement gate structure, and such as Fig. 9 institute Show, filling opening is to form to the conductive component 92 of replacement gate structure.Another sequence of processing can be implemented.
Figure 10 shows to form ESL 110 and form metallization dielectric (IMD) 112 above ESL 110.Second The deposited on top ESL 110 of ILD 80 and conductive component 90 and 92.ESL 110 may include or can be silicon nitride, carbon nitrogen SiClx, silicon oxide carbide, carbonitride etc. or their combination, and CVD, PECVD, ALD or another deposition technique can be passed through To deposit.IMD 112 may include or can be silica, such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin-coating glass, spin on polymers, silicon carbon material, their compound, their compound etc. or their combination Low k dielectric.IMD 112 can be deposited by spin coating, CVD, FCVD, PECVD, PVD or another deposition technique.ESL 110 thickness can be in the range of from about 3nm to about 100nm, and the thickness of IMD 112 can be from about 5nm to about In the range of 100nm.The combination thickness of IMD112 and ESL110 can be in the range of from about 5nm to about 200nm.
Figure 11 shows the opening 120 and 122 being respectively formed across IMD 112 and ESL110 to conductive component 90 and 92.Example Such as, photoetching and one or more etch process can be used IMD 112 and ESL 110 is patterned with 120 Hes of opening 122.Etch process may include RIE, NBE, ICP etching, capacitance coupling plasma (CCP) etching, ion beam milling (IBE) Deng or their combination.Etch process can be anisotropic.In some instances, etch process may include using first The plasma of gas, wherein first gas includes carbon tetrafluoride (CF4), perfluoroethane (C2F6), octafluoropropane (C3F8), three Fluoromethane (CHF3), difluoromethane (CH2F2), fluomethane (CH3F), fluorocarbons is (for example, CxFy, wherein x can be from 1 to 5 In the range of and y can be in the range of from 4 to 8) etc. or their combination.It includes nitrogen that plasma, which can also use, (N2), hydrogen (H2), oxygen (O2), argon gas (Ar), xenon (Xe), helium (He), carbon monoxide (CO), carbon dioxide (CO2)、 The second gas of carbonyl sulfide (COS) etc. or their combination.In some instances, the stream of the flow velocity of first gas and second gas The ratio of speed can be in the range of from about 0.001 to about 1000.In some instances, the flow velocity of first gas can be from about In the range of 5 sccms (sccm) to about 500sccm, and the flow velocity of second gas can be from about In the range of 5sccm to about 500sccm.The pressure of plasma etching can be from about 5mTorr to the range of about 120mTorr It is interior.The power of plasma generator for plasma etching can be in the range of from about 30W to about 5000W.For The frequency of the plasma generator of plasma etching can be such as 40KHz, 2MHz, 13.56MHz or from about 12MHz To about 100MHz.The Substrate bias voltage of plasma etching can be in the range of from about 20V to about 500V simultaneously And with the duty cycle (duty cycle) in the range of from about 10% to about 60%.
Opening 120 and 122 can be such as cleaned by wet cleaning procedure and dry plasma process.Wet cleaning procedure can To include that semiconductor substrate 42 is immersed in the solution including mixed acid etc..During dipping, solution may be at from about 15 DEG C at the temperature in the range of about 65 DEG C.Semiconductor substrate 42 can be immersed in solution and be continued from about 5 seconds to about 200 Duration in the range of second.After impregnating in the solution, semiconductor substrate 42 can be rinsed in deionized water flushing.? After impregnating in solution, semiconductor substrate 42 can also be rinsed, in isopropanol (IPA) with drying of semiconductor substrate 42.
It can implement dry plasma process after wet cleaning procedure with further cleaning opening 120 and 122.For example, Plasma process can remove the oxide being formed in opening 120 and 122 (for example, on the surface of conductive filling material 100 On).In some instances, plasma process may include using comprising hydrogen (H2), nitrogen (N2) etc. or their combination The plasma of gas.In some instances, the flow velocity of gas can be in the range of from about 10sccm to about 10,000sccm. The pressure of plasma process can be in the range of from about 0.1mTorr to about 100Torr.For plasma process etc. The power of plasma generator can be in the range of from about 50W to about 1000W.Plasma for plasma process is sent out The frequency of raw device can be in the range of from about 350kHz to about 40MHz.The Substrate bias voltage of plasma process can be In the range of from about 0V to about 1kV and with duty cycle in the range of from about 30% to about 70%.
Figure 12, which is shown, forms Resistance on the part of the conductive component 90 and 92 by 120 and 122 exposure of opening respectively 130 and 132.It is utilized respectively the material component different from the conductive filling material 100 of following conductive component 90 and 92 and forms resistance Keep off area 130 and 132.It can be changed by being provided in conductive component 90 and 92 (for example, conductive filling material 100) by being open The substance of material component at the part of the top surface of the conductive components 90 and 92 of 120 and 122 exposures forms 130 He of Resistance 132.Resistance 130 and 132 is formed at the part on the surface by 120 and 122 exposure of opening respectively, without unexposed Resistance 130 and 132 is formed at the part on surface (for example, by the part on the surface covered ESL 110 and/or IMD 112).Cause This, in this example, the lateral dimension of Resistance 130 and 132 and the opening 120 and 122 close to the bottom of opening 120 and 122 Respective transversal size (for example, between side wall of ESL 110 and/or IMD 112) be coextensive.
In some instances, it is provided in conductive component 90 and 92 by the way that substance to be diffused into conductive component 90 and 92 The substance.In some instances, the not chemical immersion of plasma, corona treatment or another technology can be used to come in fact Apply the diffusion of substance.
In instances, the chemical immersion of plasma can be practiced without by CVD technique.Gas for chemical immersion Body mixture may include silane (SiH4) (as example) and such as argon gas carrier gas.Silane gas can provide siliceous object Matter, for being diffused into conductive component 90 and 92.For example, the silicon from silane can diffuse into conductive component 90 and 92 In and react with it, and the hydrogen from silane can be the by-product that silicon is reacted with conductive component 90 and 92, and can lead to It crosses the flowing of gas and purifies and/or hydrogen can also be diffused into conductive component 90 and 92 to carry out.Therefore, Resistance 130 It can be silicide area with 132.In the CVD technique of not plasma, the ratio of the flow velocity of the flow velocity and argon gas of silane gas Rate can be in the range of from about 0.01 to about 0.2.The flow velocity of silane gas can be from about 50sccm to the model of about 500sccm In enclosing and the flow velocity of argon gas can be in the range of from about 1000sccm to about 8000sccm.The pressure of CVD technique can be In the range of from about 10Torr to about 50Torr.The temperature of CVD technique can be in the range of from about 200 DEG C to about 450 DEG C.Not yet There is the duration of the chemical immersion of plasma can be in the range of from about 10 seconds to about 150 second.
In another example, can be implemented by the CVD technique (for example, pecvd process) with directional plasma Corona treatment.Admixture of gas for corona treatment may include silane (SiH4) (as example) and such as argon The carrier gas of gas.Similar to chemical immersion above, silane gas can provide silicon-containing material, for being diffused into conductive component In 90 and 92, and Resistance 130 and 132 can be silicide area.In the CVD technique with directional plasma, silane The ratio of the flow velocity of the flow velocity and argon gas of gas can be from about 10-3To in the range of about 0.2.The flow velocity of silane gas can be In the range of from about 1sccm to about 500sccm and the flow velocity of argon gas can be from about 1000sccm to the model of about 8000sccm In enclosing.The pressure of CVD technique can be in the range of from about 0.1Torr to about 100Torr.The temperature of CVD technique can from In the range of about 150 DEG C to about 300 DEG C.The power of plasma generator can in the range of from about 200W to about 500W, And the frequency of plasma generator can be in the range of from about 2MHz to about 40MHz (such as about 13.56MHz).Such as In the case where not biasing the substrate holder of CVD technique, corona treatment can be it is conformal, or such as pass through biasing lining Bottom retainer, corona treatment can be orientation.The duration of corona treatment can be from about 5 seconds to about 120 In the range of second.
In some instances, it can be mentioned in conductive component 90 and 92 by injecting a substance into conductive component 90 and 92 For the substance.It in instances, may include phosphorus, boron etc. for the substance of injection.In such an example, Implantation Energy can be In the range of from about 0.5keV to about 5keV, dose concentration is from about 1012cm-2To about 1017cm-2In the range of.
Different technologies can be used to change the top surface of the conductive component 90 and 92 by 120 and 122 exposure of opening Material component.In addition, different substances can be spread and/or be injected in above example and/or in different technologies Into conductive component 90 and 92.Such as, it is possible to implement germanium, nitrogen, carbon, arsenic, tin and/or other substances.As example, instead of or remove It can be implemented germane (GeH except silane in the previous case of chemical immersion and corona treatment4), germanium can be formed Compound is as Resistance 130 and 132.Furthermore, it is possible to inject germanium to form germanide as Resistance 130 and 132.It is similar Ground, nitrogen can be used for chemical immersion, corona treatment and injection to form metal nitride as Resistance 130 and 132.It can To implement other substances to form different compositions as Resistance 130 and 132.
In general, Resistance 130 and 132 can have MSxForm, wherein " M " is at the top surface of conductive component 90 and 92 Metal, " S " are the substances of the material component at the top surface for changing conductive component 90 and 92 implemented, and " x " is object The concentration of matter S.As specific example, conductive filling material 100 can be cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru) etc., with And substance can be silicon (Si), germanium (Ge), boron (B), arsenic (As), phosphorus (P), nitrogen (N), carbon (C), tin (Sn) etc..Therefore, Resistance 130 and 132 can be or may include such as CoSix、CoGex、CoBx、CoAsx、WSix、WGex、WBx、WAsx、CuSix、 CuGex、CuBx、CuAsx、RuSix、RuGex、RuBx、RuAsxDeng metal-semiconductor compounds；Such as CoPx、CoNx、CoCx、 WPx、WNx、WCx、CuPx、CuNx、CuCx、RuPx、RuNx、RuCxDeng metal-nonmetal compounds；Or such as CoSnx、WSnx、 CuSnx、RuSnxDeng metal-metal compounds.For any metal-semiconductor compounds, the value of x can be from about 1 to about 8 In the range of.The thickness of Resistance 130 and 132 can be in the range of from about 3nm to about 5nm.
Figure 13, which is shown, to be formed in opening 120 and 122 respectively to the conductive component 140 and 142 of Resistance 130 and 132.Such as Shown in figure, for example, each conductive component 140 and 142 includes conductive filling material 146.Conductive filling material 146 can be deposited on In opening 120 and 122 and fill opening 120 and 122.Conductive filling material 146 can be or may include tungsten, cobalt, copper, ruthenium, Aluminium, gold, silver, their alloy etc. or their combination, and CVD, ALD, PVD, plating or another deposition technique can be passed through To deposit.For example, can be removed by using the flatening process of CMP etc. more after depositing conductive filling material 146 Remaining conductive filling material 146.Flatening process can remove extra conductive filling material on the top surface of IMD 112 146.Therefore, the top surface of conductive component 140 and 142 and IMD 112 can be coplanar.Conductive component 140 and 142 can be or It is properly termed as contact, plug, conducting wire, conductive pad, through-hole etc..
In some instances, it is deposited on barrier layer and/or adhesion layer and is open 120 Hes in conductive filling material 146 Before in 122, barrier layer and/or adhesion layer can be formed in opening 120 and 122.Can opening 120 and 122 in (example Such as, on Resistance 130 and 132 and along the side wall of IMD 112) and barrier layer is conformally deposited above IMD 112 And/or adhesion layer.Barrier layer and/or adhesion layer can be or may include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide etc. or Their combination, and can be deposited by ALD, CVD or another deposition technique.Can also by from the top surface of IMD112 it The flatening process removal of the extra conductive filling material 146 of upper removal is located at barrier layer and/or adhesion layer above IMD112, And therefore barrier layer and/or adhesion layer can have the top surface coplanar with the top surface of conductive filling material 146 and IMD 112.
In this example, the respective base part of conductive component 140 and 142 has the phase with Resistance 130 and 132 respectively Answer the lateral dimension that lateral dimension is coextensive.This, which is usually followed, forms Resistance 130 and 132 and subsequent by opening 120 and 122 Conductive component 140 and 142 is formed in opening 120 and 122 respectively.
Figure 14 is the flow chart of the illustrative methods in accordance with some embodiments for being used to form conductive component.In operation 202 In, the first conductive component is formed in the first dielectric layer.It shows in figs. 8 and 9 and relative to Fig. 8 and Fig. 9 description operation 202 Example.For example, forming conductive component 90 in the 2nd ILD 80, the first ILD62 and CESL 60.
In operation 204, the second dielectric layer is formed in the first conductive component and the first dielectric layer.It is shown in FIG. 10 And the example relative to Figure 10 description operation 204.For example, in conductive component 90 and the 2nd ILD 80, the first ILD 62 and CESL 60 tops form ESL 110 and IMD 112.
In operation 206, opening is formed through the second dielectric layer to the first conductive component.It is shown in FIG. 11 and opposite In the example of Figure 11 description operation 206.For example, opening 120 is formed through ESL 110 and IMD 112 to conductive component 90.
In operation 208, Resistance is formed in the first conductive component by the opening exposure for passing through the second dielectric layer. The example for being shown in FIG. 12 and operating 208 relative to Figure 12 description.For example, in the conductive component 90 by 120 exposure of opening Upper formation Resistance 130.
In operation 210, the second conductive component is formed in the opening of the second dielectric layer and contacts Resistance.Scheming The example for being shown in 13 and operating 210 relative to Figure 13 description.For example, conductive component 140 is formed in opening 120 and contacts resistance Keep off area 130.
Figure 15 to Figure 18 shows in accordance with some embodiments during being used to form the another exemplary method of conductive component Each stage at each intermediate structure sectional view.It is handled as described previously by Fig. 9, and such as below in relation to figure Continue the processing as 15 descriptions.
Figure 15 shows the formation Resistance 130 and 132 at the top surface of conductive component 90 and 92.Such as retouched above with respect to Figure 12 Implement to form Resistance 130 and 132 as stating, and therefore, for simplicity, omitting further description herein.In the reality In example, Resistance 130 and 132 can accordingly be integrally formed through the top surface of conductive component 90 and 92.
Figure 16 shows to form ESL 110 and form IMD 112 above ESL 110.Respectively on the top of the 2nd ILD 80 Face and the formation ESL 110 above the Resistance 130 and 132 on conductive component 90 and 92.IMD is formed above ESL 110 112.As above with respect to implementing to form ESL 110 and IMD 112 described in Figure 10, and therefore, for simplicity, This omits further description.
Figure 17, which is shown, to be respectively formed across IMD 112 and ESL 110 to the Resistance 130 being located on conductive component 90 and 92 With 132 opening 120 and 122.As above with respect to implementing to be formed opening 120 and 122 described in Figure 11, and because This, for simplicity, omitting further description herein.
Figure 18, which is shown, to be formed in opening 120 and 122 respectively to the conductive component 140 and 142 of Resistance 130 and 132.Such as Conductive component 140 and 142 is formed above with respect to implementing like that described in Figure 13, and therefore, for simplicity, omitting herein Further description.In instances, conductive component 140 and 142 can not have cross corresponding to Resistance 130 and 132 respectively The lateral dimension coextensive to size.This may be because (for example, leading in the whole surface of the top surface of conductive component 90 and 92 Formed before dielectric layer in electrical components 90 and 92) Resistance 130 and 132 is formed, and be subsequently formed in opening 120 and 122 Conductive component 140 and 142 may need not be coextensive with the top surface of conductive component 90 and 92 respectively.
Figure 19 is the flow chart of the another exemplary method in accordance with some embodiments for being used to form conductive component.It is operating In 252, the first conductive component is formed in the first dielectric layer.It is shown in Fig. 8 and Fig. 9 and relative to Fig. 8 and Fig. 9 description operation 252 example.For example, forming conductive component 90 in the 2nd ILD 80, the first ILD 62 and CESL 60.
In operation 254, Resistance is formed on the first conductive component.It is shown in FIG. 15 and describes to grasp relative to Figure 15 Make 254 example.For example, forming block resistance area 130 on conductive component 90.
In operation 256, the second dielectric layer is formed in Resistance, the first conductive component and the first dielectric layer.Scheming The example for being shown in 16 and operating 256 relative to Figure 16 description.For example, in Resistance 130, conductive component 90 and the 2nd ILD 80, ESL 110 and IMD 112 is formed above the first ILD 62 and CESL 60.
In operation 258, the opening across the second dielectric layer to Resistance is formed.It is shown in FIG. 17 and relative to Figure 17 The example of description operation 258.For example, forming the opening 120 across ESL 110 and IMD 112 to Resistance 130.
In act 260, the second conductive component is formed in the opening of the second dielectric layer and contacts Resistance.Scheming The example for being shown in 18 and operating 260 relative to Figure 18 description.For example, conductive component 140 is formed in opening 120 and contacts resistance Keep off area 130.
Figure 20 is energy dispersion X-ray spectrum (EDX) analysis of exemplary structure in accordance with some embodiments.EDX analysis Across the conductive filling material 100 of the conductive filling material 146 of conductive component 140, Resistance 130 and conductive component 90.It is conductive Packing material 100 is the first metal (such as cobalt), has the first concentration distribution 300.It is used to form the substance of Resistance 130 (for example, silicon) has the second concentration distribution 302.Conductive filling material 146 is the second metal (such as tungsten), with third concentration Distribution 304.As can be seen that Resistance 130 includes substance and the first metal (for example, CoSi from EDX analysisx)。
Advantage may be implemented in some embodiments.Such as it can stop for removing the flat of extra conductive filling material 146 Chemical industry skill (for example, CMP) and any subsequent wet cleaning can be used can penetrate conductive component 140 and 142 and IMD 112 it Between respective interface wet chemical, especially if adhered between IMD 112 and conductive component 140 and 142 it is poor (such as when When being not carried out barrier layer and/or adhesion layer in conductive component 140 and 142).If wet chemical is penetrated into enough depths Degree, then in the case where barrier layer is not present, wet chemical can reach and etch following conductive component 90 and 92.Such as In some examples provided herein, Resistance 130 and 132 can provide the different materials component that may be used as etch stop, It can prevent wet chemical from etching following conductive component 90 and 92.In addition, in some embodiments, such as when Resistance 130 When with 132 being silicide, Resistance 130 and 132 can provide improvement between following conductive component 90 and 92 and IMD 112 Adherency.Even further, such as when implementing selective deposition technique to be used to deposit conductive filling material 146, stop Area 130 and 132 can provide more favorable surface for deposition conductive filling material 146.This can improve pattern load and can be with Enhance the growth of film.Therefore, Resistance 130 and 132 can provide more robust structure.
One embodiment is a kind of structure.The structure includes the first dielectric layer above the substrate, is located at the first dielectric The first conductive component in layer, the second conduction positioned at the second dielectric layer of the first dielectric layer, in the second dielectric layer Component and the Resistance being arranged between the first conductive component and the second conductive component.The setting of second conductive component is situated between second Between the first side wall of electric layer and the second sidewall of the second dielectric layer and the first side wall of adjacent second dielectric layer and second is situated between The second sidewall of electric layer.Resistance at least extends laterally to second side of the second dielectric layer from the first side wall of the second dielectric layer Wall.
One embodiment is a kind of method.The first conductive component is formed in the first dielectric layer.It is conductive by modification first The component of component and form Resistance on the first conductive component.The second conductive component is formed in the second dielectric layer.First Dielectric layer forms the second dielectric layer.Second conductive component contacts Resistance.
Another embodiment is a kind of structure.The structure includes the first dielectric above the substrate, passes through the first electricity and be situated between First conductive component of matter, the Resistance on the first conductive component, the second dielectric on the first dielectric and Across the second dielectric and contact the second conductive component of Resistance.First conductive component includes the first metal.Resistance includes First metal and substance.Resistance and the bottom of the second conductive component are laterally coextensive.
Other embodiment is a kind of method.The first conductive component is formed in the first dielectric.First conductive component packet Include metal.The second dielectric is formed above the first conductive component and the first dielectric.It is formed across the second dielectric layer to first The opening of conductive component.It includes providing by being open and entering the first conductive part that Resistance is formed on the first conductive component Substance in the metal of part.It is formed in the opening to the second conductive component of Resistance.
According to an aspect of the present invention, a kind of semiconductor structure is provided, comprising: the first dielectric layer is located above substrate； First conductive component is located in the first dielectric layer；Second dielectric layer is located on the first dielectric layer；Second conductive component is located at the In two dielectric layers, the second conductive component be arranged between the first side wall of the second dielectric layer and the second sidewall of the second dielectric layer and Adjacent the first side wall and second sidewall；And Resistance, it is arranged between the first conductive component and the second conductive component, Resistance The second sidewall of the second dielectric layer is at least extended laterally to from the first side wall of the second dielectric layer.
According to one embodiment of present invention, Resistance is not arranged between the first conductive component and the second dielectric layer.
According to one embodiment of present invention, Resistance is at least partially disposed on the first conductive component and the second dielectric layer Between, and Resistance is not arranged between the first dielectric layer and the second dielectric layer.
According to one embodiment of present invention, the first conductive component includes metallic element, and Resistance includes semiconductor Element and metallic element identical with the metallic element of the first conductive component.
According to one embodiment of present invention, the first conductive component includes metallic element, and Resistance includes nonmetallic Element and metallic element identical with the metallic element of the first conductive component.
According to one embodiment of present invention, the first conductive component includes metallic element, and Resistance includes and first The different metallic element of the metallic element of conductive component and identical metallic element.
According to one embodiment of present invention, the thickness of Resistance is in the range of from 3nm to 5nm.
According to one embodiment of present invention, the first conductive component includes metallic element, and Resistance include substance and Metallic element identical with the metallic element of the first conductive component, substance include silicon, germanium, boron, arsenic, phosphorus, nitrogen, carbon, tin or they At least one of combination.
According to one embodiment of present invention, Resistance includes silicide.
According to another aspect of the present invention, a kind of semiconductor structure is provided, comprising: the first dielectric is located above substrate； First conductive component, passes through the first dielectric, and the first conductive component includes the first metal；Resistance is located at the first conductive component On, Resistance includes the first metal and substance；Second dielectric is located above the first dielectric；And second conductive component, it wears It crosses the second dielectric and contacts Resistance, Resistance and the bottom of the second conductive component are laterally coextensive.
According to one embodiment of present invention, substance is semiconductor, and Resistance is metal-semiconductor compound.
According to one embodiment of present invention, substance is nonmetallic, and Resistance is metal-nonmetal compounds.
According to one embodiment of present invention, substance is second metal different from the first metal, and Resistance is metal -- Au Belong to compound.
According to one embodiment of present invention, the thickness of Resistance is in the range of from 3nm to 5nm.
According to another aspect of the present invention, a kind of method for forming semiconductor structure is provided, comprising: in the first dielectric The first conductive component is formed, the first conductive component includes metal；Second is formed above the first conductive component and the first dielectric Dielectric；It is formed across the second dielectric to the opening of the first conductive component；Offer includes leading across being open and entering first Substance in the metal of electrical components forms Resistance on the first conductive component；And it is formed in the opening to the second of Resistance Conductive component.
According to one embodiment of present invention, it provides through the substance in the metal that is open and enters the first conductive component It is impregnated including metal is exposed to aerochemistry by opening, wherein substance is from the gas diffusion that aerochemistry impregnates to metal In.
According to one embodiment of present invention, it provides through the substance in the metal that is open and enters the first conductive component Including metal is exposed to corona treatment by being open, wherein substance from the plasma diffusion of corona treatment to In metal.
According to one embodiment of present invention, it provides through the substance in the metal that is open and enters the first conductive component Including injecting a substance into metal.
According to one embodiment of present invention, substance includes silicon-containing material.
According to one embodiment of present invention, Resistance is silicide.
Foregoing has outlined the feature of several embodiments so that those skilled in the art may be better understood it is of the invention each Aspect.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or modify Implement and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Art technology Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from of the invention In the case where spirit and scope, they can make a variety of variations, replace and change herein.

Claims (10)

1. a kind of semiconductor structure, comprising:
First dielectric layer is located above substrate；
First conductive component is located in first dielectric layer；
Second dielectric layer is located on first dielectric layer；
Second conductive component is located in second dielectric layer, and second dielectric layer is arranged in second conductive component Between the first side wall and the second sidewall of second dielectric layer and abut the first side wall and the second sidewall；And
Resistance is arranged between first conductive component and second conductive component, and the Resistance is at least from described The first side wall of second dielectric layer extends laterally to the second sidewall of second dielectric layer.
2. semiconductor structure according to claim 1, wherein the Resistance be not arranged in first conductive component and Between second dielectric layer.
3. semiconductor structure according to claim 1, wherein the Resistance is at least partially disposed on described first and leads Between electrical components and second dielectric layer, and the Resistance is not arranged in first dielectric layer and second dielectric Between layer.
4. semiconductor structure according to claim 1, wherein first conductive component includes metallic element, and institute Stating Resistance includes semiconductor element and metallic element identical with the metallic element of first conductive component.
5. semiconductor structure according to claim 1, wherein first conductive component includes metallic element, and institute Stating Resistance includes nonmetalloid and metallic element identical with the metallic element of first conductive component.
6. semiconductor structure according to claim 1, wherein first conductive component includes metallic element, and institute Stating Resistance includes the metallic element and identical metallic element different from the metallic element of first conductive component.
7. semiconductor structure according to claim 1, wherein the thickness of the Resistance is in the range from 3nm to 5nm It is interior.
8. semiconductor structure according to claim 1, wherein first conductive component includes metallic element, and institute Stating Resistance includes substance and metallic element identical with the metallic element of first conductive component, the substance include silicon, At least one of germanium, boron, arsenic, phosphorus, nitrogen, carbon, tin or their combination.
9. a kind of semiconductor structure, comprising:
First dielectric is located above substrate；
First conductive component, passes through first dielectric, and first conductive component includes the first metal；
Resistance is located on first conductive component, and the Resistance includes first metal and substance；
Second dielectric is located above first dielectric；And
Second conductive component across second dielectric and contacts the Resistance, the Resistance and second conduction The bottom of component is laterally coextensive.
10. a kind of method for forming semiconductor structure, comprising:
The first conductive component is formed in the first dielectric, first conductive component includes metal；
The second dielectric is formed above first conductive component and first dielectric；
It is formed across second dielectric to the opening of first conductive component；
It includes providing across the opening and entering first conductive part that Resistance is formed on first conductive component Substance in the metal of part；And
It is formed in said opening to the second conductive component of the Resistance.
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