CN110321296A - Method for writing data and solid state hard disk - Google Patents
Method for writing data and solid state hard disk Download PDFInfo
- Publication number
- CN110321296A CN110321296A CN201810279244.6A CN201810279244A CN110321296A CN 110321296 A CN110321296 A CN 110321296A CN 201810279244 A CN201810279244 A CN 201810279244A CN 110321296 A CN110321296 A CN 110321296A
- Authority
- CN
- China
- Prior art keywords
- data
- accelerator
- writing
- written
- hard disk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
This disclosure relates to a kind of method for writing data and solid state hard disk, the load of the processor for mitigating solid state hard disk.The described method includes: the processor of the solid state hard disk receives the instruction for data to be written；The processor notifies the accelerator of writing of the solid state hard disk that the data are written；The cache unit write accelerator and the data are written to the solid state hard disk from the input/output port of the solid state hard disk.
Description
Technical field
This disclosure relates to field of computer technology, and in particular, to a kind of method for writing data and solid state hard disk.
Background technique
With the high speed development of data storage technology, solid state hard disk (Solid State Drives, SSD) is read due to having
The features such as writing rate is fast, anti-vibration, low-power consumption, noiseless, low in calories and light weight, has been widely used in military, vehicle
The fields such as load, industry, medical treatment and aviation.
Solid state hard disk can have one or more processors (Central Processing Unit, CPU), processor
It is equivalent to the brain of solid state hard disk, plans as a whole solid state hard disk and completes various work.For example, in the caching for writing data into solid state hard disk
When unit, the processor of solid state hard disk is needed to complete to write data into the operation of cache unit, for example, configuration write-in cache unit
Address, inquiry write state etc., the operation for needing processor to execute is more, and the processor load of solid state hard disk is heavier.
Summary of the invention
Purpose of this disclosure is to provide a kind of method for writing data and solid state hard disks, for mitigating the processor of solid state hard disk
Load.
In a first aspect, providing a kind of method for writing data, application and solid state hard disk, comprising:
The processor of the solid state hard disk receives the instruction for data to be written；
The processor notifies the accelerator of writing of the solid state hard disk that the data are written；
It is described to write accelerator the slow of the solid state hard disk is written into from the input/output port of the solid state hard disk in the data
Memory cell.
Optionally, the accelerator of writing includes direct memory access DMA interface, to control with the DMA of the solid state hard disk
Device connection, the caching write accelerator and the data are written to the solid state hard disk from the input/output port of the solid state hard disk
Unit, comprising:
The accelerator of writing determines the destination address for being located at the cache unit according to the data volume of the data；
It is described to write dma controller described in Accelerator control for the corresponding caching sky of the data write-in destination address
Between.
Optionally, the method also includes:
The processor writes accelerator and sends the cache unit according to the storage state of the cache unit, Xiang Suoshu
Available address；
The accelerator of writing records the available address；
The accelerator of writing determines the destination address for being located at the cache unit according to the data volume of the data, comprising:
The accelerator of writing determines the destination address according to the data volume of the data from the available address.
Optionally, the method also includes:
The accelerator of writing obtains data writing progress, wherein the data writing progress characterization has been written into described slow
Deposit space data volume account for the data data volume ratio；
The accelerator of writing records the data writing progress；
The accelerator of writing is to the processor transmission data writing progress.
Optionally, the method also includes:
It is described write accelerator and the data volume of the cache unit is written reaches the first preset threshold when, it is described to write accelerator
The processor is notified to handle the data for having been written into the cache unit.
Optionally, after the instruction that the processor of the solid state hard disk receives for data to be written, further includes:
Whether the processor judges the data volume of the data less than the second preset threshold；
The processor notifies the accelerator of writing of the solid state hard disk that the data are written, comprising:
When the data volume of the data is less than second preset threshold, accelerator is write described in the processor notice and is write
Enter the data.
Optionally, the method also includes:
The accelerator of writing sends the storage address for having been written into the data of the cache unit to the processor；
The processor obtains the data for having been written into the cache unit, to having been written into according to the storage address
The data for stating cache unit are handled.
Optionally, the method also includes:
The accelerator of writing receives the state control instruction that the processor is sent；
It is described to write accelerator halted state or operating status are switched to according to the control instruction；
It is described to write accelerator the slow of the solid state hard disk is written into from the input/output port of the solid state hard disk in the data
Memory cell, comprising:
The caching list is written from the input/output port when in operating status, by the data in the accelerator of writing
Member.
Second aspect provides a kind of solid state hard disk, comprising: input/output port interconnected, writes acceleration at cache unit
Device and processor；Wherein,
The processor is used to receive the instruction for data to be written, and writes accelerator described in notice and the data are written；
The accelerator of writing is for being written the cache unit from the input/output port for the data.
Optionally, the solid state hard disk further includes direct memory access dma controller, and the accelerator of writing is connect by DMA
Mouth is connect with the dma controller, and the accelerator of writing is used for:
According to the data volume of the data, the destination address for being located at the cache unit is determined；
It controls the dma controller and the corresponding spatial cache of the destination address is written into the data.
Optionally, the processor is also used to the storage state according to the cache unit, and Xiang Suoshu writes accelerator transmission
The available address of the cache unit；
The accelerator of writing is also used to record the available address；
The accelerator of writing is used for:
According to the data volume of the data, the destination address is determined from the available address.
Optionally, the accelerator of writing is also used to:
Obtain data writing progress, wherein the data writing progress characterization has been written into the data of the spatial cache
Amount accounts for the ratio of the data volume of the data；
Record the data writing progress；
The data writing progress is sent to the processor.
Optionally, the accelerator of writing is also used to:
It is described write accelerator and the data volume of the cache unit is written reaches the first preset threshold when, notify the processing
Device handles the data for having been written into the cache unit.
Optionally, the processor is also used to:
After receiving the instruction for data to be written, judge the data volume of the data whether less than the second default threshold
Value；
When the data volume of the data is less than second preset threshold, accelerator is write described in notice, the number is written
According to.
Optionally, the accelerator of writing is also used to send depositing for the data for having been written into the cache unit to the processor
Store up address；
The processor is also used to the data for having been written into the cache unit be obtained, to according to the storage address
The data that the cache unit is written are handled.
Optionally, the accelerator of writing is also used to:
Receive the state control instruction that the processor is sent；
Halted state or operating status are switched to according to the control instruction；
When in operating status, the cache unit is written into from the input/output port in the data.
In the embodiment of the present disclosure, the processor of solid state hard disk can be notified when receiving the instruction for data to be written
Solid state hard disk writes accelerator data are written, and then data are written in cache unit from input/output port by writing accelerator.
In this way, it joined in solid state hard disk and write accelerator, then in data to be written, the processor of solid state hard disk
It need to only notify to write accelerator, specific write operation can be completed by writing accelerator, and then reduce the load of processor, together
When, write operation is carried out due to the processor without solid state hard disk, processor available free can go to complete other work, solid-state
The data-handling efficiency of hard disk is higher.
Other feature and advantage of the disclosure will the following detailed description will be given in the detailed implementation section.
Detailed description of the invention
Attached drawing is and to constitute part of specification for providing further understanding of the disclosure, with following tool
Body embodiment is used to explain the disclosure together, but does not constitute the limitation to the disclosure.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of solid state hard disk in the embodiment of the present disclosure.
Fig. 2 is the flow chart of method for writing data in the embodiment of the present disclosure.
Fig. 3 is to write accelerator structure schematic diagram in the embodiment of the present disclosure.
Specific embodiment
It is described in detail below in conjunction with specific embodiment of the attached drawing to the disclosure.It should be understood that this place is retouched
The specific embodiment stated is only used for describing and explaining the disclosure, is not limited to the disclosure.
Before being illustrated to the method for writing data that the disclosure provides, first pair this disclosure relates to the relevant technologies into
Row explanation.
Solid state hard disk can be the hard disk made of solid-state electronic storage chip array.Currently, the storage of solid state hard disk is situated between
Matter generally can there are two types of, one is using flash memory (FLASH) chip be used as storage medium, another be use dynamic random
It accesses memory (Dynamic Random Access Memory, DRAM) and is used as storage medium.Wherein, using FLASH chip
As the solid state hard disk of storage medium, that is, usually said SSD, its appearance can be made into a variety of apperances, such as:
The patterns such as laptop hard, micro harddisk, storage card, USB flash disk.
Solid state hard disk can have one or more processors, for the solid state hard disk with multiple processors, no
With processor can complete different functions, for example, segment processor completes input/output port management and by data from connecing
Functions, the segment processors such as mouth write-in solid state hard disk complete FTL (Flash Translation Layer, the flash memory of storing data
Conversion layer) operation and management function, segment processor complete multichannel flash cell management and data storage function, etc.
Deng.In the embodiment of the present disclosure, in the case where solid state hard disk has multiple processors, signified processor be can be for managing
The processor of input/output port.
Solid state hard disk is commonly configured with cache unit, for example can be DDR (Double Data Rate, double data speed
Rate) memory, or can be RAM (Random Access Memory, random access memory), etc..It is write by data
When entering solid state hard disk, can first it write data into the cache unit of solid state hard disk, then when reading data, it can be first from caching
The data of needs are searched in unit, if having found can directly read, the speed of service of cache unit is very fast, therefore can
Solid state hard disk is helped quickly to run.Currently, the operation for writing data into cache unit is completed by processor, then handling
Device needs to carry out the operation such as address administration, state-detection, for processor, heavy load.
Referring to Figure 1, in order to reduce solid state hard disk processor load, the disclosure provides a kind of solid state hard disk 100, wraps
It includes input/output port 101 interconnected, cache unit 102, write accelerator 103 and processor 104, input/output port 101
It such as can be PCIe mouthfuls, cache unit 102 for example can be DDR memory etc..Each component is mutually connected can
To be as shown in Figure 1, each component is connect with bus (such as AXI bus, etc.), write accelerator 103 again individually with input
Delivery outlet 101 connects.The embodiment of the present disclosure is not construed as limiting the mode of each component connection, as long as can be in communication with each other.
Solid state hard disk 100 is able to carry out the method for writing data of disclosure offer, provides with reference to the accompanying drawing the disclosure
Method for writing data be described in detail.
Fig. 2 is referred to, Fig. 2 is a kind of flow chart of method for writing data shown according to an exemplary embodiment, the party
Method can be applied to solid state hard disk 100 shown in FIG. 1.As shown in Fig. 2, method includes the following steps:
Step S21: the processor 104 of solid state hard disk 100 receives the instruction for data to be written.
Step S22: processor 104 notifies the accelerator 103 of writing of solid state hard disk 100 that data are written.
Step S23: accelerator 103 is write by data, solid state hard disk 100 is written from the input/output port 101 of solid state hard disk 100
Cache unit 102.
It in the embodiment of the present disclosure, is increased in solid state hard disk 100 and writes accelerator 103, for writing the inside of accelerator 103
How structure arranges that the embodiment of the present disclosure is not construed as limiting actually, writes data into cache unit 102 as long as can be realized
Function.Fig. 3 is referred to, Fig. 3 is a kind of structure for illustratively writing accelerator 103, and writing accelerator 103 for example may include
Bus interface, DMA (Direct Memory Access, direct memory access) interface, state of a control register, input/output
Information buffer, input address buffer, system control module, information data processing module, data DMA control module.Under
It, will be for writing accelerator 103 and be structure shown in Fig. 3, to the data for the solid state hard disk 100 that the disclosure provides in the explanation of text
Wiring method is described in detail, certainly, only schematical for module shown in Fig. 3 division, in actual implementation may be used
To have other module division modes and function implementation.
When data will be written into solid state hard disk 100 in host, host can send write-in data to solid state hard disk 100
Instruction, then the instruction for data to be written can be received by the processor 104 of solid state hard disk 100.Processor 104 is receiving
After the instruction of data is written, notice writes accelerator 103, for example processor 104 is connect by bus with accelerator 103 is write,
Processor 104 can send the order of write-in data to the input information buffer for writing accelerator 103 shown in Fig. 3.Input
Information buffer can parse the information for needing the data block read and write, and write accelerator 103 and then know to the letter of the data of write-in
Breath.Inputting information buffer can be with asynchronous design method be used, as long as that is, processor 104 is in the case where command queue is discontented
Information can be sent to input information buffer, the mode that substitution both sides shake hands promotes the speed of data processing.
The operation of specific write-in data can be carried out by writing accelerator 103, i.e., by writing accelerator 103 for data from defeated
Enter delivery outlet 101 and cache unit 102 is written, in this way, can reduce the load of processor 104, processor 104 available free can be gone
Other work are completed, the data-handling efficiency of solid state hard disk 100 is higher.
Optionally, solid state hard disk 100 can be the solid state hard disk 100 configured with dma controller, then writing accelerator 103
It may include DMA interface, to be connect with the dma controller of solid state hard disk 100.It, can be by writing accelerator 103 when data are written
According to the data volume for the data to be written, determines the destination address for being located at cache unit 102, then controlled by writing accelerator 103
Dma controller writes data into the corresponding spatial cache of destination address.
Accelerator 103 shown in Fig. 3 of writing can be connect by DMA interface with dma controller, and dma controller does not have number
It, can only be based on order come moving data according to the ability of processing.Therefore, writing accelerator 103 can be first according to the data to be written
The destination address of cache unit 102 is written to determine for data volume, and writing accelerator 103 can be by inputting information buffer receiving area
The instruction that device 104 is sent is managed, and then knows the data volume of data to be written, for example, needing the space of 1KB to be written to store
Data, then the destination address that can accommodate 1KB data positioned at cache unit 102 can be determined by writing accelerator 103.It determines
Destination address and then control DMA move data from input/output interface corresponding to the destination address in cache unit 102
In spatial cache, and then realize the write-in of data.In this way, it is configured without the processor 104 of solid state hard disk 100
DMA alleviates the load of the processor 104 of solid state hard disk 100, and being conducive to processor 104 can continue to execute other tasks,
Promote the processing speed of solid state hard disk 100.
It optionally, can be by for writing how accelerator 103 determines that destination address, the embodiment of the present disclosure are not construed as limiting
Manage device 104 according to the storage state of cache unit 102, to the available address for writing the transmission cache unit 102 of accelerator 103, then
It writes accelerator 103 and records available address.Accelerator 103 is write when determining destination address, it can be according to the data volume of data, from can
With destination address determining in address.
Processor 104 can read the storage state of cache unit 102, and then know cache unit 102 which is slow actually
It is available to deposit the space free time.In the embodiment of the present disclosure, processor 104 can be obtained when the free time in cache unit 102 can
With address, then available address is sent to and writes accelerator 103, write accelerator 103 and store available address, to need
Address distribution is carried out when data are written.For example the input address buffer of accelerator 103 can be write as shown in Figure 3 to store
Available address, input address buffer can equally use asynchronous design method, as long as processor 104 is discontented in command queue
In the case where available address can be sent to input address buffer, the mode shaken hands of substitution both sides promote data processing
Speed.
That is, the current available address of cache unit 102 is stored in input address buffer, then believing in input
Breath buffer receive write-in data order after, can by the data that information data processing module will be written information and
Current available address informs system control module, by system control module come the data volume size based on the data to be written,
It is determined to accommodate the destination address for the data to be written from available address, then by the source address of data, destination address, number
It packages according to information such as packet sizes according to DMA transfer mode, dma controller is controlled by data DMA control module and is counted
According to move.In this way, available complete the operations such as configuration dma controller, distribution destination address, mitigation processing by writing accelerator 103
The load of device 104, processor 104 are able to carry out other orders, promote the efficiency of 100 data processing of solid state hard disk.
Optionally, data writing progress can also be obtained by writing accelerator 103, and data writing progress characterization has been written into caching
The data volume in space accounts for the ratio of the data volume of data, 103 usable record data writing progress of accelerator is write, then to processor
104 send data writing progress.
As shown in Figure 3 writes accelerator 103, writes data into cache unit writing the control dma controller of accelerator 103
When 102, the available data writing progress of data DMA control module, and then know data are written with how many, residue is how much, number
It is written successfully according to being, or write-in failure etc. information.The information that data DMA control module can will acquire is sent to system control
Molding block, then stored by state of a control register, certainly, the data that data DMA control module can also directly will acquire
Writing progress is sent to status register and is stored.Processor 104 can be known by interacting with state of a control register
Data writing progress, so that processor 104 can control the various states that data are written in accelerator 103 of writing, solid state hard disk
100 data-handling capacity is stronger.
Optionally, when the data volume for writing the write-in cache unit 102 of accelerator 103 reaches the first preset threshold, acceleration is write
Device 103 can be handled the data for having been written into cache unit 102 with notifier processes device 104.
For small bag data lesser for data volume, one small bag data of every write-in is required to carry out configuration DMA control
The operations such as device, configuration writing address, status monitoring, if these operations are completed by processor 104, each operation is more
Cycles per instruction carries out, the transmission for short packet data, the meeting frequent progress aforesaid operations of processor 104, and efficiency is more low.This public affairs
It opens in embodiment, aforesaid operations can be completed by writing accelerator 103, writing accelerator 103 can be monocyclic operation, relatively
In processor 104, data are written using accelerator 103 is write being capable of effective raising efficiency.
In order to preferably promote the efficiency that solid state hard disk 100 writes data, when small bag data is written by writing accelerator 103,
It handling without every write-in equal notifier processes device 104 of one data, small bag data can be accumulated by writing accelerator 103,
Write-in small bag data data volume accumulation reach the first preset threshold after, reinform processor 104 to have been written into caching
The data of unit 102 are handled.First preset threshold can be preset any threshold, can be solid state hard disk 100
Set when leaving the factory, perhaps can also by user's sets itself as needed or be also possible to hard by solid-state
Disk 100 according to storage state dynamic configuration, etc., the embodiment of the present disclosure is not construed as limiting the numerical value of the first preset threshold.
For example, the first preset threshold can be set as 512KB, etc..
Processor can be reinformed after the data of write-in cache unit 102 reach the first preset threshold by writing accelerator 103
The data of 104 processing write-ins.For example, the first preset threshold is 512KB, accelerator 103 is write in the parcel for being written with 128 4KB
After data, accumulation has reached the first preset threshold, at this time again by writing 103 notifier processes device of accelerator, 104 pairs of write-in cache units
The total data that 102 accumulation has reached 512KB is further processed.For writing 103 notifier processes device 104 of accelerator
Mode, the embodiment of the present disclosure are not construed as limiting, for example, the system control module for writing accelerator 103 described in Fig. 3 can also be by one
Data line is directly connect with processor 104, and system control module can directly pass through the disconnecting processor 104 established,
So that the data of 104 pairs of processor deposit cache units 102 are handled.Certainly, other can also be passed through by writing accelerator 103
Mode notifier processes device 104.Processor 104 is knowing that it is pre- that the data for writing the write-in cache unit 102 of accelerator 103 reach first
If after threshold value, the data after accumulation can be further processed, for example the data of the first preset threshold are up to from caching
Unit 102 is stored in the persistence medium (such as NAND FLASH) of solid state hard disk 100.It in this way, can be effective
The write efficiency of small bag data is promoted, writing speed is improved.
Optionally, after the instruction that the processor 104 of solid state hard disk 100 receives for data to be written, can also judge
Whether the data volume of data is less than the second preset threshold, and when the data volume of data is less than the second preset threshold, processor 104 is again
Notice writes accelerator 103 and data is written.
The writing speed that small bag data can be obviously improved due to writing accelerator 103, then processor 104 is receiving master
After the instruction for the write-in data that machine issues, it can first judge that the data to be written are small bag data, that is, judgement will be write
Whether the data volume of the data entered is less than the second preset threshold, in the data to be written less than the second preset threshold, that is, really
When being set to small bag data, reinforms and write accelerator 103 data are written.Second preset threshold can be preset any threshold
Value, can be what solid state hard disk 100 had been set when leaving the factory, or can also by user's sets itself as needed,
Or be also possible to by solid state hard disk 100 according to storage state dynamic configuration, etc., the embodiment of the present disclosure is default for second
The numerical value of threshold value is not construed as limiting.For example, the second preset threshold can be set as 24KB, etc..Certainly, judging to be written
When data are greater than the second preset threshold, write operation can be completed by processor 104, or equally can also be by writing accelerator
103 complete write operation, and the embodiment of the present disclosure is not construed as limiting this.In this way, small bag data can be completed by writing accelerator 103
Write operation, effectively promote the write efficiency of small bag data, improve writing speed.
Optionally, write accelerator 103 accumulation write-in cache unit 102 small bag data reach the first preset threshold after, write
Accelerator 103 can also send the storage address that have been written into the data of cache unit 102 to processor 104, and processor 104 can be with
According to storage address, the data for having been written into cache unit 102 are obtained, to handle the data for having been written into cache unit 102.
Processor 104 will be handled the data for having been written into cache unit 102, for example write data into NAND FLASH
In, need to know the address for having been written into the data of cache unit 102, then can be sent from writing accelerator 103 to processor 104
Have been written into the storage address of the data of cache unit 102.For example, as shown in Figure 3 writes accelerator 103, it can be by output information
Buffer informs that processor 104 has accumulated the information of the data of write-in cache unit 102, for example has accumulated write-in caching list
The storage address of the data of member 102, the information such as data volume size, then processor 104 can be found according to the information of acquisition
The data of cache unit 102 are had been written into, so as to handle these data.Output information buffer is equally available using asynchronous
Design method, as long as the i.e. reading output information buffer feedback in the case where command queue is discontented of processor 104
Information, the mode that substitution both sides shake hands, promotes the speed of data processing.
Optionally, the state control instruction of the transmission of processor 104 can also be received by writing accelerator 103, then according to control
Instruction is switched to halted state or operating status.Accelerator 103 is write when in operating status, it could be by data from input and output
Cache units 102 are written in mouth 101.
That is, processor 104 can control and write accelerator 103 and open or close, writes accelerator 103 and only running
It just can be carried out the write operation of data when state.As shown in Figure 3 writes accelerator 103, and processor 104 can be posted to state of a control
Storage sends control instruction, and then controls and write opening or closing for accelerator 103.In this way, solid state hard disk 100 can
Accelerator 103 is write to determine whether to enable according to actual use situation, mode is more flexible, the data of solid state hard disk 100
Processing capacity is stronger.
It is apparent to those skilled in the art that for convenience and simplicity of description, only with above-mentioned each function
The division progress of module can according to need and for example, in practical application by above-mentioned function distribution by different function moulds
Block is completed, i.e., the internal structure of solid state hard disk is divided into different functional modules, to complete whole described above or portion
Divide function.The specific work process of the device of foregoing description, can refer to corresponding processes in the foregoing method embodiment, herein not
It repeats again.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary, for example, the module or unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, each functional unit in each embodiment of the application can integrate in one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, the technical solution of the application is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are with so that solid state hard disk is held
The all or part of the steps of each embodiment the method for row the application.And storage medium above-mentioned include: USB flash disk, mobile hard disk,
Read-only memory (ROM, Read-Only Memory), RAM memory, magnetic or disk etc. are various to can store program code
Medium.
Specifically, the corresponding computer program instructions of one of the embodiment of the present application method for writing data can be deposited
It stores up on CD, hard disk, the storage mediums such as USB flash disk, when the computer journey corresponding with a kind of method for writing data in storage medium
Sequence instruction is read or is performed by a solid state hard disk, includes the following steps:
The processor of the solid state hard disk receives the instruction for data to be written；
The processor notifies the accelerator of writing of the solid state hard disk that the data are written；
It is described to write accelerator the slow of the solid state hard disk is written into from the input/output port of the solid state hard disk in the data
Memory cell.
Optionally, the accelerator of writing includes direct memory access DMA interface, to control with the DMA of the solid state hard disk
Device connects, store in the storage medium and step: the input for writing accelerator by the data from the solid state hard disk
The cache unit of the solid state hard disk is written in delivery outlet, and corresponding computer instruction is during being performed, comprising:
The accelerator of writing determines the destination address for being located at the cache unit according to the data volume of the data；
It is described to write dma controller described in Accelerator control for the corresponding caching sky of the data write-in destination address
Between.
Optionally, other step is also stored in the storage medium, the other step had been performed
Cheng Zhong, further includes:
The processor writes accelerator and sends the cache unit according to the storage state of the cache unit, Xiang Suoshu
Available address；
The accelerator of writing records the available address；
Store in the storage medium and step: according to the data volume of the data, determination is located at the accelerator of writing
The destination address of the cache unit, corresponding computer instruction is during being performed, comprising:
The accelerator of writing determines the destination address according to the data volume of the data from the available address.
Optionally, other step is also stored in the storage medium, the other step had been performed
Cheng Zhong, further includes:
The accelerator of writing obtains data writing progress, wherein the data writing progress characterization has been written into described slow
Deposit space data volume account for the data data volume ratio；
The accelerator of writing records the data writing progress；
The accelerator of writing is to the processor transmission data writing progress.
Optionally, other step is also stored in the storage medium, the other step had been performed
Cheng Zhong, further includes:
It is described write accelerator and the data volume of the cache unit is written reaches the first preset threshold when, it is described to write accelerator
The processor is notified to handle the data for having been written into the cache unit.
Optionally, store in the storage medium and step: the processor of the solid state hard disk is received for number to be written
According to instruction, corresponding computer instruction is after being performed, further includes:
Whether the processor judges the data volume of the data less than the second preset threshold；
Store in the storage medium and step: the processor notifies the accelerator of writing of the solid state hard disk that institute is written
Data are stated, corresponding computer instruction is during being performed, comprising:
When the data volume of the data is less than second preset threshold, accelerator is write described in the processor notice and is write
Enter the data.
Optionally, other step is also stored in the storage medium, the other step had been performed
Cheng Zhong, further includes:
The accelerator of writing sends the storage address for having been written into the data of the cache unit to the processor；
The processor obtains the data for having been written into the cache unit, to having been written into according to the storage address
The data for stating cache unit are handled.
Optionally, other step is also stored in the storage medium, the other step had been performed
Cheng Zhong, further includes:
The accelerator of writing receives the state control instruction that the processor is sent；
It is described to write accelerator halted state or operating status are switched to according to the control instruction；
Stored in the storage medium and step: the input for writing accelerator by the data from the solid state hard disk
The cache unit of the solid state hard disk is written in delivery outlet, and corresponding computer instruction is during being performed, comprising:
The caching list is written from the input/output port when in operating status, by the data in the accelerator of writing
Member.
The above, above embodiments are only described in detail to the technical solution to the disclosure, but the above implementation
The explanation of example is merely used to help understand disclosed method and its core concept, should not be construed as the limitation to the disclosure.This
Those skilled in the art are in the technical scope that the disclosure discloses, and any changes or substitutions that can be easily thought of, should all cover
Within the protection scope of the disclosure.
Claims (16)
1. a kind of method for writing data is applied to solid state hard disk characterized by comprising
The processor of the solid state hard disk receives the instruction for data to be written；
The processor notifies the accelerator of writing of the solid state hard disk that the data are written；
The caching list write accelerator and the data are written to the solid state hard disk from the input/output port of the solid state hard disk
Member.
2. the method according to claim 1, wherein the accelerator of writing includes direct memory access DMA interface,
To connect with the dma controller of the solid state hard disk, described to write accelerator defeated by the input of the data from the solid state hard disk
The cache unit of the solid state hard disk is written in outlet, comprising:
The accelerator of writing determines the destination address for being located at the cache unit according to the data volume of the data；
It is described to write dma controller described in Accelerator control for the corresponding spatial cache of the data write-in destination address.
3. according to the method described in claim 2, it is characterized in that, the method also includes:
According to the storage state of the cache unit, Xiang Suoshu writes accelerator and sends the available of the cache unit processor
Address；
The accelerator of writing records the available address；
The accelerator of writing determines the destination address for being located at the cache unit according to the data volume of the data, comprising:
The accelerator of writing determines the destination address according to the data volume of the data from the available address.
4. according to the method described in claim 2, it is characterized in that, the method also includes:
The accelerator of writing obtains data writing progress, wherein it is empty that the data writing progress characterization has been written into the caching
Between data volume account for the data data volume ratio；
The accelerator of writing records the data writing progress；
The accelerator of writing is to the processor transmission data writing progress.
5. the method according to claim 1, wherein the method also includes:
It is described write accelerator and the data volume of the cache unit is written reaches the first preset threshold when, it is described to write accelerator notice
The processor handles the data for having been written into the cache unit.
6. according to the method described in claim 5, it is characterized in that, the processor in the solid state hard disk is received for number to be written
According to instruction after, further includes:
Whether the processor judges the data volume of the data less than the second preset threshold；
The processor notifies the accelerator of writing of the solid state hard disk that the data are written, comprising:
When the data volume of the data is less than second preset threshold, accelerator write-in institute is write described in the processor notice
State data.
7. according to the method described in claim 5, it is characterized in that, the method also includes:
The accelerator of writing sends the storage address for having been written into the data of the cache unit to the processor；
The processor obtains the data for having been written into the cache unit according to the storage address, with described slow to having been written into
The data of memory cell are handled.
8. the method according to claim 1, wherein the method also includes:
The accelerator of writing receives the state control instruction that the processor is sent；
It is described to write accelerator halted state or operating status are switched to according to the control instruction；
The caching list write accelerator and the data are written to the solid state hard disk from the input/output port of the solid state hard disk
Member, comprising:
The cache unit is written from the input/output port when in operating status, by the data in the accelerator of writing.
9. a kind of solid state hard disk characterized by comprising input/output port interconnected, cache unit, write accelerator and
Processor；Wherein,
The processor is used to receive the instruction for data to be written, and writes accelerator described in notice and the data are written；
The accelerator of writing is for being written the cache unit from the input/output port for the data.
10. solid state hard disk according to claim 9, which is characterized in that the solid state hard disk further includes direct memory access
Dma controller, the accelerator of writing are connect by DMA interface with the dma controller, and the accelerator of writing is used for:
According to the data volume of the data, the destination address for being located at the cache unit is determined；
It controls the dma controller and the corresponding spatial cache of the destination address is written into the data.
11. solid state hard disk according to claim 10, which is characterized in that
The processor is also used to the storage state according to the cache unit, and Xiang Suoshu writes accelerator and sends the cache unit
Available address；
The accelerator of writing is also used to record the available address；
The accelerator of writing is used for:
According to the data volume of the data, the destination address is determined from the available address.
12. solid state hard disk according to claim 10, which is characterized in that the accelerator of writing is also used to:
Obtain data writing progress, wherein the data volume that the data writing progress characterization has been written into the spatial cache accounts for
The ratio of the data volume of the data；
Record the data writing progress；
The data writing progress is sent to the processor.
13. solid state hard disk according to claim 9, which is characterized in that the accelerator of writing is also used to:
It is described write accelerator and the data volume of the cache unit is written reaches the first preset threshold when, notify the processor pair
The data for having been written into the cache unit are handled.
14. solid state hard disk according to claim 13, which is characterized in that the processor is also used to:
After receiving the instruction for data to be written, judge the data volume of the data whether less than the second preset threshold；
When the data volume of the data is less than second preset threshold, accelerator is write described in notice, the data are written.
15. solid state hard disk according to claim 13, which is characterized in that
The accelerator of writing is also used to send the storage address for having been written into the data of the cache unit to the processor；
The processor is also used to obtain the data for having been written into the cache unit according to the storage address, with to having been written into
The data of the cache unit are handled.
16. solid state hard disk according to claim 9, which is characterized in that the accelerator of writing is also used to:
Receive the state control instruction that the processor is sent；
Halted state or operating status are switched to according to the control instruction；
When in operating status, the cache unit is written into from the input/output port in the data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810279244.6A CN110321296A (en) | 2018-03-31 | 2018-03-31 | Method for writing data and solid state hard disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810279244.6A CN110321296A (en) | 2018-03-31 | 2018-03-31 | Method for writing data and solid state hard disk |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110321296A true CN110321296A (en) | 2019-10-11 |
Family
ID=68111989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810279244.6A Withdrawn CN110321296A (en) | 2018-03-31 | 2018-03-31 | Method for writing data and solid state hard disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110321296A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070168607A1 (en) * | 2006-01-17 | 2007-07-19 | Kabushiki Kaisha Toshiba | Storage device using nonvolatile cache memory and control method thereof |
| CN105843775A (en) * | 2016-04-06 | 2016-08-10 | 中国科学院计算技术研究所 | On-chip data partitioning read-write method, system and device |
| CN106873904A (en) * | 2016-12-30 | 2017-06-20 | 北京联想核芯科技有限公司 | Method for writing data and solid state hard disc |
| CN108292229A (en) * | 2015-12-20 | 2018-07-17 | 英特尔公司 | The instruction of adjacent aggregation for reappearing and logic |
-
2018
- 2018-03-31 CN CN201810279244.6A patent/CN110321296A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070168607A1 (en) * | 2006-01-17 | 2007-07-19 | Kabushiki Kaisha Toshiba | Storage device using nonvolatile cache memory and control method thereof |
| CN108292229A (en) * | 2015-12-20 | 2018-07-17 | 英特尔公司 | The instruction of adjacent aggregation for reappearing and logic |
| CN105843775A (en) * | 2016-04-06 | 2016-08-10 | 中国科学院计算技术研究所 | On-chip data partitioning read-write method, system and device |
| CN106873904A (en) * | 2016-12-30 | 2017-06-20 | 北京联想核芯科技有限公司 | Method for writing data and solid state hard disc |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106873904A (en) | Method for writing data and solid state hard disc | |
| CN104951252B (en) | A kind of data access method and PCIe storage devices | |
| CN101615106B (en) | Method and system for virtualizing SAS storage adapter | |
| US9158684B2 (en) | Flash-DRAM hybrid memory module | |
| CN106201350B (en) | Method, memory and the computer system of storing data | |
| TWI483178B (en) | Apparatus including memory system controllers and related methods | |
| US20150127691A1 (en) | Efficient implementations for mapreduce systems | |
| US20080229049A1 (en) | Processor card for blade server and process. | |
| CN105849669A (en) | Method and apparatus for DRAM spatial coalescing within a single channel | |
| CN105335308B (en) | To access information treating method and apparatus, the system of storage device | |
| EP3910488A1 (en) | Systems, methods, and devices for near data processing | |
| US7971004B2 (en) | System and article of manufacture for dumping data in processing systems to a shared storage | |
| CN100414524C (en) | Method for controlling data transmission between two different speed buses | |
| KR20130132591A (en) | Methods and apparatus for efficient communication between caches in hierarchical caching design | |
| CN109582215A (en) | Execution method, hard disk and the storage medium of hard disk operation order | |
| JP2017531856A (en) | Active storage units and arrays | |
| CN110109851A (en) | Electronic system and its operating method with main frame and memory controller | |
| CN109697022A (en) | A kind of processing method, device and the computer readable storage medium of message descriptor PD | |
| CN106873903A (en) | Date storage method and device | |
| CN106502581B (en) | Flash controller, flash memory control method and solid state hard disk | |
| US8745294B2 (en) | Dynamic random access memory for a semiconductor storage device-based system | |
| EP3982269A1 (en) | Systems, methods, and devices for accelerators with virtualization and tiered memory | |
| CN113468083B (en) | Dual-port NVMe controller and control method | |
| CN110321296A (en) | Method for writing data and solid state hard disk | |
| KR101428317B1 (en) | High-performance ahci interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20191011 |