CN110312091A - Meet the signal receiving device and its signal processing method of digital TV broadcast standards - Google Patents
Meet the signal receiving device and its signal processing method of digital TV broadcast standards Download PDFInfo
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- CN110312091A CN110312091A CN201810235305.9A CN201810235305A CN110312091A CN 110312091 A CN110312091 A CN 110312091A CN 201810235305 A CN201810235305 A CN 201810235305A CN 110312091 A CN110312091 A CN 110312091A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/50—Tuning indicators; Automatic tuning control
Abstract
In a signal receiving device, the anti-interleaver of timing imposes the anti-cross-program of timing to multiple interlaced frames, wrong as a result, and the generation timing request when finding out by the starting point for examining interlaced frame to generate timing reciprocal cross.Signal processing circuit imposes the signal handler with an average retardation amount to timing reciprocal cross mistake result, to generate signal processing results.It removes wobble buffer to obtain by the original output time for examining interlaced frame, generates settlement request accordingly, and the signal processing results are converted into transmission stream.It examines circuit to generate timing result according to timing request and settlement request, and judges whether met preset condition by the inspection output time according to timing result and average retardation amount.If the new time that exported by examining is generated and accepts inspection by examining the output time not conform to preset condition.
Description
Technical field
The present invention is related to digital television broadcasting, and especially with the removal jitter buffer in digital television broadcasting receiving end
Device (de-jitter buffer) is related.
Background technique
With the progress of the communication technology, the development of digital picture broadcast is gradually mature.Digital television broadcasting (digital
Video broadcasting, DVB) standard is at present in Africa and the digital picture broadcast standard of Asia most mainstream.Fig. 1
The outline functional block diagram of a digital television broadcasting receiving end is presented, wherein including tuner 101, analogue-to-digital converters
102, front-end circuit 103, demodulator circuit 104, balanced device 105, wrong (the de-interleaving)/forward direction of reciprocal cross detect mistake
(forward error correction) circuit 106, removal wobble buffer 107, source decoder (source
Decoder) 108 and display 109.
The main function of removal wobble buffer 107 is that temporary reciprocal cross mistake/forward direction detects the number that wrong circuit 106 exports successively
According to, these data groups are combined into transmission stream (transport stream), and transmission stream is passed in due course at the appropriate speed
Pass source decoder 108.If not waiting for a period of time slightly and just opening after removal wobble buffer 107 receives the first stroke data
Begin to export the transmission stream, wrong circuit 106 may be detectd because of reciprocal cross mistake/forward direction by data and is stored in removal wobble buffer 107
Speed it is not fast enough, the situation that the follow-up data in the transmission stream has little time to keep up with occurs.This problem is commonly referred to as owing position
(underflow).It relatively, may be because of its storage space if removal wobble buffer 107 starts very much to export transmission stream slowly
The problem of being not enough to accommodate reciprocal cross mistake/forward direction and detect the data that wrong circuit 106 is stored in, and overflow (overflow) occurs.
In order to avoid occurring to owe position or overflow problem, according to the regulation of digital TV broadcast standards, transmission end must be directed to
Each interlaced frame (interleaving frame) one output time (time-to-output, TTO) parameter of offer is connect
The removal wobble buffer 107 of receiving end, it is indicated that start the appropriate time point that output corresponds to the transmission stream of the interlaced frame.
However, transmission end, which may not necessarily provide, reasonably exports time parameter to receiving end in realistic situation.Citing comes
It says, the output time parameter of all interlaced frames unreasonably can be set to zero by certain transmission ends.If receiving end not voluntarily
It closes, but the output time parameter of transmission end offer is provided, just may meet with aforementioned deficient position problem, seriously affect reception
The normal operation at end.
Summary of the invention
To solve the above problems, the present invention proposes a kind of new signal receiving device and signal processing method.
An embodiment according to the present invention is a kind of signal receiving device, is mentioned to receive a digital television broadcasting transmission end
The video-audio signal of confession.The video-audio signal corresponds to multiple interlaced frames.The signal receiving device includes a timing reciprocal cross mistake device, a letter
Number processing circuit, one examine circuit, a removal wobble buffer, an amendment circuit and an initialization circuit.The anti-interleaver of the timing
It is to impose a timing reciprocal cross mistake program to multiple interlaced frame, to generate a timing reciprocal cross mistake as a result, and finding out one
Timing request is generated when by a starting point for examining interlaced frame.The signal processing circuit is to the timing reciprocal cross mistake result
A signal handler is imposed, to generate a signal processing results, wherein the signal handler has an average retardation amount.It should
Removal wobble buffer is to obtain this from the signal processing results by the original output time for examining interlaced frame, accordingly
A settlement request is generated, and the signal processing results are converted into a transmission stream.The inspection circuit is to according to the meter
When request with the settlement request generate a timing result, and be somebody's turn to do and be handed over by inspection according to the timing result and average retardation amount judgement
Whether the one of wrong frame is met a preset condition by the inspection output time.If the preset condition should not be met by the inspection output time,
The amendment circuit generate one it is new exported the time by examining, and request the inspection circuit check this be new by examining output time to be
It is no to meet the preset condition.If this is by examining the output time meet the preset condition, which be exported according to this by inspection
Time sets the time point that the removal wobble buffer exports the transmission stream.
It is according to another embodiment of the present invention a kind of signal processing method applied to digital television broadcasting receiving end.It should
Method includes: (a) receiving the video-audio signal that a digital television broadcasting transmission end provides, which corresponds to multiple interlock
Frame；(b) a timing reciprocal cross mistake program is imposed to multiple interlaced frame, to generate a timing reciprocal cross mistake as a result, and finding out one
Timing request is generated when by a starting point for examining interlaced frame；(c) a signal processing journey is imposed to the timing reciprocal cross mistake result
Sequence, to generate a signal processing results, wherein the signal handler has an average retardation amount；(d) from the signal processing knot
It obtains about this in fruit by the original output time for examining interlaced frame, generates a settlement request accordingly；It (e) will be at the signal
Reason result is converted to a transmission stream；(f) timing result is generated with the settlement request according to timing request, and according to the meter
When result and the average retardation amount judge this by examine interlaced frame one by examine output the time whether meet a preset condition；
If (g) should by examining the output time not meet the preset condition, generate one it is new exported the time by examining, and examine this new by
Examine whether the output time meets the preset condition；And if (h) should be by examining the output time to meet the preset condition, according to this
By the time point for examining the setting of output time to export the transmission stream.
It can be further understood by following detailed description of the invention and institute's accompanying drawings about the advantages and spirit of the present invention.
Detailed description of the invention
The outline functional block diagram of a digital television broadcasting receiving end is presented in Fig. 1.
Fig. 2 is the functional block diagram according to the signal receiving device in one embodiment of the invention.
Fig. 3 is presented reciprocal cross mistake/forward direction and detects wrong circuit, removal wobble buffer, examines circuit, amendment circuit, initialization circuit
Connection relationship a kind of embodiment.
Fig. 4 is the flow chart according to the signal processing method in one embodiment of the invention.
It should be noted that schema of the invention includes that the functional block diagram of a variety of functional modules associated with each other is presented.
The schemas such as this are not thin portion circuit diagram, and connecting line therein is only to indicate signal stream.Between functional element and/or program
A variety of interactive relationship are not necessarily intended to reach through the direct electrical connection beginning.In addition, the function of individual component be not necessarily intended to as
The mode being painted in schema is distributed, and distributed block is not necessarily intended to the realization of electronic component in a distributed manner.
Symbol description
101,201: tuner 102,202: analogue-to-digital converters
103,203: front-end circuit 104,204: demodulator circuit
105,205: balanced device 106,206: reciprocal cross mistake/forward direction detects wrong circuit
107,207: removal wobble buffer 108,208: source decoder
109,209: display 211: examining circuit
211A: timing circuit 211B: add circuit
211C: comparison circuit 212: amendment circuit
213: initialization circuit S401~S409: process step
Specific embodiment
An embodiment according to the present invention is the signal receiving device that one kind meets digital television broadcasting (DVB) standard,
Functional block diagram is depicted in Fig. 2.Signal receiving device 200 includes tuner 201, analogue-to-digital converters 202, front end electricity
Road 203, demodulator circuit 204, balanced device 205, reciprocal cross mistake/forward direction detect wrong circuit 206, removal wobble buffer 207, source decoding
Device 208, display 209 examine circuit 211, amendment circuit 212 and initialization circuit 213.Comparing Fig. 1 and Fig. 2 can be seen that, letter
The main characteristics of number reception device 200 are to be provided with inspection circuit 211, the amendment that cooperation removal wobble buffer 207 operates
Circuit 212 and initialization circuit 213.
As it was earlier mentioned, transmission end can provide an output time parameter for removing jitter buffer for each interlaced frame
Device 207 refers to.In practice, when incredible transmission end will not usually provide unreasonable output only for a few interlaced frame
Between parameter, but the output time parameter of a succession of interlaced frame is set to unreasonable numerical value.It follows that if having found
Remove that the output time parameter that wobble buffer 207 obtains is unreasonable, can inference other subsequent interlaced frames the output time
Parameter is also likely to be unreasonable.Therefore, in signal receiving device 200, examine circuit 211 that can examine transmission end needle first
The output time parameter (hereinafter referred to as this parameter is original output time TTO_TX) that some interlaced frame is provided, then decide whether
Start subsequent revision program.More specifically, if circuit 211 is examined to determine that original output time TTO_TX meets a default item
Part examines circuit 211 that initialization circuit 213 is just requested to be set according to original output time TTO_TX for removal wobble buffer 207
Start the time point of output transmission stream.On the contrary, pre- if circuit 211 is examined to determine that original output time TTO_TX does not meet this
If condition, amendment circuit 212 exports the time after just generating an amendment, and request checking circuit 211 is tested again, with judgement
Export whether the time meets the preset condition after amendment.After exporting the time after finding out the amendment for meeting the preset condition, setting
Circuit 213 is to remove wobble buffer 207 to set the time point for starting to export transmission stream according to the output time after this amendment.
The adoptable preset condition of inspection circuit 211 introduced below, and examine circuit 211, amendment circuit 212, setting
The thin portion of circuit 213 operates embodiment.
Fig. 3 is presented reciprocal cross mistake/forward direction and detects wrong circuit 206, removal wobble buffer 207, examines circuit 211, amendment circuit
212, a kind of embodiment of the connection relationship of initialization circuit 213.Fig. 3 shows two that reciprocal cross mistake/forward direction is detectd in wrong circuit 206
Mac function: the anti-interleaver of timing (time de-interleaver) 206A and signal processing circuit 206B.In practice, handing over
Mistake/forward direction is detectd in wrong circuit 206, and the anti-interleaver 206A of timing is usually coupled to the anti-interleaver of a frequency (frequency de-
Interleaver after), and signal processing circuit 206B refers to and is coupled to the anti-interleaver of timing in signal receiving device 200
Circuit between 206A and removal wobble buffer 207, the such as, but not limited to anti-interleaver of unit (cel l de-
Interleaver), circulation delay removes (cyclic delay removal) circuit, soft judgement (soft de-mapping)
Circuit, the anti-interleaver in position (bit de-interleaver), low density parity check (low density parity check,
LDPC) decoder, Bo Si-Qiao Heli (BCH) decoder and fundamental frequency descrambling (baseband descrambling) circuit.
Various signal handlers in signal processing circuit 206B can contribute an implementation retardation (implementation
) or transmission delay amount (transmission latency) delay.This average value for implementing retardation (hereinafter referred to as averagely prolongs
Amount imp_delay late) it can be generated through simulation calculation or practical measure, and be stored beforehand in signal receiving device 200
Memory (not being painted) in.It should be noted that the size of average retardation amount imp_delay may be with signal format (example
Such as coding mode) change and it is different；Signal receiving device 200 corresponds to unlike signal format there are many can storing in advance
Average retardation amount imp_delay, as examining the reference information that uses of circuit 211.
In this embodiment, examine circuit 211 electric comprising a timing circuit 211A, an add circuit 211B, a comparison
A road 211C and multiplexer 211D.Timing circuit 211A is responsible for calculating a working time Cnt.As shown in figure 3, timing circuit 211A
A timing request can be received from the anti-interleaver 206A of timing.More specifically, the anti-interleaver 206A of timing is examined finding
Interlaced frame starting point when notice timing circuit 211A start timing.On the other hand, removal wobble buffer 207 can from its
It is parsed in input signal and sends a settlement request when interlaced frame examined original exports time TTO_TX and give timing electricity
Road 211A.After receiving the settlement request, timing circuit 211A can be by working time Cnt accumulative at that time as a timing result
Tto_Cnt sends comparison circuit 211C to.It is the anti-interleaver 206A of timing, signal processing circuit that timing result tto_Cnt, which can be said,
206B, and one section of working time length that removal wobble buffer 207 is used in the interlaced frame that processing is examined.Examine electricity
Road 211 test for the first time work when the hereinafter referred to as initial interlaced frame of interlaced frame examined, timing circuit 211A is for initial
The timing result tto_Cnt that interlaced frame generates is represented as tto_Cnt_0.
It should be noted that the anti-interleaver 206A of timing finds out the detailed technology of the starting point of an interlaced frame and removal shake is delayed
Rush device 207 parse it is original output time TTO_TX detailed technology be known to those skilled in the art, do not repeated in this.It is another
Aspect, even if receiving settlement request and generating timing result tto_Cnt, timing circuit 211A still will continue to its Counts.
Timing circuit 211A accumulative working time Cnt will be provided to the use of initialization circuit 213, and details is detailed later.
As it was earlier mentioned, the average retardation amount imp_delay of signal processing circuit 206B contribution can be learnt in advance.Addition electricity
Road 211B can receive average retardation amount imp_delay, and calculate average retardation amount imp_delay and one and exported the time by inspection
The addition result Sum of TTO.As shown in figure 3, when multiplexer 211D can receive the original output that removal wobble buffer 207 obtains
Between TTO_TX, and amendment circuit 212 generate amendment after export time TTO ', therefrom select one as be transferred to addition electricity
Road 211B's is exported time TTO by examining.When inspection circuit 211 tests work for the first time, it is by inspection output time TTO
The original output time TTO_TX of initial interlaced frame, and add circuit 211B is directed to the addition result Sum that initial interlaced frame calculates
It is represented as Sum_0.In other words, addition result Sum_0 is original output time TTO_TX and average retardation amount imp_delay
Sum.
In this embodiment, the preset condition for examining circuit 211 to use is set to " average retardation amount imp_delay
Timing result tto_Cnt " is had to be larger than with by the addition result Sum of inspection output time TTO.Therefore, comparison circuit 211C is negative
Duty compares the size of addition result Sum Yu timing result tto_Cnt.In more detail, transmission end is usually according to coded program
The time of consumption sets the original output time TTO_TX of receiving end to be supplied to, but the decoding program of receiving end can be than transmission
The coded program at end is time-consuming.That is, the various signal handlers in signal processing circuit 206B may include
Examination misses process, not in the time span that original output time TTO_TX is covered, it is therefore necessary to by average retardation amount imp_delay
It accounts for.After being added with average retardation amount imp_delay, reasonable original output time TTO_TX, which ought to can be enabled, " to be added
As a result Sum_0 is set up greater than this preset condition of timing result tto_Cnt_0 ".
The case where explanation " addition result Sum_0 is greater than timing result tto_Cnt_0 " first.When comparison circuit 211C is exported
Inspection result show that original output time TTO_TX meets above-mentioned preset condition, amendment circuit 212 does not need to operate, and sets
Circuit 213 can be to remove wobble buffer 207 to set the time for starting to export transmission stream according to original output time TTO_TX
Point.For example, circuit designers can enable initialization circuit 213 by original output time TTO_TX and average retardation amount imp_
The addition result Sum_0 of delay is set as removing the output time that wobble buffer 207 actually uses.As shown in figure 3, timing
The addition result Sum that the working time Cnt and add circuit 211B that circuit 211A is counted are generated can be provided to setting electricity
Road 213.Initialization circuit 213 just at work between Cnt when reaching addition result Sum_0, send an output request, request removal
Wobble buffer 207 starts the transmission stream that output corresponds to initial interlaced frame.
In practice, timing interlock (time interleaving) depth is all identical with coding mode and time front and back phase
The output time that two close interlaced frames are applicable in does not have too many differences.If it is known that next there is continuous multiple interlaced frames
Timing interleave depth and coding mode are all identical, can inference be suitable for these interlaced frames the output time can be close.Therefore, sentencing
Original output time TTO_TX of fixed initial interlaced frame is examined one by one after credible numerical value, to examine circuit 211 to be not necessarily intended to continuation
Test the original output time of subsequent interlaced frame.More specifically, initialization circuit 213 can be with the original output time of initial interlaced frame
Based on TTO_TX, set the identical output time for next continuous multiple interlaced frames, for removal wobble buffer 207 in
It is used when exporting transmission stream relevant to multiple interlaced frame.
It should be noted that initialization circuit 213 causes the time for removing the output transmission stream of wobble buffer 207 not to be added
As a result Sum_0 is limited.For example, the decoding time of each interlaced frame slightly difference, circuit designers can may enable removal
Wobble buffer 207 starts to export the time of transmission stream slightly larger than addition result Sum_0, to cover the decoding of subsequent interlaced frame
The variability of length of time.Theoretically, the addition result Sum_0 that will be greater than timing result tto_Cnt_0 orders as initialization circuit 213
The time for generating output request is enough to guarantee removal wobble buffer 207 when exporting the transmission stream of subsequent interlaced frame not
It can occur to owe position (underflow) problem.On the other hand, the upper limit for the time that the generation of initialization circuit 213 output is requested is will not
Enable removal wobble buffer 207 that overflow (overflow) problem occurs.As long as it will be understood by those skilled in the art that initialization circuit
As soon as 213 times for generating output request were set in a reasonable range, it is avoided that removal wobble buffer 207 occurs to owe
The problem of position or overflow.That is, the time that initialization circuit 213 generates output request can have a degree of adjustment bullet
Property.
The case where " addition result Sum_0 is less than or equal to timing result tto_Cnt_0 " will be illustrated next.Work as comparison circuit
The inspection result of 211C output shows that original output time TTO_TX does not meet preset condition, and amendment circuit 212 can then receive
One instruction, and time TTO ' _ 1 is exported after generating an amendment accordingly.In practice, transmission end is generating a reasonable original output
When time TTO_TX, the timing interleave depth TI of an interlaced frame may be referred to.Therefore, in an embodiment, circuit 212 is corrected
Using the timing interleave depth TI of an interlaced frame as output time TTO ' _ 1 after amendment.For DVB-T2 standard, timing is handed over
Wrong depth TI may be the integral multiple (such as three times) of the time span of a T2 frame, it is also possible to the time span of a T2 frame
Integer point one (such as one third).Amendment circuit 212 can calculate according to the data that transmission end provides and be sent into letter at present
The timing interleave depth TI of the interlaced frame of number reception device 200, calculation are known to those skilled in the art, not in this
It repeats.Above-mentioned interlaced frame depth TI may be stored in amendment circuit 212 in advance, or can be from removal wobble buffer 207
Parsing result obtains relevant information.When the inspection result of comparison circuit 211C output shows that original output time TTO_TX is not met
Preset condition, multiplexer 211D can send time TTO ' _ 1 is exported after amendment into add circuit 212B, with average retardation amount imp_
Delay is added, and calculates addition result Sum_1.Another possibility is that output time TTO ' _ 1 will be deposited after amendment circuit 212 will be corrected
Enter to remove in wobble buffer 207, therefore add circuit 212B can be read after correcting by removal wobble buffer 207 and export the time
TTO'_1.In other words, when the not initial interlaced frame of the interlaced frame examined, subsequent interlaced frame, when the output examined
Between TTO be correct circuit 212 generate amendment after export time TTO '.
In an embodiment, if circuit 211 is examined to determine that original output time TTO_TX cannot enable preset condition set up, go
Except wobble buffer 207 can be reset, that is, abandon data relevant to initial interlaced frame, restart receive with it is next
The related data of interlaced frame.In addition, timing circuit 211A can be also reset, timing result tto_ is generated for next interlaced frame
Cnt.In more detail, timing circuit 211A can be held in the anti-interleaver 206A of timing when finding the starting point of next interlaced frame
Beginning timing, and the clearing when removing wobble buffer 207 and parsing the original output time TTO_TX of the interlaced frame.In timing
After circuit 211A obtains the timing result tto_Cnt (indicating with symbol tto_Cnt_1) of next interlaced frame, comparison circuit 211C
Timing result tto_Cnt_1 will be compared and addition result Sum_1 (exports time TTO ' _ 1 and imp_ after namely correcting
The addition result of delay) size.If addition result Sum_1 is greater than timing result tto_Cnt_1, when indicating to export after correcting
Between TTO ' _ 1 enable preset condition set up, this inspection result can drive initialization circuit 213 according to after amendment export time TTO ' _ 1 be
Removal wobble buffer 207 sets the time point for starting to export transmission stream.For example, initialization circuit 213 can be according to addition
As a result Sum_1 setting generates the time of its output request, and enabling removal wobble buffer 207, time output is next continuous more according to this
The transmission stream of a interlaced frame.
If comparison circuit 211C output inspection result display amendment after output time TTO ' _ 1 without decree preset condition at
Vertical, then correcting circuit 212 can generate greater than output time TTO ' _ 2 after another amendment for exporting time TTO ' _ 1 after amendment.It is real
In business, amendment circuit 212 exports the time after can slightly increasing amendment every time, after finding out and can meet the amendment of preset condition
Export the time.In an embodiment, amendment circuit 212 exports speed according to the capacity and transmission stream of removal wobble buffer 207
Rate calculates a tolerable supplement amount, and timing interleave depth TI is added with the tolerable supplement amount, when as exporting after amendment
Between TTO ' _ 2.For example, amendment circuit 212 can enable the tolerable supplement amount correspond to the capacity for removing wobble buffer 207
A quarter.Assuming that the capacity of removal wobble buffer 207 is two megabits, and transmission stream output speed is every 7/64 millisecond
Export megabit data, then correct circuit 212 can calculate removal 207 every 7/128 milliseconds of wobble buffer can export its capacity
The data of a quarter.In that case, 7/128 millisecond is above-mentioned tolerable supplement amount, and exports the time after correcting
TTO ' _ 2 are timing interleave depth TI and 7/128 millisecond of addition result.
Similarly, add circuit 211B can calculate output time TTO ' _ 2 and average retardation amount imp_delay after amendment
Addition result Sum_2, and comparison circuit 211C can compare addition result Sum_2 with correspond to next one interlaced frame timing
As a result tto_Cnt_2, whether output time TTO ' _ 2 meet preset condition after determining amendment whereby.If addition result Sum_2 is big
In timing result tto_Cnt_2, initialization circuit 213 can be removal wobble buffer according to time TTO ' _ 2 are exported after amendment
207 settings start to export the time point of transmission stream.Relatively, if addition result Sum_2 is less than timing result tto_Cnt_2,
Then correcting circuit 212 will continue to generate higher than output time TTO ' _ 3 after another amendment for exporting time TTO ' _ 2 after amendment,
The rest may be inferred.
In the above-described embodiments, when that preset condition cannot be enabled to set up by inspection output time TTO, wobble buffer is removed
207 can abandon and this is by examining the relevant data of interlaced frame at present, and a subsequent interlaced frame can be chosen as new examined
Interlaced frame.In that case, output time TTO ' is for new by inspection interlaced frame after the generated amendment of amendment circuit 212
It uses, that is, new is exported the time by examining by examine interlaced frame as this.For example, if the original of initial interlaced frame
Output beginning, TTO_TX time cannot enable preset condition set up, then export time TTO ' _ 1 after correcting amendment caused by circuit 212
It is for new by examining interlaced frame (that is, a subsequent interlaced frame, and non-initial interlaced frame) to use.If exporting the time after amendment
TTO ' _ 1 can enable preset condition set up, then it is removal jitter buffer that initialization circuit 213, which is according to time TTO ' _ 1 is exported after amendment,
Device 207 sets the time point for starting output transmission stream relevant to the subsequent interlaced frame.
In another embodiment, when that preset condition cannot be enabled to set up by inspection output time TTO, wobble buffer is removed
207 will not abandon at present this by examining the relevant data of interlaced frame.In that case, it corrects caused by circuit 212
After amendment export time TTO ' be at present this by examine interlaced frame use, as this interlaced frame newly when being exported by inspection
Between.For example, if original output time TTO_TX of initial interlaced frame cannot enable preset condition set up, circuit is corrected
Output time TTO ' _ 1 is still to use for initial interlaced frame after amendment caused by 212, is examined as initial interlaced frame is new
Test the output time.Until find out can enable preset condition set up by examine export the time, removal wobble buffer 207 just can be accordingly
Export transmission stream relevant to initial interlaced frame.
It is according to another embodiment of the present invention a kind of signal processing method applied to digital television broadcasting receiving end,
Flow chart is depicted in Fig. 4.Firstly, step S401 is the video-audio signal for receiving a digital television broadcasting transmission end and providing, it should
Video-audio signal corresponds to multiple interlaced frames.Step S402 is to impose a timing reciprocal cross mistake program to multiple interlaced frame, to generate
One timing reciprocal cross is wrong as a result, and generating timing request when finding out one by a starting point for examining interlaced frame.Step S403
To impose a signal handler to the timing reciprocal cross mistake result, to generate a signal processing results, the wherein signal processing journey
Sequence has an average retardation amount.Step S404 is to be obtained from the signal processing results about this by the original for examining interlaced frame
Begin the output time, generates a settlement request accordingly.Step S405 is the timing request generated according to step S402 and step S404
The settlement request generated generates a timing result.The timing result and the signal handler is averaged according to step S406
Retardation judges whether this is met a preset condition by the inspection output time by the one of inspection interlaced frame.If the judgement of step S406
As a result be it is no, then step S407 will be performed, that is, it is new by examining interlaced frame to set one, and be generated one and new exported by inspection
Time.After step S407, step S402 and its subsequent step will be merely re-executed.On the other hand, another after step S403
Have step S408, also will the signal processing results be converted to a transmission stream.If the judging result of step S406 be it is yes, walk
Rapid S409 will be performed, that is, according to the time by the transmission stream for examining output time setting output step S408 to generate
Point.
It will be understood by those skilled in the art that the various operation changes previously described when introducing signal receiving device 200
Also the signal processing method that can be applied in Fig. 4, details repeat no more.
By the detailed description of above embodiments, be intended to more to clearly describe feature and spirit of the invention, and not with
Above-mentioned disclosed embodiment limits scope of the invention.On the contrary, the purpose is to wish to cover various changes
And tool equality is arranged in the scope of the claims to be applied of the invention.
Claims (14)
1. a kind of signal receiving device, to receive a video-audio signal of digital television broadcasting transmission end offer, the audio-visual letter
Number correspond to multiple interlaced frames, which includes:
One timing reciprocal cross mistake device, it is wrong to generate a timing reciprocal cross to impose a timing reciprocal cross mistake program to multiple interlaced frame
As a result, and generating timing request when finding out one by a starting point for examining interlaced frame；
One signal processing circuit, to impose a signal handler to the timing reciprocal cross mistake result, to generate a signal processing
As a result, wherein the signal handler has an average retardation amount；
One removal wobble buffer, when obtaining this from the signal processing results by the original output for examining interlaced frame
Between, a settlement request is generated accordingly, and the signal processing results are converted into a transmission stream；
One examines circuit, to generate a timing result with the settlement request according to timing request, and according to the timing result
Judge whether this is met a preset condition by the inspection output time by the one of inspection interlaced frame with the average retardation amount；
One amendment circuit, if should be by examining the output time not meet the preset condition, amendment circuit generation one is new to be examined
The time is exported, and requests the inspection circuit check this is new by examining whether the output time meets the preset condition；And
One initialization circuit, if the preset condition should be met by the inspection output time, when the initialization circuit by inspection according to that should be exported
Between set the time point that the removal wobble buffer exports the transmission stream.
2. signal receiving device as described in claim 1, which is characterized in that the inspection circuit includes:
One timing circuit starts timing to request according to the timing, and exports the timing result according to the settlement request；
One add circuit, to calculate this by the addition result for examining the output time and the average retardation amount；And
One comparison circuit, to compare the addition result and the timing result, when wherein the addition result is greater than the timing result,
The preset condition should be met by the inspection output time by representing.
3. signal receiving device as claimed in claim 2, which is characterized in that if the comparison circuit determines to be exported by inspection
Between meet the preset condition, the initialization circuit in the timing circuit add up a working time be equal to the addition result when, enable should
Removal wobble buffer starts to export the transmission stream.
4. signal receiving device as described in claim 1, which is characterized in that the amendment circuit is using this by inspection interlaced frame
One timing interleave depth new is exported the time by examining as this.
5. signal receiving device as claimed in claim 4, which is characterized in that if the inspection circuit determines that this is new defeated by examining
The time does not meet the preset condition out, which exports according to a capacity of the removal wobble buffer and a transmission stream
Rate calculations one may be allowed supplement amount, and the timing interleave depth is added with the tolerable supplement amount, as it is another newly by
The output time is examined, and requests the inspection circuit check this is another new by examining whether the output time meets the preset condition.
6. signal receiving device as described in claim 1, which is characterized in that the amendment circuit is in multiple interlaced frame
A subsequent interlaced frame generate this and new exported the time by examining；If the inspection circuit determines that the new time that exported by examining accords with
Close the preset condition, the initialization circuit according to this it is new by examine the output time set removal wobble buffer output with after this
The time point of the continuous relevant transmission stream of interlaced frame.
7. signal receiving device as described in claim 1, which is characterized in that the amendment circuit is to be directed to be somebody's turn to do by inspection interlaced frame
It generates this and new is exported the time by examining；If the inspection circuit determines that the new time that exported by examining meets the preset condition,
The initialization circuit according to this it is new by examine the output time set removal wobble buffer output with should be by inspection interlaced frame phase
The time point of the transmission stream closed.
8. a kind of signal processing method applied to digital television broadcasting receiving end, includes:
(a) video-audio signal that a digital television broadcasting transmission end provides is received, which corresponds to multiple interlaced frames；
(b) a timing reciprocal cross mistake program is imposed to multiple interlaced frame, to generate a timing reciprocal cross mistake as a result, and finding out one
Timing request is generated when by a starting point for examining interlaced frame；
(c) signal handler is imposed to the timing reciprocal cross mistake result, to generate a signal processing results, wherein at the signal
Managing program has an average retardation amount；
(d) this is obtained from the signal processing results by the original output time for examining interlaced frame, is generated a clearing accordingly and is asked
It asks；
(e) signal processing results are converted into a transmission stream；
(f) timing result is generated with the settlement request according to timing request, and according to the timing result and the average retardation
Amount judges whether this is met a preset condition by the inspection output time by the one of inspection interlaced frame；
If (g) should by examining the output time not meet the preset condition, generate one it is new exported the time by examining, and examine this new
By examine output the time whether meet the preset condition；And
If (h) the transmission string should be exported by inspection output time setting according to this by examining the output time to meet the preset condition
The time point of stream.
9. signal processing method as claimed in claim 8, which is characterized in that step (f) includes:
It is requested to start timing according to the timing, and the timing result is exported according to the settlement request；
This is calculated by the addition result for examining the output time and the average retardation amount；
Compare the addition result and the timing result；And
If the addition result is greater than the timing result, determine that the preset condition is set up.
10. signal processing method as claimed in claim 9, characterized by comprising:
It is requested to start timing according to the timing, adds up a working time；And
If, when the working time being equal to the addition result, should be opened by examining the output time to be judged as meeting the preset condition
Begin to export the transmission stream.
11. signal processing method as claimed in claim 8, which is characterized in that step (g) includes to use to be somebody's turn to do by inspection interlaced frame
A timing interleave depth as this it is new examined after export the time.
12. signal processing method as claimed in claim 11, which is characterized in that further include:
If step (g) determines that the new time that exported by examining does not meet the preset condition, according to a buffer capacity and a transmission
Crossfire output speed calculates a tolerable supplement amount；
The timing interleave depth is added with the tolerable supplement amount, as another new by examining the output time；And
Examine this another new by examining whether the output time meets the preset condition.
13. signal processing method as claimed in claim 8, which is characterized in that step (g) is in multiple interlaced frame
One subsequent interlaced frame generates this and new is exported the time by examining；If step (g) determines that the new time that exported by examining meets this
Preset condition, this is new by examining the setting of output time to export the transmission relevant to the subsequent interlaced frame according to step (h)
The time point of crossfire.
14. signal processing method as claimed in claim 8, which is characterized in that step (g) is to be directed to be produced by inspection interlaced frame
Raw this new is exported the time by examining；If step (g) determines that the new time that exported by examining meets the preset condition, step
(h) according to this it is new by examine the setting output of output time with should be by the time of the relevant transmission stream of inspection interlaced frame
Point.
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