CN110310604A

CN110310604A - A kind of driving method of scan drive circuit, display panel and display panel

Info

Publication number: CN110310604A
Application number: CN201910580881.1A
Authority: CN
Inventors: 吴桐; 钱栋
Original assignee: Shanghai Vision Mdt Infotech Ltd
Current assignee: Vision Technology Co ltd
Priority date: 2019-06-29
Filing date: 2019-06-29
Publication date: 2019-10-08
Anticipated expiration: 2039-06-29
Also published as: CN110310604B

Abstract

The embodiment of the invention discloses the driving methods of a kind of scan drive circuit, display panel and display panel.The scan drive circuit includes: the first clock signal input terminal, second clock signal input part, switching signal input terminal, the first latch and control module, the second latch and control module and the first display switching module；The first display switching module latches respectively with the switching signal input terminal, first latch and control module and described second and control module is electrically connected；The first display switching module is used to respond the switching signal of the switching signal input terminal input, exports first shift signal, or output second shift signal.Compared with prior art, the embodiment of the present invention can be compatible with more display patterns, and realize and switchably show plurality of display modes, to enrich the scanning mode of scan drive circuit.

Description

A kind of driving method of scan drive circuit, display panel and display panel

Technical field

The present embodiments relate to field of display technology more particularly to a kind of scan drive circuits, display panel and display The driving method of panel.

Background technique

The continuous promotion of requirement with people to display equipment with the continuous development of display technology, virtual reality (Virtual Reality, VR) shows that equipment enters the visual field of people more and more widely.

In order to realize display effect more abundant, need to show hardware compatibility multi-display function.Wherein, equipment is shown Display function realized by the scanning mode of scan drive circuit.However, the scanning mode list of existing scan drive circuit One, the display function for resulting in display equipment is single, can not be compatible with more, requirements at the higher level display patterns.Therefore, scanning circuit Be designed to developer's one of main research tendency now.

Summary of the invention

The embodiment of the present invention provides the driving method of a kind of scan drive circuit, display panel and display panel, with abundant The scanning mode of scan drive circuit.

In a first aspect, the embodiment of the invention provides a kind of scan drive circuits.When the scan drive circuit includes: first Clock signal input part, second clock signal input part, switching signal input terminal, first latch and control module, second latch and Control module and the first display switching module；

First latch and control module switch with first clock signal input terminal and first display respectively Module electrical connection, first latch and control module are used to respond the first clock letter of the first clock signal input terminal input Number, export the first shift signal；

Second latch and control module switch with the second clock signal input part and first display respectively Module electrical connection, second latch and control module are used to respond the second clock letter of second clock signal input part input Number, export the second shift signal；

It is described first display switching module respectively with the switching signal input terminal, it is described first latch and control module and Second latch and control module electrical connection；The first display switching module is defeated for responding the switching signal input terminal The switching signal entered exports first shift signal, or output second shift signal.

Second aspect, the embodiment of the invention also provides a kind of display panel, which includes: the first clock signal Line, second clock signal wire, line switching signal, scan line and multiple turntable driving electricity such as provided by any embodiment of the invention Road；

First clock signal input terminal of the scan drive circuit is electrically connected with first clock cable, described to sweep The second clock signal input part for retouching driving circuit is electrically connected with the second clock signal wire, the switching signal input terminal with The line switching signal electrical connection, the output end of the scan drive circuit are electrically connected with the scan line；

Multiple scan drive circuit cascade connections.

The third aspect, the embodiment of the invention also provides a kind of driving methods of display panel.The driving of the display panel Method is applicable to display panel provided by any embodiment of the invention.The driving method of the display panel includes:

The first clock signal is sent to first clock cable, Xiang Suoshu second clock signal wire sends second clock Signal, Xiang Suoshu line switching signal send switching signal, and Xiang Suoshu the first enabling signal line sends the first enabling signal, Xiang Suoshu Second enabling signal line sends the second enabling signal；

According to first clock signal and the first enabling signal, the first of multiple scan drive circuits is driven to latch And control module is sequentially output the first shift signal；According to the switching signal, the of multiple scan drive circuits is driven One display switching module is sequentially output first shift signal, and the scan drive circuit is driven to export the first scanning letter step by step Number, the display panel is shown with the first display pattern；

Alternatively, driving multiple scan drive circuits according to the second clock signal and second enabling signal Second latch and control module export the second shift signal；The second of multiple scan drive circuits are driven to show switching mould Block is sequentially output second shift signal, and the scan drive circuit is driven to export the second scanning signal, the display step by step Panel is shown with the second display pattern.

Setting of the embodiment of the present invention first is latched and control module exports the first shift signal, the second latch and control module It is electric with the first display switching module to export the second shift signal, the first latch and control module and the second latch and control module Connection, can be defeated in the scanning signal output end of scan drive circuit by the on state of control the first display switching module First shift signal or the second shift signal out.Compared with prior art, the embodiment of the present invention can be compatible with more displays Mode, and realize and switchably show plurality of display modes, to enrich the scanning mode of scan drive circuit.

Detailed description of the invention

Fig. 1 is a kind of structural schematic diagram of scan drive circuit provided in an embodiment of the present invention；

Fig. 2 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Fig. 3 is a kind of driver' s timing schematic diagram of scan drive circuit provided in an embodiment of the present invention；

Fig. 4 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Fig. 5 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Fig. 6 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Fig. 7 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Fig. 8 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Fig. 9 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Figure 10 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Figure 11 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Figure 12 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention；

Figure 13 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention；

Figure 14 is a kind of structural schematic diagram of scan drive circuit cascade connection provided in an embodiment of the present invention；

Figure 15 is a kind of driver' s timing schematic diagram of display panel provided in an embodiment of the present invention；

Figure 16 is a kind of structural schematic diagram of pixel circuit provided in an embodiment of the present invention；

Figure 17 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention；

Figure 18 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention；

Figure 19 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention；

Figure 20 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention；

Figure 21 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention；

Figure 22 is a kind of flow diagram of the driving method of display panel provided in an embodiment of the present invention；

Figure 23 is a kind of flow diagram of the driving method of display panel provided in an embodiment of the present invention.

Specific embodiment

The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.

Fig. 1 is a kind of structural schematic diagram of scan drive circuit provided in an embodiment of the present invention.Referring to Fig. 1, which is driven Dynamic circuit includes: the first clock signal input terminal CLK1, second clock signal input part CLKR, switching signal input terminal SW, One latch and control module 100, second latch and control module 200 and first shows switching module 300.

First latch and control module 100 show switching module with the first clock signal input terminal CLK1 and first respectively 300 electrical connections, the first latch and control module 100 are used to respond the first clock letter of the first clock signal input terminal CLK1 input Number, export the first shift signal.

Second latch and control module 200 show switching module with second clock signal input part CLKR and first respectively 300 electrical connections, the second latch and control module 200 are used to respond the second clock letter of second clock signal input part CLKR input Number, export the second shift signal.

First display switching module 300 latches respectively with switching signal input terminal SW, first and control module 100 and second It latches and control module 200 is electrically connected；First display switching module 300 is used to respond the switching of switching signal input terminal SW input Signal exports the first shift signal, or the second shift signal of output.

Wherein, the first shift signal and the second shift signal are different shift signals.First shift signal and second moves Position signal for example can be, typical clock signal (normal timing), roll clock signal (Rolling timing), Rolling black clock signal, whole clock signal (global timing), bright clock signal (dimming timing) or One or both of aging clock signal (aging timing).In order to realize the first shift signal and the second shift signal Difference can be set the structure difference of the first latch and control module 100 with the second latch and control module 200, can also set It is different with the clock frequency of second clock signal to set the first clock signal.

Setting of the embodiment of the present invention first is latched and control module 100 exports the first shift signal, and second latches and control Module 200 exports the second shift signal, and first latches and control module 100 and second latches and control module 200 is with first Show that switching module 300 is electrically connected, it can be by the on state of control the first display switching module 300, in turntable driving electricity The scanning signal output end on road exports the first shift signal or the second shift signal.Compared with prior art, the present invention is implemented Example can be compatible with more display patterns, and realize and switchably show plurality of display modes, to enrich turntable driving The scanning mode of circuit.

Fig. 2 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to fig. 2, above-mentioned On the basis of each embodiment, optionally, which further includes third clock signal input terminal XCLK1, the first displacement Signal input part STV and the first junior signal output end NEXTN；The third clock of third clock signal input terminal XCLK1 input Signal is identical as the frequency of the first clock signal that the first clock signal input terminal CLK1 is inputted, and phase is different.

First latch and control module 100 include the first latch 110 and the first logic gates 120.First latch 110 respectively with the first clock signal input terminal CLK1, the first shift signal input terminal STV, the first junior signal output end NEXTN It is electrically connected with the first display switching module 300, the first latch 110 is used to respond the first clock signal input terminal CLK1 input First clock signal latches the shift signal of the first shift signal input terminal STV input, and passes through first junior's signal output end NEXTN output.First logic gates 120 respectively with third clock signal input terminal XCLK1, first junior's signal output end The display switching module 300 of NEXTN and first is electrically connected；First logic gates 120 is for responding first junior's signal output end First junior's signal of NEXTN output, the third clock signal of output third clock signal input terminal XCLK1 input.

Wherein, the first logic gates 120 for example can be NAND gate, the combination with door or multiple logic gate devices, It is NAND gate that the first logic gates 120 is schematically illustrated in Fig. 2.When the first clock signal input terminal CLK1 input first Clock signal, third clock signal input terminal XCLK1 input third clock signal, and switching signal input terminal SW inputs switching signal, First shift signal input terminal STV inputs the first shift signal, and the first junior signal output end NEXTN exports the first junior letter Number.

First latch 110 latches the first shift signal and refers to, when the first clock signal closes first latch 110 When, the first latch 110 can keep level state on last stage.First logic gates 120 responds first junior's signal First junior's signal of output end NEXTN output, the third clock signal that the third clock signal input terminal XCLK1 is inputted Output refers to, when first junior's signal is useful signal, the signal of the first logic gates 120 output is by third clock signal Control.The signal of first logic gates 120 output can be former third clock signal, when being also possible to negated third Clock signal.

Illustratively, the first latch and control module 100 control scan drive circuit and export typical clock signal (normal timing).First display switching module 300 is electrically connected with the scanning signal output end of scan drive circuit, therefore, The signal that first display switching module 300 exports can be directly transferred to scanning signal output end.

If the first display switching module 300 responds switching signal, the first shift signal is exported, that is, exports typical timing letter Number.

Fig. 3 is a kind of driver' s timing schematic diagram of scan drive circuit provided in an embodiment of the present invention, referring to Fig. 3, example Property, the driver' s timing of the scan drive circuit includes first stage T1, second stage T2, phase III T3, fourth stage T4 With the 5th stage T5.

T1 in the first stage, the first shift signal are high level (the first high level pulse stage), and third clock signal is Low level.When the first clock signal is low level, the first latch 110 latches the first shift signal of previous stage, the One junior signal output end NEXTN continues to output low level.When the first clock signal is high level, 110 sound of the first latch The high level for answering the first clock signal exports the first shift signal to the first junior signal output end NEXTN, i.e., under first First junior's signal of grade signal output end NEXTN output is also high level.First logic gates 120 responds the first junior letter Number high level, by the low level output of third clock signal, i.e., first junior's signal be high level when, the first logic gate electricity The signal that road 120 exports is consistent with the level of third clock signal, is low level (Low), thus defeated in scanning signal output end Low level out.

In second stage T2, the first shift signal is high level (the second high level pulse stage), and the first clock signal is Low level.First latch 110 latch first stage T1 the first shift signal, the first junior signal output end NEXTN after Continuous output high level.When third clock signal is low level, the first logic gates 120 responds the height electricity of first junior's signal It is flat, by the low level output of third clock signal.When third clock signal is high level, the response of the first logic gates 120 The high level of first junior's signal, by the high level output of third clock signal, i.e., when first junior's signal is high level, the The signal of one logic gates 120 output is consistent with the level of third clock signal, is high level (High), to believe in scanning Number output end exports high level.

In phase III T3, the first shift signal is low level, and the first clock signal is low level, and third clock signal is Low level.First latch 110 latch second stage T2 the first shift signal, the first junior signal output end NEXTN after Continuous output high level.First logic gates 120 responds the high level of first junior's signal, by the low level of third clock signal Output, i.e., when first junior's signal is high level, the signal of the first logic gates 120 output and the electricity of third clock signal It is flat consistent, be low level (Low), to export low level in scanning signal output end.

In fourth stage T4, the first shift signal is low level, and the first clock signal is high level, and third clock signal is Low level.First latch 110 responds the high level of the first clock signal, and the first shift signal is exported, and believes in the first junior First junior's signal of number output end NEXTN output is also low level.First logic gates 120 responds first junior's signal Low level and export low level, i.e., when first junior's signal is low level, the signal and the of the first logic gates 120 output Three clock signals are unrelated, export low level (Low) always, to export low level in scanning signal output end.

In the 5th stage T5, the first shift signal is low level, and the first clock signal is low level.First latch 110 The first shift signal for latching fourth stage T4, continues to output low level in the first junior signal output end NEXTN.First logic Gate circuit 120 responds the low level of first junior's signal and exports low level, i.e., when first junior's signal is low level, first The signal that logic gates 120 exports is unrelated with third clock signal, low level (Low) is exported always, thus in scanning signal Output end exports low level.

And so on, after the 5th stage T5, the first shift signal remains low level, defeated in scanning signal output end Low level out.

The first shift signal is shifted and is exported by the scan drive circuit as a result, and in the second high electricity of the first shift signal The flat pulse stage exports the high level pulse of third clock signal to scanning signal output end, realizes typical clock signal Output.If the scanning signal is exported in the scanning signal of scan drive circuits at different levels by the scan drive circuit cascade connection End is transmitted step by step, and driving display panel realizes the first display pattern.

Fig. 4 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to fig. 4, above-mentioned On the basis of each embodiment, optionally, scan drive circuit further include: the display switching mould of enabling signal input terminal INB and second Block 400.

Second display switching module 400 respectively with switching signal input terminal SW, the first shift signal input terminal STV, starting Signal input part INB and first is latched and control module 100 is electrically connected, and the second display switching module 400 is for responding switching letter The switching signal of number input terminal SW input, the first shift signal of output the first shift signal input terminal STV input, or output The enabling signal of enabling signal input terminal INB input.First latch and control module 100 further include: the second logic gates 130, the input terminal of the second logic gates 130 is electrically connected with the first junior signal output end NEXTN, the second logic gates 130 output end is electrically connected with the first display switching module 300；Second logic gates 130 is for exporting first junior's signal.

Wherein, the second display switching module 400 for example can be data selector, the address signal of data selector Input terminal is electrically connected with switching signal input terminal SW, and the first data signal input and the first shift signal of data selector are defeated Enter STV is held to be electrically connected, the second data signal input of data selector is electrically connected with enabling signal input terminal INB.Second patrols Collecting gate circuit 130 for example can be the combination of NOT gate, buffer or multiple logic gates.Second logic gates 130 responds simultaneously The first junior's signal for exporting the first junior signal output end NEXTN output refers to that the second logic gates 130 is by the first junior Signal control, the signal of the second logic gates 130 output can be former first junior's signal, be also possible to negated first Junior's signal.

With continued reference to Fig. 4, on the basis of the various embodiments described above, optionally, switching signal input terminal SW is cut including first Change signal input part GI and the second switching signal input terminal RB；First display switching module 300 includes the first data selector 310 With the second data selector 320.

The control terminal of first data selector 310 is electrically connected with the first switching signal input terminal GI, the first data selector 310 first input end is electrically connected with the first logic gates 120, the second input terminal and second of the first data selector 310 Logic gates 130 is electrically connected.

The control terminal of second data selector 320 is electrically connected with the second switching signal input terminal RB, the second data selector 320 first input end is electrically connected with the output end of the first data selector 310, the second input of the second data selector 320 End is latched with second and control module 200 is electrically connected.

Illustratively, when the first switching signal input terminal GI input low level, the second switching signal input terminal RB input is low When level, the output end of the first display switching module 300 and the first logic gates 120 are connected, the first latch and control module The 100 typical clock signals of output；When the first switching signal input terminal GI input high level, the second switching signal input terminal RB is defeated When entering low level, the output end of the first display switching module 300 and the second logic gates 130 are connected, and first latches and control Module 100 exports whole clock signal；When the second switching signal input terminal RB input high level, the first display switching module 300 output end and the second latch and control module 200 are connected.The embodiment of the present invention is realized using two signal controls as a result, The switching of three-way output signal processed.

Wherein, the output of typical clock signal is similar with previous embodiment, and which is not described herein again.Below to whole timing The driving method of signal is illustrated.

Fig. 5 is that the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention shows referring to Fig. 5 Example property, the driver' s timing of the scan drive circuit includes the 6th stage T6, the 7th stage T7, the 8th stage T8, the 9th stage T9, the tenth stage T10 and the 11st stage T11.

In the 6th stage T6, enabling signal is low level.When the first clock signal is low level, the first latch 110 The enabling signal for latching previous stage, continues to output low level in the first junior signal output end NEXTN.When the first clock signal When for high level, the first latch 110 responds the high level of the first clock signal, and enabling signal is exported to first junior's signal Output end NEXTN is also high level in first junior's signal of the first junior signal output end NEXTN output.Second logic Gate circuit 130 responds the low level of first junior's signal, and by the low level output, i.e., the second logic gates 130 will be under first Grade signal directly exports, and the second logic gates 130 exports low level, to export low level in scanning signal output end.

In the 7th stage T7, enabling signal is low level, and the first clock signal is low level.First latch 110 latches The enabling signal of 6th stage T6 continues to output low level in the first junior signal output end NEXTN.Second logic gates The low level of 130 first junior's signals of response, by the low level output, i.e. the second logic gates 130 is by first junior's signal It directly exports, the second logic gates 130 exports low level, to export low level in scanning signal output end.

In the 8th stage T8, enabling signal is low level, and the first clock signal is high level.First latch 110 and The working condition and output signal of two logic gates 130 are identical as the 6th stage T6, and the second logic gates 130 exports low Level, to export low level in scanning signal output end.

In the 9th stage T9, the first clock signal is low level.First latch 110 latches the starting letter of the 8th stage T8 Number, low level is continued to output in the first junior signal output end NEXTN.Second logic gates 130 responds first junior's signal Low level, by the low level output, i.e. the second logic gates 130 directly exports first junior's signal, the second logic gate Circuit 130 exports low level, to export low level in scanning signal output end.

In the tenth stage T10, enabling signal is high level, and the first clock signal is high level.The response of first latch 110 The high level of first clock signal exports enabling signal to the first junior signal output end NEXTN, i.e., in first junior's signal First junior's signal of output end NEXTN output is also high level.Second logic gates 130 responds the height of first junior's signal Level, by the high level output, i.e. the second logic gates 130 directly exports first junior's signal, the second logic gates 130 output high level, to export high level in scanning signal output end.

In the 11st stage T11, enabling signal is high level, and the first clock signal is low level.First latch 110 lock The enabling signal for depositing the tenth stage T10 continues to output high level in the first junior signal output end NEXTN.Second logic gate electricity Road 130 responds the high level of first junior's signal, and by the high level output, i.e. the second logic gates 130 believes the first junior It number directly exports, the second logic gates 130 exports high level, to export high level in scanning signal output end.

And so on, after the 11st stage T11, enabling signal remains high level, and the second logic gates 130 is defeated High level out exports high level in scanning signal output end.

The scan drive circuit exports enabling signal as a result, realizes whole clock signal output, and whole clock signal It is identical as the pulse width of enabling signal, the influence of pulse width not subject clock signal.If the scan drive circuit is cascaded Connection, then the scanning signal exports simultaneously in the scanning signal output end of scan drive circuits at different levels, and driving display panel is realized Whole display pattern.

Fig. 6 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to Fig. 6, above-mentioned On the basis of each embodiment, optionally, scan drive circuit further includes the second shift signal input terminal STVR, second junior's signal Output end NEXTR and first node N1.

Second latch and control module 200 include the second latch 210 and third logic gates 220.Second latch 210 respectively with second clock signal input part CLKR, the second shift signal input terminal STVR and second junior's signal output end NEXTR electrical connection, the second latch 210 are used to respond the second clock signal of second clock signal input part CLKR input, lock The second shift signal of the second shift signal input terminal STVR input is deposited, and is exported by the second junior signal output end NEXTR. The first input end of third logic gates 220 is electrically connected with the second junior signal output end NEXTR, third logic gates 220 the second input terminal is electrically connected with first node N1, the output end of third logic gates 220 and the first display switching module 300 electrical connections；Third logic gates 220 is used to respond and export under the second of the second junior signal output end NEXTR output The current potential of grade signal and first node N1, exports third shift signal.

Wherein, third logic gates 220 for example can be the combination of NOT gate, buffer or multiple logic gates. Third logic gates 220, which responds and exports second junior's signal that the second junior signal output end NEXTR is exported, to be referred to, third Logic gates 220 is controlled by second junior's signal, and the signal that third logic gates 220 exports can be former second junior letter Number, it is also possible to negated second junior signal.Illustratively, first node N1 and first is latched and control module 100 Output end electrical connection.Optionally, first node N1 is electrically connected with the output end of the first logic gates 120.If first node N1 It is electrically connected with the output end of the first logic gates 120, third logic gates 220 is also latched and control module by first Control.

Third shift signal, which for example can be, to be rolled clock signal, rolls black clock signal or bright clock signal Deng.Just roll below clock signal, roll the driving method of clock signal of blacking, bright clock signal and aging clock signal into Row explanation.

Fig. 7 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to Fig. 7, show Example property, if the current potential of first node N1 keeps high level.The driver' s timing of the scan drive circuit included the tenth two-stage T12, the 13rd stage T13, the 14th stage T14, the 15th stage T15, the 16th stage T16 and the 17th stage T17.

In the tenth two-stage T12, the second shift signal is low level, and second clock signal is high level.Second latch The high level of 210 response second clock signals, the second shift signal is exported, and is exported in the second junior signal output end NEXTR Second junior's signal be also low level.Third logic gates 220 responds the low level of second junior's signal, by the low level Output, i.e., third logic gates 220 directly exports second junior's signal, to export low electricity in scanning signal output end It is flat.

In the 13rd stage T13, the second shift signal is low level, and second clock signal is low level.Second latch 210 latch the second shift signal of the tenth two-stage T12, continue to output low level in the second junior signal output end NEXTR.The Three logic gates 220 respond the low level of second junior's signal, and by the low level output, i.e. third logic gates 220 will Second junior's signal directly exports, to export low level in scanning signal output end.

In the 14th stage T14, the second shift signal is low level, and second clock signal is high level.Second latch 210 and third logic gates 220 working condition and output signal it is identical as the tenth two-stage T12, it is defeated in scanning signal Outlet exports low level.

In the 15th stage T15, the second shift signal is low level, and second clock signal is low level.Second latch 210 and third logic gates 220 working condition and output signal it is identical as the 13rd stage T13, it is defeated in scanning signal Outlet exports low level.

In the 16th stage T16, the second shift signal is high level, and second clock signal is high level.Second latch The high level of 210 response second clock signals, the second shift signal is exported to the second junior signal output end NEXTR, that is, is existed Second junior's signal of the second junior signal output end NEXTR output is also high level.The response of third logic gates 220 second The high level of junior's signal, by the high level output, i.e. third logic gates 220 directly exports second junior's signal, from And high level is exported in scanning signal output end.

In the 17th stage T17, the second shift signal is high level, and second clock signal is low level.Second latch 210 latch the second shift signal of the 16th stage T16, continue to output high level in the second junior signal output end NEXTR.The Three logic gates 220 respond the high level of second junior's signal, and by the high level output, i.e. third logic gates 220 will Second junior's signal directly exports, to export high level in scanning signal output end.

And so on, after the 17th stage T17, the second shift signal remains high level, exports in scanning signal End output high level.

The second shift signal is shifted and is exported by the scan drive circuit as a result, is realized and is rolled clock signal output, and rolls Clock signal is identical as the pulse width of the second shift signal, the influence of pulse width not subject clock signal.If by the scanning Driving circuit cascade connection, then the scanning signal is transmitted step by step in the scanning signal output end of scan drive circuits at different levels, driving Display panel realizes scroll display mode.

Fig. 8 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to Fig. 8, show Example property, if the current potential of first node N1 keeps high level.The driver' s timing of the scan drive circuit included the 18th stage T18, the 19th stage T19, the 20th stage T20, the 21st stage T21 and the 20th two-stage T22.

In the 18th stage T18, the second shift signal is low level, and second clock signal is low level.Second latch 210 latch the second shift signal on last stage, continue to output high level in the second junior signal output end NEXTR.Third is patrolled Volume gate circuit 220 responds the high level of second junior's signal, and by the high level output, i.e. third logic gates 220 is by second Junior's signal directly exports, to export high level in scanning signal output end.

In the 19th stage T19, the second shift signal is low level, and second clock signal is high level.Second latch The high level of 210 response second clock signals, the second shift signal is exported, and is exported in the second junior signal output end NEXTR Second junior's signal be also high level.Third logic gates 220 responds the high level of second junior's signal, by the high level Output, i.e., third logic gates 220 directly exports second junior's signal, to export high electricity in scanning signal output end It is flat.

In the 20th stage T20, the second shift signal is low level.If second clock signal is low level, second is latched Device 210 latches the second shift signal on last stage, continues to output low level in the second junior signal output end NEXTR.Third Logic gates 220 responds the low level of second junior's signal, and by the low level output, i.e. third logic gates 220 is by the Two junior's signals directly export, to export low level in scanning signal output end.If second clock signal be high level, second Latch 210 responds the high level of second clock signal, the second shift signal is exported, in second junior's signal output end Second junior's signal of NEXTR output is also low level.Third logic gates 220 responds the low level of second junior's signal, By the low level output, i.e. third logic gates 220 directly exports second junior's signal, thus in scanning signal output end Export low level.

In the 21st stage T21, the second shift signal is high level, and second clock signal is high level.Second latches Device 210 responds the high level of second clock signal, the second shift signal is exported to the second junior signal output end NEXTR, i.e., It is also high level in second junior's signal of the second junior signal output end NEXTR output.The response of third logic gates 220 the The high level of two junior's signals, by the high level output, i.e. third logic gates 220 directly exports second junior's signal, To export high level in scanning signal output end.

In the 20th two-stage T22, the second shift signal is high level, and second clock signal is low level.Second latches Device 210 latches the second shift signal of the 21st stage T21, continues to output high electricity in the second junior signal output end NEXTR It is flat.Third logic gates 220 responds the high level of second junior's signal, by the high level output, i.e. third logic gates 220 directly export second junior's signal, to export high level in scanning signal output end.

And so on, after the 20th two-stage T22, the second shift signal remains high level, defeated in scanning signal Outlet exports high level.

The second shift signal is shifted and is exported by the scan drive circuit as a result, is realized and is rolled clock signal output of blacking, and Rolling clock signal of blacking is identical as the pulse width of the second shift signal, the influence of pulse width not subject clock signal.If By the scan drive circuit cascade connection, then the scanning signal passes step by step in the scanning signal output end of scan drive circuits at different levels It passs, driving display panel, which is realized, rolls display pattern of blacking.Unlike rolling mode, the timing for mode output of blacking is rolled Signal by second clock signal control, and the frequency of second clock signal be higher than the first clock signal frequency.

Fig. 9 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to Fig. 9, show Example property, if the current potential of first node N1 keeps high level.The driver' s timing of the scan drive circuit included the 23rd stage T23, the 24th stage T24 and the 25th stage T25.

In the 23rd stage T23, the second shift signal is low level, and second clock signal is high level.Second latches Device 210 responds the high level of second clock signal, and the second shift signal is exported, defeated in the second junior signal output end NEXTR Second junior's signal out is also low level.Third logic gates 220 responds the low level of second junior's signal, by the low electricity Flat output, i.e., third logic gates 220 directly exports second junior's signal, to export low electricity in scanning signal output end It is flat.

In the 24th stage T24, second clock signal is low level.Second latch 210 latches the on last stage Two shift signals continue to output low level in the second junior signal output end NEXTR.The response of third logic gates 220 second The low level of junior's signal, by the low level output, i.e. third logic gates 220 directly exports second junior's signal, from And low level is exported in scanning signal output end.

In the 25th stage T25, the second shift signal is high level.If second clock signal is high level, the second lock Storage 210 responds the high level of second clock signal, the second shift signal is exported, in the second junior signal output end NEXTR Second junior's signal of output is also high level.Third logic gates 220 responds the high level of second junior's signal, by the height Level output, i.e., third logic gates 220 directly exports second junior's signal, to export in scanning signal output end high Level.If second clock signal is low level, the second latch 210 latches the second shift signal on last stage, under second Grade signal output end NEXTR continues to output high level.Third logic gates 220 responds the high level of second junior's signal, will The high level output, i.e. third logic gates 220 directly export second junior's signal, thus defeated in scanning signal output end High level out.

And so on, after the 25th stage T25, the second shift signal repeats output low level pulse, the scanning Driving circuit repeats the working condition of the 23rd stage T25 of stage T23~the 25th.

The second shift signal is shifted and is exported by the scan drive circuit as a result, realizes bright clock signal output, and bright The influence of the pulse width of clock signal not subject clock signal.If by the scan drive circuit cascade connection, the scanning signal It is transmitted step by step in the scanning signal output end of scan drive circuits at different levels, driving display panel realizes bright display pattern.With rolling Dynamic model formula and rolling are blacked unlike mode, and the clock signal of bright mode output has multiple low level pulses defeated in a frame Out.

Figure 10 is the driver' s timing schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to Figure 10, Illustratively, if the current potential of first node N1 keeps high level.First higher level's signal input part STV and the input of second higher level's signal Hold STVR is low level always, therefore second clock signal input part CLKR can be by the low electricity of second higher level's signal input part STVR Flat write-in second is latched and control module 200, so that the output of scanning signal output end is in low level state, and this state It can be always maintained at down.The second shift signal is shifted and is exported by the scan drive circuit as a result, realizes that aging clock signal is defeated Out, and the influence of the pulse width of aging clock signal not subject clock signal.If, should by the scan drive circuit cascade connection Scanning signal is transmitted step by step in the scanning signal output end of scan drive circuits at different levels, and driving display panel realizes that aging shows mould Formula.

The second of the embodiment of the present invention is latched and control module 200 realizes and rolls clock signal, rolls timing letter of blacking Number, bright clock signal and aging clock signal these four display patterns it is integrated, to be conducive to promote the aobvious of display panel Show quality.

It should be noted that schematically illustrating the second latch in the above-described embodiments and control module 200 can be defeated Clock signal is rolled out, rolls clock signal of blacking, bright clock signal and aging clock signal, not to limit of the invention It is fixed.Can also be set as needed the second latch in other embodiments and control module 200 export typical clock signal or Person's entirety clock signal etc..

It should also be noted that, schematically illustrating first node N1 and the first logic gates in the above-described embodiments 120 output end is electrically connected, not limitation of the invention.In other embodiments, first segment can also be set as needed The third that point N1 is connected to latches and control module, can according to need set in practical applications.

Figure 11 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to Figure 11, upper On the basis of stating each embodiment, optionally, scan drive circuit further include: third latch and control module 500 and the 4th clock Signal input part CLK3.

Third latches and control module 500 latches respectively with the 4th clock signal input terminal CLK3 and second and control module 200 electrical connections, third latches and control module 500 is used to respond the 4th clock letter that the 4th clock signal input terminal CLK3 is inputted Number, export the 4th shift signal.First node N1 is latched with third and the output end of control module 500 is electrically connected.

Wherein, third latches and control module 500 includes third latch 510 and the 4th logic gates 520.Third lock Storage 510 respectively with the 4th clock signal input terminal CLK3, the first shift signal input terminal STV, third junior signal output end NEXTB and first node N1 electrical connection, third latch 510 are used to respond the first of the 4th clock signal input terminal CLK3 input Clock signal latches the shift signal of the first shift signal input terminal STV input, and passes through third junior signal output end NEXTB output.4th logic gates 520 respectively with third clock signal input terminal XCLK1, third junior signal output end NEXTB and first node N1 electrical connection；4th logic gates 520 is for responding third junior signal output end NEXTB output First junior's signal, output third clock signal input terminal XCLK1 input third clock signal.

Setting third of the embodiment of the present invention latches and control module 500 is electrically connected with first node N1, can pass through third It latches and the control of control module 500 second is latched and the output signal of control module 200.For example, rolling timing of blacking in output During signal, more low level pulses can be exported.Therefore, it is defeated to realize signal more abundant for the embodiment of the present invention Out.

It should be noted that in the above embodiments, the first latch 110, the second latch 210 and third latch 510 structure may be the same or different.Just the structure of one of latch is illustrated below, but not as to this The restriction of invention.

With continued reference to Figure 11, optionally, the first latch 110 includes the first phase inverter 111, the second phase inverter 112, third Phase inverter 113 and the 4th phase inverter 114.The input terminal of first phase inverter 111 is electrically connected with the first clock signal input terminal CLK1. First power input of the second phase inverter 112 is electrically connected with the output end of the first phase inverter 111, and the of the second phase inverter 112 Two power inputs are electrically connected with the first clock signal input terminal CLK1, and the input terminal of the second phase inverter 112 and the first higher level believe Number input terminal STV electrical connection.First power input of third phase inverter 113 is electrically connected with first higher level's signal input part STV, The output end of the first phase inverter of second source input terminal 111 of third phase inverter 113 is electrically connected, the input of third phase inverter 113 End is electrically connected with the first junior signal output end NEXTN, 112 output end of the output end of third phase inverter 113 and the second phase inverter Electrical connection.The input terminal of 4th phase inverter 114 is electrically connected with the output end of third phase inverter 113, the output of the 4th phase inverter 114 End is electrically connected with the first junior signal output end NEXTN.

Figure 12 is the structural schematic diagram of another scan drive circuit provided in an embodiment of the present invention.Referring to Figure 12, upper On the basis of stating each embodiment, optionally, scan drive circuit further include: voltage domain expansion module 600.

Voltage domain expansion module 600 is latched with first and control module 100, second latches and control module 200 is electrically connected, Voltage domain expansion module 600 be used for respond first latch and control module 100 output, by the current potential of the first shift signal by Switch between first current potential V1 and the second current potential V2, is extended to and switches between third current potential V3 and the 4th current potential V4.Or electricity Pressure domain expansion module 600 is used to respond second and latches and the output of control module 200, by the current potential of the second shift signal by the Switch between one current potential V1 and the second current potential V2, is extended to and switches between third current potential V3 and the 4th current potential V4.Wherein, | V2- V1 | < | V4-V3 |.

Illustratively, the device in the first latch and control module 100 and the second latch and control module 200 uses 8V device Part, the first clock signal input terminal CLK, second clock signal input part CLKR, on first higher level's signal input part STV and second The voltage domain of the signal of grade signal input part STVR input is 0~5V.First display switching module 300 export the first current potential be 0V, the second current potential are 5V.I.e. when the signal that the first display switching module 300 exports is low level, current potential 0V；When first When the signal for showing that switching module 300 exports is high level, current potential 5V.The third electricity that voltage domain expansion module 600 exports Position is -5V, and the 4th current potential is 5V.When the signal that i.e. voltage domain expansion module 600 exports is low level, current potential is -5V；Work as electricity When the signal for pressing domain expansion module 600 to export is high potential, current potential 5V.Voltage domain expansion module 600 is defeated by scanning signal The voltage domain of outlet is extended to -5V~5V by 0~5V.

Voltage domain expanded mode is arranged between the first display switching module 300 and scanning signal output end in the embodiment of the present invention Block 600 realizes the voltage domain extension of scanning signal output end in the case where applied signal voltage domain is constant.Wherein, it inputs The voltage domain of signal is constant to be conducive to maintain lower circuit power consumption.The extension of output voltage domain is conducive to picture with lower current potential Plain circuit is resetted, better reduction, to be conducive to promote display effect.

With continued reference to Figure 12, on the basis of the various embodiments described above, optionally, voltage domain expansion module 600 includes: first Current potential conversion module 610, the second current potential conversion module 620, third show switching module 630 and current potential selecting module 640.

First current potential conversion module 610 is latched with first and control module 100 is electrically connected, the first current potential conversion module 610 For responding the current potential of the first latch and the output of control module 100, the current potential of the first shift signal is translated, and defeated Out；The current potential of first current potential conversion module 610 output switches between the first current potential V1 and third current potential V3.

Second current potential conversion module 620 is latched with second and control module 200 is electrically connected, the second current potential conversion module 620 For responding the current potential of the second latch and the output of control module 200, the current potential of the second shift signal is translated, and defeated Out；The current potential of second current potential conversion module 620 output switches between the first current potential V1 and third current potential V3.

Third shows that switching module 630 is electric with switching signal input terminal SW, the first current potential conversion module 610 and second respectively Position conversion module 620 is electrically connected, and third shows that switching module 630 is used to respond the switching letter of switching signal input terminal SW input Number, export the level shifted signal of the first shift signal, or the level shifted signal of the second shift signal of output.

Current potential selecting module 640 shows that switching module 630 is electrically connected with the first display switching module 300 and third respectively, Current potential selecting module 640 is used to respond the first display switching module 300 and third shows the current potential that switching module 630 exports, defeated The signal that first display switching module 300 exports out, or output third show the signal that switching module 630 exports.

Wherein, the first current potential conversion module 610 and the second current potential conversion module 620 for example can be level translator.Electricity Position selecting module 640 for example can be data selector.Illustratively, pass through the voltage of the signal all the way of the second data selector Domain is 0~5V, and the voltage domain by the signal all the way of current potential selecting module 640 is -5~0V, i.e., carries out between same voltage domain Data selection.The embodiment of the present invention latches and three road signals and that control module 100 exports in this way, realizing to first The voltage domain extension for the two paths of signals that two latches and control module 200 export.And no setting is required four numbers of the embodiment of the present invention Signal behavior is carried out according to selector, is that the extension for realizing voltage domain and data select only with three data selectors, reduces The usage quantity of device.

With continued reference to Figure 12, on the basis of the various embodiments described above, optionally, scan drive circuit further include: the 5th electricity Position signal input part VGH, the 6th electric potential signal input terminal GND, control of Electric potentials signal input part and current potential select control module 700。

Current potential select control module 700 respectively with the 5th electric potential signal input terminal VGH, the 6th electric potential signal input terminal GND, Control of Electric potentials signal input part and current potential selecting module 640 are electrically connected, and current potential selects control module 700 to control for response pctential The 5th electric potential signal input terminal VGH and current potential selecting module 640 is connected in the control of Electric potentials signal of signal input part input, or The 6th electric potential signal input terminal GND and electric potential signal input terminal is connected.

Wherein, control of Electric potentials signal input part for example may include the electricity of the first control of Electric potentials signal input part XAG and second The current potential of position control signal input AG, the first control of Electric potentials signal input part XAG and the second control of Electric potentials signal input part AG On the contrary.Current potential selecting module 640 for example can be buffer, the first power input of buffer and the first display switching module 300 electrical connections, the second source input terminal of buffer show that switching module 630 is electrically connected with third, the input terminal of buffer and Current potential selects control module 700, and the output end of buffer is electrically connected with scanning signal output end OUT.When current potential selects control mould Block 700 be used for response pctential control signal input input control of Electric potentials signal, conducting the 6th electric potential signal input terminal GND and When electric potential signal input terminal, 0V is exported in the first display switching module 300, when third shows 630 output -5V of switching module, is delayed Device is rushed by -5V voltage output；5V is exported in the first display switching module 300, when third shows that switching module 630 exports 0V, is delayed Device is rushed by 5V voltage output, it is thus achieved that voltage domain is -5V~5V.When current potential selection control module 700 is used for response pctential The control of Electric potentials signal of control signal input input, is connected the 5th electric potential signal input terminal VGH and current potential selecting module 640 When, the output current potential of current potential selecting module 640 drags down, and realizes the output of aging clock signal.

With continued reference to Figure 12, on the basis of the various embodiments described above, optionally, scan drive circuit further include: the 5th electricity Position signal input part VGH, resolution-control signal input terminal, scanning signal output end and resolution ratio control module 800.

Scanning signal output end is electrically connected with the first display switching module 300.Resolution ratio control module 800 is respectively with the 5th Electric potential signal input terminal VGH, resolution-control signal input terminal and the electrical connection of scanning signal output end, resolution ratio control module 800 for responding the resolution-control signal of resolution-control signal input terminal input, conducting output the 5th electric potential signal input Hold VGH and scanning signal output end.

Wherein, resolution-control signal input terminal for example may include first resolution control signal input ENBV and Two resolution-control signal input terminal XENBV；The second resolution of second resolution control signal input XENBV controls signal It is opposite with the first resolution of first resolution control signal input ENBV control signal.Resolution ratio control module 800 includes The first transistor M1, second transistor M2, the 5th phase inverter 810 and hex inverter 820.The control terminal of the first transistor M1 with First resolution control signal input ENBV electrical connection, the first end of the first transistor M1 and the 5th electric potential signal input terminal VGH electrical connection, the second end of the first transistor M1 are electrically connected with scanning signal output end OUT.First electricity of the 5th phase inverter 810 Source input terminal is electrically connected with first resolution control signal input ENBV, the second source input terminal of the 5th phase inverter 810 with Second resolution control signal input XENBV electrical connection, the input terminal of the 5th phase inverter 810 and the first display switching module 300 electrical connections, the output end of the 5th phase inverter 810 are electrically connected with scanning signal output end OUT.The control terminal of second transistor M2 It is electrically connected with second resolution control signal input ENBVN, the first end of second transistor M2 and the 6th electric potential signal input VSS electrical connection is held, the second end of second transistor M2 is electrically connected with scanning signal output end OUT.The first of hex inverter 820 Power input is electrically connected with first resolution control signal input ENBV, the second source input terminal of hex inverter 820 It is electrically connected with second resolution control signal input XENBV, the input terminal and third of hex inverter 820 show switching module 630 electrical connections, the output end of hex inverter 820 are electrically connected with scanning signal output end OUT.

Illustratively, when first resolution control signal is low level, and second resolution control signal is high level, the Five phase inverters 810 and hex inverter 820 disconnect, so that output par, c and earlier logic circuit disconnect, the first transistor Output is pulled to the 5th current potential by M1, and output is pulled to the 6th current potential by second transistor M2.Wherein, the 5th current potential for example can be height Level, the 6th current potential for example can be low level.

Illustratively, which is emission control circuit (EMIT circuit), which controls picture The turn-on and turn-off of plain circuit and luminescent device.For example, when emission control circuit exports high level, pixel circuit and photophore Part disconnects.5th current potential is high level, when first resolution controls signal for the conducting of resolution ratio control module 800, the 5th current potential High level be transmitted to scanning signal output end OUT, the pixel circuit being electrically connected with the scan drive circuit and luminescent device are disconnected It opens, luminescent device does not shine.In a frame, first resolution control signal can convert between high level and low level, When first resolution controls the signal control conducting of resolution ratio control module 800, corresponding pixel does not show picture；It is differentiated first When rate controls the signal control shutdown of resolution ratio control module 800, corresponding pixel shows picture.I.e. the embodiment of the present invention can be selected It selects the position for starting display and terminates the position of display, to realize the function of display area control, enable to display surface The picture of plate output different resolution.

With continued reference to Figure 12, on the basis of the various embodiments described above, optionally, scan drive circuit further includes multiple reverse phases Device 900.Wherein, the inverting action that signal may be implemented is connected in series in odd number phase inverter 900, and even number of inverters 900 is connected Connection will not have an impact the level state of signal.The embodiment of the present invention is arranged multiple phase inverters 900 and is conducive to promote scanning The load capacity of driving circuit.

On the basis of the various embodiments described above, optionally, output voltage domain is the phase inverter 900 in the branch of -5~0V The quantity of phase inverter 900 in branch that quantity is 0~5V with output voltage domain is equal, is conducive to promote scan drive circuit The symmetry of output signal.

With continued reference to Figure 12, on the basis of the various embodiments described above, optionally, which further includes resetting letter Number input terminal RST, third transistor M3 and the 4th transistor M4.The control terminal and reset signal input terminal of third transistor M3 RST electrical connection, the first end of third transistor M3 is electrically connected with the 5th electric potential signal input terminal VGH, and the of third transistor M3 Two ends are electrically connected with the output end of the first display switching module 300.The control terminal and reset signal input terminal of 4th transistor M4 RST electrical connection, the first end of the 4th transistor M4 is electrically connected with the 6th electric potential signal input terminal GND, and the of the 4th transistor M4 Two ends show that switching module 630 is electrically connected with third.The embodiment of the present invention is in this way, may be implemented to scanning signal output end The reset of OUT signal.

With continued reference to Figure 12, on the basis of the various embodiments described above, optionally, the first latch and control module 100 are also wrapped It includes the 5th transistor M5, the second latch and control module 200 further includes the 6th transistor M6, third latches and control module 500 It further include the 7th transistor M7.The control terminal of 5th transistor M5, the 6th transistor M6 and the 7th transistor M7 are believed with reset The first end of number input terminal RST electrical connection, the 5th transistor M5, the 6th transistor M6 and the 7th transistor M7 with the 5th current potential Signal input part VGH electrical connection, the second end of the 5th transistor M5 are electrically connected with the first junior signal output end NEXTN, and the 6th The second end of transistor M6 is electrically connected with the second junior signal output end NEXTR, under the second end and third of the 7th transistor M7 Grade signal output end NEXTB electrical connection.The embodiment of the present invention is in this way, realize the reset to Latch output signal.

The embodiment of the invention also provides a kind of display panels.The display panel for example can be micro- Organic Light Emitting Diode Display panel (micro-OLED), organic LED display panel (OLED), micro- LED display panel (micro- ) or liquid crystal display panel (LCD) LED.Illustratively, which is applicable to VR and shows that equipment etc. is high-resolution aobvious Show equipment, is readily applicable to computer, mobile phone, tablet computer etc. and shows equipment.

Figure 13 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention.Referring to Figure 13, the display panel It include: that the first clock cable 10, second clock signal wire 20, line switching signal 30, scan line 40 and multiple such as present invention appoint Scan drive circuit 40 provided by embodiment of anticipating.First clock signal input terminal of scan drive circuit 40 and the first clock are believed Number line 10 is electrically connected, and the second clock signal input part of scan drive circuit 40 is electrically connected with second clock signal wire 20, switching Signal input part is electrically connected with line switching signal 30, and the output end of scan drive circuit 40 is electrically connected with scan line 40.It is multiple to sweep Retouch 40 cascade connection of driving circuit.

The first latch and control module output the is arranged in the embodiment of the present invention in the scan drive circuit 40 of display panel One shift signal, second latch and control module export the second shift signal, first latch and control module and second latch and Control module is electrically connected with the first display switching module, and the on state of switching module can be shown by control first, The scanning signal output end of scan drive circuit exports the first shift signal or the second shift signal.Compared with prior art, The embodiment of the present invention can be compatible with more display patterns, and realize and switchably show plurality of display modes, thus abundant The scanning mode of scan drive circuit, enriches the display pattern of display panel.

Figure 14 is a kind of structural schematic diagram of scan drive circuit cascade connection provided in an embodiment of the present invention.Referring to figure 14, the display panel further include: third clock cable 11, the 4th clock cable 51, the 5th clock cable 21 and the 6th Clock cable 52.

First clock signal input terminal of odd level scan drive circuit is electrically connected with the first clock cable 10, odd level The second clock signal input part of scan drive circuit is electrically connected with second clock signal wire 20, odd level scan drive circuit Third clock signal input terminal is electrically connected with third clock cable 11, and the 4th clock signal of odd level scan drive circuit is defeated Enter end to be electrically connected with the 4th clock cable 51, the 5th clock signal input terminal of odd level scan drive circuit and the 5th clock Signal wire 21 is electrically connected, and the 6th clock signal input terminal and the 6th clock cable 52 of odd level scan drive circuit are electrically connected It connects.

First clock signal input terminal of even level scan drive circuit is electrically connected with third clock cable 11, even level The second clock signal input part of scan drive circuit is electrically connected with the 5th clock cable 21, even level scan drive circuit Third clock signal input terminal is electrically connected with the first clock cable 10, and the 4th clock signal of even level scan drive circuit is defeated Enter end to be electrically connected with the 6th clock cable 52, the 5th clock signal input terminal and second clock of even level scan drive circuit Signal wire 20 is electrically connected, and the 6th clock signal input terminal and the 4th clock cable 51 of even level scan drive circuit are electrically connected It connects.

Figure 15 is a kind of driver' s timing schematic diagram of display panel provided in an embodiment of the present invention.Referring to Figure 15, exporting Under the display pattern of typical clock signal, the output pulse of odd level scan drive circuit is corresponding with the first clock signal, even It is corresponding with second clock signal that several levels scan drive circuit exports pulse.Each scanning drive signal hands on step by step.

Be scanned for below driving circuit output scanning signal driving display panel realize the first display pattern principle into Row explanation.The scanning signal output end of scan drive circuit 50 is electrically connected by scan line 40 with the pixel of display panel.

Figure 16 is a kind of structural schematic diagram of pixel circuit provided in an embodiment of the present invention.Referring to Figure 16, the pixel circuit Including data signal input VDATA, the first scanning signal input terminal WS_1, the second scanning signal input terminal WS_2, the first ginseng Examine signal end NCP, the second reference signal end VFB, the first power end ELVDD, second source end ELVSS, LED control signal end EMIT, driving transistor MD, input module MS1, reseting module MS2, light emitting control module MS3 and capacitor C1.Input module MS1 Control terminal be electrically connected with the first scanning signal input terminal WS_1, the first end and data signal input of input module MS1 The second end of VDATA electrical connection, input module MS1 is electrically connected with the control terminal of driving transistor MD.The first end of capacitor C1 with The second end of first reference signal end NCP electrical connection, capacitor C1 is electrically connected with the control terminal of driving transistor MD.Drive transistor The first end of MD is electrically connected with the first power end ELVDD.The control terminal of reseting module MS2 and the second scanning signal input terminal WS_2 Electrical connection, the first end of reseting module MS2 are electrically connected with the second reference signal end VFB, the second end and driving of reseting module MS2 The second end of transistor MD is electrically connected.The control terminal of light emitting control module MS3 is electrically connected with LED control signal end EMIT, is shone The first end of control module MS3 be electrically connected with the second end of driving transistor MD, the second end of light emitting control module MS3 with it is luminous The anode of device OLED is electrically connected.The cathode of luminescent device OLED is electrically connected with second source end ELVSS.

Illustratively, which is emission control circuit, and scanning signal output end and pixel circuit shine Control terminal EMIT electrical connection.Under typical clock signal output mode, in the first high level pulse stage of higher level's shift signal, Pixel circuit is in reseting stage, and each node and luminescent device anode do and reset inside pixel circuit.In higher level's shift signal When the second high level pulse stage, scanning signal output end exports high level, and pixel circuit and luminescent device disconnect, luminescent device It does not shine, pixel circuit is in data write phase, by data-signal write driver transistor.It can be seen that when typical Under sequential signal output mode, in a frame, only at the second high level pulse stage of higher level's shift signal, scanning signal output End output high level, pixel circuit and luminescent device disconnect, and luminescent device does not shine.

Figure 17 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention.Referring to Figure 17, example Property, under the display pattern for exporting whole clock signal, scanning drive signals at different levels export identical signal simultaneously.So, The whole display that whole pixels open simultaneously may be implemented in the display panel.

Figure 18 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention.Referring to Figure 18, example Property, under the display pattern that output rolls clock signal, the output pulse of odd level scan drive circuit and the first clock are believed Number correspondence, it is corresponding with second clock signal that even level scan drive circuit exports pulse.Under each scanning drive signal is transmitted step by step It goes.

Illustratively, which is emission control circuit, and scanning signal output end and pixel circuit shine Control terminal EMIT electrical connection.It rolls under clock signal output mode, the pulse width of LED control signals at different levels and enabling signal It is all the same, the influence of pulse width not subject clock signal.When scanning signal output end export high level, pixel circuit and shine Device disconnects, and luminescent device does not shine；When scanning signal output end exports low level, pixel circuit is connected with luminescent device, sends out Optical device shines.And fluorescent lifetime of the luminescent device in a frame is determined by the pulse width of enabling signal.

Optionally, the pulse width of enabling signal is wide greater than the pulse of the first clock signal on the first clock cable 50 Degree, and the pulse width for the second clock signal being greater than on second clock signal wire 60.The scanning of scan drive circuits at different levels is believed Number output end OUT successively shifts output scanning signal, and the pulse width of scanning signal is equal with the pulse width of enabling signal.

Illustratively, it rolls under clock signal output mode, in a frame, compared to typical clock signal, Shang Jiyi The low level time of position signal greatly reduces, for example, the pulse width of the low level pulse is only the 20% of a frame time.That , the time that pixel circuit is connected with luminescent device is only the 20% of a frame time, in the remaining time, pixel circuit and shine Device disconnects, and luminescent device does not shine.Therefore, in the case where rolling clock signal output mode, the height of scanning signal output end output Level time has been more than 2 high level pulse stages of higher level's shift signal.

Figure 19 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention.Referring to Figure 19, example Property, under the display pattern that output rolls clock signal of blacking, when the output pulse of odd level scan drive circuit is with first Clock signal is corresponding, and it is corresponding with second clock signal that even level scan drive circuit exports pulse.Each scanning drive signal passes step by step It passs down.Since the clock frequency of second clock signal is greater than the clock frequency of the first clock signal, adjacent two-stage scan The interval of driving signal output is smaller, and the time that entire display panel is completed in scanning is shorter.

Figure 20 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention.Referring to fig. 20, example Property, under the display pattern for exporting bright clock signal, the output pulse of odd level scan drive circuit and the first clock are believed Number correspondence, it is corresponding with second clock signal that even level scan drive circuit exports pulse.Under each scanning drive signal is transmitted step by step It goes.

Figure 21 is the driver' s timing schematic diagram of another display panel provided in an embodiment of the present invention.Referring to fig. 21, example Property, under the display pattern of output aging clock signal, output par, c and earlier logic circuit are disconnected, turntable driving electricity at different levels Road exports low level, so that pixel circuit is connected with luminescent device OLED.

With continued reference to Figure 14, on the basis of the various embodiments described above, optionally, which further includes forward scan control Signal wire 61 and reverse scan control signal wire 62 processed.Scan drive circuit include forward scan control signal input U2D and Reverse scan control signal input D2U, forward scan control signal input U2D are electrically connected with forward scan control signal wire 61 It connects, reverse scan control signal input D2U is electrically connected with reverse scan control signal wire 62.The embodiment of the present invention is arranged in this way The forward scan and reverse scan for realizing display panel, further enrich the display pattern of display panel.

It should be noted that schematically illustrate in the above-described embodiments display panel resolution ratio be 1920 × 1200, and be divided into three scan drive circuit module EMIT_2, not limitation of the invention.In other embodiments, also The resolution ratio that display panel can be set is higher, or the resolution ratio of setting display panel is lower, in practical applications can root It is configured according to needs.

The embodiment of the invention also provides a kind of driving methods of display panel.The driving method of the display panel is applicable In display panel provided by any embodiment of the invention.Figure 22 is a kind of driving of display panel provided in an embodiment of the present invention The flow diagram of method.Referring to fig. 22, the driving method of the display panel the following steps are included:

S110, the first clock signal is sent to the first clock cable, sends second clock letter to second clock signal wire Number, switching signal is sent to line switching signal, the first enabling signal is sent to the first enabling signal line, to the second enabling signal line Send the second enabling signal.

S120, according to the first clock signal and the first enabling signal, drive the first of multiple scan drive circuits latch and Control module is sequentially output the first shift signal；According to switching signal, the first of multiple scan drive circuits is driven to show switching Module is sequentially output the first shift signal, and driving scan drive circuit exports the first scanning signal step by step, and display panel is with first Display pattern is shown；Alternatively, driving the second of multiple scan drive circuits to lock according to second clock signal and the second enabling signal It deposits and control module exports the second shift signal；The second of multiple scan drive circuits are driven to show that switching module is sequentially output the Two shift signals, driving scan drive circuit export the second scanning signal step by step, and display panel is shown with the second display pattern.

The embodiment of the present invention is shown by driving scan drive circuit to export the first scanning signal step by step according to switching signal Show that panel is shown with the first display pattern；Alternatively, driving scan drive circuit exports the second scanning signal step by step, display panel with Second display pattern is shown.Compared with prior art, the embodiment of the present invention can be compatible with more display patterns, and realizing can Switching ground display plurality of display modes, to enrich the scanning mode of scan drive circuit.

On the basis of the various embodiments described above, optionally, the first display pattern includes: that the first scanning signal includes the first electricity Gentle second electrical level, the pulse width of the first level pulse are equal to the pulse width of second clock signal；Second electrical level is for leading Logical scan line.

On the basis of the various embodiments described above, optionally, the second display pattern includes: that the second scanning signal includes the first electricity Gentle second electrical level, the pulse width of the first level pulse are greater than the period of second clock signal；Second electrical level is swept for being connected Retouch line.

On the basis of the various embodiments described above, optionally, the second enabling signal includes the first level and second electrical level, one In frame, the quantity at least two of second electrical level pulse.

Second display pattern includes: that the second scanning signal includes the first level and second electrical level, in a frame, second electrical level The quantity of pulse is at least two；Second electrical level is for being connected scan line.

On the basis of the various embodiments described above, optionally, the frequency of second clock signal is greater than the frequency of the first clock signal Rate；Second enabling signal includes the first level and second electrical level, and the second electrical level pulse of the second enabling signal is located at a frame time Later period.

Second scanning signal includes the first level and second electrical level, and the second electrical level pulse of the second scanning signal is located at a frame The later period of time；Second electrical level is for being connected scan line.

Figure 23 is a kind of flow diagram of the driving method of display panel provided in an embodiment of the present invention.Referring to fig. 23, On the basis of the various embodiments described above, optionally, the driving method of the display panel the following steps are included:

S210, the first clock signal is sent to the first clock cable, sends third clock letter to third clock cable Number, switching signal is sent to line switching signal, sends the first enabling signal to the first enabling signal line；

S220, according to switching signal, drive the second of multiple scan drive circuits to show switching module conducting enabling signal Input terminal and the first latch and control module；

S230, according to the first clock signal, drive the first latches first of multiple scan drive circuits to start letter Number, obtain first junior's signal；

S240, according to first junior's signal, drive the second logic gates of multiple scan drive circuits while output the Three shift signals；

S250, according to switching signal, driving the first display switching module exports third shift signal, driving turntable driving electricity Road exports third scanning signal step by step, and display panel is shown with third display pattern.

On the basis of the various embodiments described above, optionally, the driving method of display panel, further includes:

The 5th electric potential signal is sent to the 5th electric potential signal line.

In the part-time of a frame, resolution-control signal is sent to resolution-control signal line.

According to resolution-control signal, drive resolution ratio control module that the 5th electric potential signal input terminal and scanning signal is connected Output end, scanning signal output end export second electrical level；Second electrical level is for being connected scan line.

On the basis of the various embodiments described above, optionally, in a frame, the second enabling signal permanent second level.

Second display pattern includes: the second scanning signal permanent second level in a frame；Second electrical level is swept for being connected Retouch line.

The 5th electric potential signal is sent to the 5th electric potential signal line, sends the 6th electric potential signal to the 6th electric potential signal line, to Control of Electric potentials signal wire sends control of Electric potentials signal.

According to control of Electric potentials signal, drive current potential selection control module that the 5th electric potential signal input terminal and current potential selection is connected Module.

Current potential selecting module is driven to export second electrical level；Second electrical level is for being connected scan line.

Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation, It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.

Claims

1. a kind of scan drive circuit characterized by comprising

First clock signal input terminal, second clock signal input part, switching signal input terminal, the first latch and control module, Second latch and control module and the first display switching module；

First latch and control module show switching module with first clock signal input terminal and described first respectively Electrical connection, first latch and control module are used to respond the first clock signal of the first clock signal input terminal input, defeated First shift signal out；

Second latch and control module show switching module with the second clock signal input part and described first respectively Electrical connection, second latch and control module are used to respond the second clock signal of second clock signal input part input, defeated Second shift signal out；

The first display switching module latches respectively with the switching signal input terminal, described first and control module and described Second latch and control module electrical connection；The first display switching module is used to respond the switching signal input terminal input Switching signal exports first shift signal, or output second shift signal.

2. scan drive circuit according to claim 1, which is characterized in that further include third clock signal input terminal, One shift signal input terminal and first junior's signal output end；The third clock signal of the third clock signal input terminal input It is identical as the frequency of the first clock signal of first clock signal input terminal input, and phase is different；

First latch and control module include the first latch and the first logic gates；

First latch respectively with first clock signal input terminal, the first shift signal input terminal, described One junior's signal output end and the first display switching module electrical connection, first latch is for when responding described first First clock signal of clock signal input part input, latches the shift signal of the first shift signal input terminal input, and leads to Cross the output of first junior signal output end；

First logic gates respectively with the third clock signal input terminal, first junior signal output end and institute State the electrical connection of the first display switching module；First logic gates is for responding the output of first junior signal output end First junior's signal, export the third clock signal of third clock signal input terminal input.

3. scan drive circuit according to claim 2, which is characterized in that further include: enabling signal input terminal and second Show switching module；

It is described second display switching module respectively with the switching signal input terminal, the first shift signal input terminal, the starting Signal input part and first latch and control module electrical connection, the second display switching module is for responding the switching The switching signal of signal input part input exports the first shift signal or defeated of the first shift signal input terminal input The enabling signal of the enabling signal input terminal input out；

It is described first latch and control module further include: the second logic gates, the input terminal of second logic gates with The electrical connection of first junior signal output end, the output end of second logic gates and the first display switching module Electrical connection；Second logic gates is for exporting first junior signal.

4. scan drive circuit according to claim 3, which is characterized in that the switching signal input terminal is cut including first Change signal input part and the second switching signal input terminal；The first display switching module includes the first data selector and second Data selector；

The control terminal of first data selector is electrically connected with the first switching signal input terminal, the first data selection The first input end of device is electrically connected with first logic gates, the second input terminal of first data selector with it is described The electrical connection of second logic gates；

The control terminal of second data selector is electrically connected with the second switching signal input terminal, the second data selection The first input end of device is electrically connected with the output end of first data selector, the second input of second data selector End is latched with described second and control module is electrically connected.

5. scan drive circuit according to claim 1, which is characterized in that further include the second shift signal input terminal, Two junior's signal output ends and first node；

Second latch and control module include the second latch and third logic gates；

Second latch is respectively and under the second clock signal input part, the second shift signal input terminal and described second Grade signal output end electrical connection, second latch are used to respond the second clock of the second clock signal input part input Signal, latches the second shift signal of the second shift signal input terminal input, and is exported by second junior signal End output；

The first input end of the third logic gates is electrically connected with second junior signal output end, the third logic Second input terminal of gate circuit is electrically connected with the first node, and the output end of the third logic gates is aobvious with described first Show that switching module is electrically connected；The third logic gates is used to respond and export the output of second junior signal output end The current potential of second junior's signal and the first node exports third shift signal.

6. scan drive circuit according to claim 5, which is characterized in that further include: third latch and control module and 4th clock signal input terminal；

The third latches and control module latches respectively with the 4th clock signal input terminal and described second and control mould Block electrical connection, the third latches and control module is used to respond the 4th clock signal of the 4th clock signal input terminal input, Export the 4th shift signal；

The first node is latched with the third and the output end of control module is electrically connected.

7. scan drive circuit according to claim 5, which is characterized in that the first node and it is described first latch and The output end of control module is electrically connected.

8. scan drive circuit according to claim 1, which is characterized in that further include: voltage domain expansion module；

The voltage domain expansion module is latched with described first and control module, the second latch and control module are electrically connected, described Voltage domain expansion module be used for respond it is described first latch and control module output, by the current potential of first shift signal by Switch between the first current potential V1 and the second current potential V2, is extended to and switches between third current potential V3 and the 4th current potential V4；Or Second latch and the output of control module are responded, by the current potential of second shift signal by the first current potential V1 and second Switch between current potential V2, is extended to and switches between third current potential V3 and the 4th current potential V4；

Wherein, | V2-V1 | < | V4-V3 |.

9. scan drive circuit according to claim 8, which is characterized in that the voltage domain expansion module includes: first Current potential conversion module, the second current potential conversion module, third show switching module and current potential selecting module；

The first current potential conversion module is latched with described first and control module is electrically connected, and the first current potential conversion module is used In the current potential for responding first latch and the output of control module, the current potential of first shift signal is translated, and Output；The current potential of the first current potential conversion module output switches between the first current potential V1 and third current potential V3；

The second current potential conversion module is latched with described second and control module is electrically connected, and the second current potential conversion module is used In the current potential for responding second latch and the output of control module, the current potential of second shift signal is translated, and Output；The current potential of the second current potential conversion module output switches between the first current potential V1 and third current potential V3；

The third show switching module respectively with the switching signal input terminal, the first current potential conversion module and described the The electrical connection of two current potential conversion modules, the third show that switching module is used to respond the switching of the switching signal input terminal input Signal exports the level shifted signal of first shift signal, or the level conversion letter of output second shift signal Number；

The current potential selecting module shows that switching module is electrically connected with the first display switching module and the third respectively, institute It states current potential selecting module and shows the current potential of switching module output for responding the first display switching module and the third, it is defeated The signal of the first display switching module output out, or the output third show the signal of switching module output.

10. scan drive circuit according to claim 9, which is characterized in that further include: the 5th electric potential signal input terminal, 6th electric potential signal input terminal, control of Electric potentials signal input part and current potential select control module；

Current potential selection control module respectively with the 5th electric potential signal input terminal, the 6th electric potential signal input terminal, The control of Electric potentials signal input part and the electrical connection of current potential selecting module, the current potential selection control module is for responding the electricity The control of Electric potentials signal of position control signal input input, is connected the 5th electric potential signal input terminal and the current potential selects mould Block, or the 6th electric potential signal input terminal and the electric potential signal input terminal is connected.

11. scan drive circuit according to claim 1, which is characterized in that further include: the 5th electric potential signal input terminal, Resolution-control signal input terminal, scanning signal output end and resolution ratio control module；

The scanning signal output end is electrically connected with the first display switching module；

The resolution ratio control module respectively with the 5th electric potential signal input terminal, the resolution-control signal input terminal and The scanning signal output end electrical connection, the resolution ratio control module are defeated for responding the resolution-control signal input terminal The output the 5th electric potential signal input terminal and the scanning signal output end is connected in the resolution-control signal entered.

12. a kind of display panel characterized by comprising the first clock cable, second clock signal wire, line switching signal, Scan line and multiple such as described in any item scan drive circuits of claim 1-11；

First clock signal input terminal of the scan drive circuit is electrically connected with first clock cable, and the scanning is driven The second clock signal input part of dynamic circuit is electrically connected with the second clock signal wire, the switching signal input terminal with it is described Line switching signal electrical connection, the output end of the scan drive circuit are electrically connected with the scan line；

Multiple scan drive circuit cascade connections.

13. a kind of driving method of display panel, which is characterized in that the display panel includes the first clock cable, second Clock cable, line switching signal, the first enabling signal line, the second enabling signal line, scan line and multiple such as claim 1 institute The scan drive circuit stated；

First clock signal input terminal of the scan drive circuit is electrically connected with first clock cable, and the scanning is driven The second clock signal input part of dynamic circuit is electrically connected with the second clock signal wire, the switching signal input terminal with it is described Line switching signal electrical connection, the output end of the scan drive circuit are electrically connected with the scan line；Multiple turntable drivings Circuits cascading connection；

The driving method of the display panel includes:

The first clock signal is sent to first clock cable, Xiang Suoshu second clock signal wire sends second clock letter Number, Xiang Suoshu line switching signal sends switching signal, and Xiang Suoshu the first enabling signal line sends the first enabling signal, Xiang Suoshu the Two enabling signal lines send the second enabling signal；

According to first clock signal and the first enabling signal, the first of multiple scan drive circuits are driven to latch and control Molding block is sequentially output the first shift signal；According to the switching signal, drive the first of multiple scan drive circuits aobvious Show that switching module is sequentially output first shift signal, the scan drive circuit driven to export the first scanning signal step by step, The display panel is shown with the first display pattern；

Alternatively, according to the second clock signal and second enabling signal, the of multiple scan drive circuits is driven Two latches and control module export the second shift signal；Drive multiple scan drive circuits second show switching module according to Secondary output second shift signal, drives the scan drive circuit to export the second scanning signal, the display panel step by step It is shown with the second display pattern.

14. the driving method of display panel according to claim 13, which is characterized in that first enabling signal includes First level and second electrical level, the pulse width of first level pulse are equal with the period of first clock signal；

First display pattern includes: that first scanning signal includes the first level and second electrical level, first level The pulse width of pulse is equal to the pulse width of the second clock signal；The second electrical level is for being connected the scan line.

15. the driving method of display panel according to claim 13, which is characterized in that second enabling signal includes First level and second electrical level, the pulse width of first level pulse are greater than the period of the second clock signal；

Second display pattern includes: that second scanning signal includes the first level and second electrical level, first level The pulse width of pulse is greater than the period of the second clock signal；The second electrical level is for being connected the scan line.

16. the driving method of display panel according to claim 13, which is characterized in that second enabling signal includes First level and second electrical level, in a frame, the quantity at least two of the second electrical level pulse；

Second display pattern includes: that second scanning signal includes the first level and second electrical level, described in a frame The quantity of second electrical level pulse is at least two；The second electrical level is for being connected the scan line.

17. the driving method of display panel according to claim 13, which is characterized in that the scan drive circuit also wraps It includes: the second shift signal input terminal, second junior's signal output end and first node；

The first input end of the third logic gates is electrically connected with second junior signal output end, the third logic Second input terminal of gate circuit is electrically connected with the first node, and the output end of the third logic gates is aobvious with described first Show that switching module is electrically connected；The third logic gates is used to respond and export the output of second junior signal output end The current potential of second junior's signal and the first node exports third shift signal；

The driving method of the display panel further include: the frequency of the second clock signal is greater than first clock signal Frequency；Second enabling signal includes the first level and second electrical level, the second electrical level pulse position of second enabling signal In the later period of a frame time；

Second scanning signal includes the first level and second electrical level, and the second electrical level pulse of second scanning signal is located at The later period of one frame time；The second electrical level is for being connected the scan line.

18. the driving method of display panel according to claim 13, which is characterized in that the scan drive circuit also wraps Include: third clock signal input terminal, the first shift signal input terminal, first junior's signal output end, enabling signal input terminal and Second display switching module；The third clock signal and first clock signal of the third clock signal input terminal input are defeated The frequency for entering the first clock signal of end input is identical, and phase is different；The enabling signal input terminal and first starting Signal wire electrical connection；

First logic gates respectively with the third clock signal input terminal, first junior signal output end and institute State the electrical connection of the first display switching module；First logic gates is for responding the output of first junior signal output end First junior's signal, export the third clock signal of third clock signal input terminal input；

The second display switching module is believed with starting described in the switching signal input terminal, the first shift signal input terminal respectively Number input terminal and described first latches and control module electrical connection, the second display switching module are believed for responding the switching The switching signal of number input terminal input exports the first shift signal of the first shift signal input terminal input, or output The enabling signal of the enabling signal input terminal input；

It is described first latch and control module further include: the second logic gates, the input terminal of second logic gates with The electrical connection of first junior signal output end, the output end of second logic gates and the first display switching module Electrical connection；Second logic gates is for exporting first junior signal；

The driving method of the display panel, further includes:

The first clock signal is sent to first clock cable, Xiang Suoshu third clock cable sends third clock letter Number, Xiang Suoshu line switching signal sends switching signal, and Xiang Suoshu the first enabling signal line sends the first enabling signal；

According to the switching signal, drive the second display switching module of multiple scan drive circuits that the starting letter is connected Number input terminal and described first latches and control module；

According to first clock signal, the first starting described in the first latches of multiple scan drive circuits is driven Signal obtains first junior's signal；

According to first junior signal, the second logic gates of multiple scan drive circuits is driven to export third simultaneously Shift signal；

According to the switching signal, driving the first display switching module exports the third shift signal, and the scanning is driven to drive Dynamic circuit exports third scanning signal step by step, and the display panel is shown with third display pattern.

19. the driving method of display panel according to claim 13, which is characterized in that the display panel further includes Five electric potential signal lines and resolution-control signal line；

The scan drive circuit further include: the 5th electric potential signal input terminal, resolution-control signal input terminal, scanning signal are defeated Outlet and resolution ratio control module；The 5th electric potential signal input terminal is electrically connected with the 5th electric potential signal line, and described point Resolution control signal input is electrically connected with the resolution-control signal line；

The resolution ratio control module respectively with the 5th electric potential signal input terminal, the resolution-control signal input terminal and The scanning signal output end electrical connection；

The driving method of the display panel, further includes:

The 5th electric potential signal is sent to the 5th electric potential signal line；

In the part-time of a frame, Xiang Suoshu resolution-control signal line sends resolution-control signal；

According to the resolution-control signal, drive the resolution ratio control module be connected the 5th electric potential signal input terminal and The scanning signal output end, the scanning signal output end export second electrical level；The second electrical level is for being connected described sweep Retouch line.

20. the driving method of display panel according to claim 13, which is characterized in that in a frame, described second is opened Dynamic signal permanent second level；

Second display pattern includes: the second scanning signal permanent second level in a frame；The second electrical level is used In the conducting scan line.

21. the driving method of display panel according to claim 13, which is characterized in that the display panel further includes Five electric potential signal lines, the 6th electric potential signal line and control of Electric potentials signal wire；

The scan drive circuit further include: the 5th electric potential signal input terminal, the 6th electric potential signal input terminal, control of Electric potentials signal Input terminal and current potential select control module；The 5th electric potential signal input terminal is electrically connected with the 5th electric potential signal line, institute It states the 6th electric potential signal input terminal to be electrically connected with the 6th electric potential signal line, the electric potential signal input terminal and the current potential control Signal wire electrical connection processed；

Current potential selection control module respectively with the 5th electric potential signal input terminal, the 6th electric potential signal input terminal, The control of Electric potentials signal input part and the electrical connection of current potential selecting module；

The driving method of the display panel, further includes:

The 5th electric potential signal is sent to the 5th electric potential signal line, the 6th electric potential signal is sent to the 6th electric potential signal line, to current potential Control signal wire sends control of Electric potentials signal；

According to the control of Electric potentials signal, drive the current potential selection control module be connected the 5th electric potential signal input terminal and The current potential selecting module；

Drive the current potential selecting module output second electrical level；The second electrical level is for being connected the scan line.