CN110299901B - Controllable algorithm for circulating on-off program - Google Patents
Controllable algorithm for circulating on-off program Download PDFInfo
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- CN110299901B CN110299901B CN201910452066.7A CN201910452066A CN110299901B CN 110299901 B CN110299901 B CN 110299901B CN 201910452066 A CN201910452066 A CN 201910452066A CN 110299901 B CN110299901 B CN 110299901B
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- C—CHEMISTRY; METALLURGY
- C21—METALLURGY OF IRON
- C21B—MANUFACTURE OF IRON OR STEEL
- C21B5/00—Making pig-iron in the blast furnace
- C21B5/006—Automatically controlling the process
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- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G15/00—Time-pieces comprising means to be operated at preselected times or after preselected time intervals
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0426—Programming the control sequence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
- H03K3/66—Generators producing trains of pulses, i.e. finite sequences of pulses by interrupting the output of a generator
- H03K3/70—Generators producing trains of pulses, i.e. finite sequences of pulses by interrupting the output of a generator time intervals between all adjacent pulses of one train being equal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
Abstract
The invention discloses an algorithm of a controllable circulation on-off program, which mainly relates to the technical field of a blast furnace feeding system and comprises a setting and resetting control part, a circulation counting part and a circulation control part, wherein the circulation counting part controls a switching value output value so that the switching value output value can be controlled to do the actions of setting at regular time and resetting at regular time in a circulation mode.
Description
Technical Field
The invention mainly relates to the technical field of blast furnace feeding systems, in particular to an algorithm of a controllable cyclic on-off program.
Background
In a blast furnace feeding system, when charging, furnace burden falls from a storage bin and enters a weighing hopper through screening of a vibrating screen. When the furnace burden falls on a screen mesh of the vibrating screen, the material blocks larger than the screen mesh slide through the screen mesh and enter a weighing hopper, the material blocks smaller than the screen mesh fall off the screen mesh and are conveyed away by a return belt, and in the process of screening the furnace burden, a large amount of furnace burden powder is accumulated on the screen mesh along with the vibrating screen.
Disclosure of Invention
In view of the shortcomings and drawbacks of the prior art, the present invention provides an algorithm for a controllable cycling on-off program
In order to solve the technical problem, the invention adopts the following technical scheme: an algorithm of a controllable cyclic on-off program, which is characterized in that: the device comprises a setting and resetting control part, a cycle counting part and a cycle control part;
in the cycle control part, a reset priority type trigger and a switch-on delay timer are used for starting and ending an algorithm, when a start button is clicked on a monitoring picture, a 'running instruction' is sent out, a digital quantity 'running activation' is set to be '1' through the reset priority type trigger, the cycle switch-on and switch-off algorithm starts to be executed, the 'running activation' is reset to be 0 after a variable 'running end' state in a program is '1', the algorithm is ended, meanwhile, the variable 'running end' is delayed for 0.5 seconds through the switch-on delay timer, a 'running end delay' signal is sent out, and the purpose of increasing the delay is to eliminate abnormal signal fluctuation;
in the cycle counting part, an up-counter module is used for calculating the cycle times in the program operation, and when the preset cycle times are reached, an end signal is sent out;
IN the setting and resetting control part, the control of the setting and resetting time of the external variable ' operation output ' is realized by a pulse timer and a disconnection delay timer, when the ' operation activation ' state is changed to ' 1 ', a pulse signal ' 1 ' is sent out by a positive delay detection contact, a pulse timer module is activated, the internal timer of the pulse timer module starts to time, and the ' 1 ' is output by a Q output end, after the disconnection delay timer module, the ' operation interruption ' signal state connected with the Q output end is changed to ' 1 ', at the moment, the ' operation output ' is set to ' 1 ', when the internal timer of the pulse timer module reaches the ' operation on time setting ' time, the state of the Q output end of the module is changed to ' 0 ', the ' operation output ' is also reset to ' 0 ', the disconnection delay timer module is activated, the internal timer starts to time, when the internal timer of the disconnection delay timer module reaches the ' operation off time setting ' time ', the ' operation interruption ' reset ' 0 ', and when the negative delay detection variable connected with the input end of the pulse timer module is changed from ' 1 ' to ' 0 ', a pulse signal ' 1 ' is sent out again, and a cycle is started.
As a further improvement of the present invention, in the reset priority flip-flop, if the signal state of the S input terminal is "1" and the signal state of the R1 input terminal is "0", the reset priority flip-flop is set, otherwise, if the signal state of the S input terminal is "0" and the signal state of the R input terminal is "1", the reset priority flip-flop is set, and if the signal states of both the input terminals are "1", the execution order of the instructions is most important, the set reset priority flip-flop executes the set instruction first, then executes the reset instruction, and maintains the reset state during execution of the rest of the program scan.
As a further improvement of the invention, IN the on-delay timer, if there is a rising edge at the on-IN input, the on-delay timer will start an internal timer, the signal change is always a necessary condition for starting the timer, as long as the signal state of the IN input is "1", the timer will run at a time interval set at the PT input, the timer reaches the set time without error, and when the signal state of the IN input is still "1", the signal state of the Q output is "1", and if the signal state of the IN input changes from "1" to "0" during the timer running, the timer will stop, IN which case the signal state of the Q output is "0".
As a further improvement of the invention, an external variable 'cycle time setting' is connected at the PV end of the ascending counter module, parameters can be modified on a monitoring picture at any time, the ascending counter counts once every time the signal state of the variable 'operation output' is changed from '0' to '1', when the accumulated count is equal to the given value of the variable 'cycle time setting', the variable 'operation ending' at the output end of the module is set to '1', and when the variable 'operation activation' or the 'operation ending delay' positive jump is changed to '1', the count of the ascending counter is cleared to prepare for a new round of ascending count.
As a further improvement of the invention, IN the pulse timer, if there is a rising edge at the IN input, the pulse timer will start, the signal change is always a necessary condition for enabling the timer, the timer runs at a time interval set at the PT input, even if the signal state at the IN input becomes "0" before the time interval ends, and the signal state at the Q output is always "1" as long as the timer runs.
As a further improvement of the present invention, IN the off-delay timer, if there is a falling edge at the IN input, the off-delay timer will start the timer, and the signal change is always a necessary condition for enabling the timer, if the signal state of the IN input is "1", or the timer is running, the signal state of the Q output is "1", the timer reaches a preset time value, and the signal state of the IN input is still "0", the signal state of the Q output becomes "0", if the signal state of the IN input is changed from "0" to "1" during the running of the timer, the timer will be reset, and the timer can be restarted after the signal state of the IN input is changed from "1" to "0" again.
Compared with the prior art, the invention has the beneficial effects that: the controllable algorithm of the cyclic on-off program controls the blanking gate of the vibrating screen, so that the gate is automatically closed for a period of time after being opened for a period of time and then opened and closed when the vibrating screen vibrates, and the process is repeated for several times, so that the vibrating screen generates several times of air vibration in the discharging process, furnace charge powder on the vibrating screen is screened off, the powder entering the furnace is reduced, the powder in the furnace charge is reduced, the charge surface cannot be pasted, the gas flow easily and uniformly passes through the furnace bottom, the air permeability is good, and the phenomenon of material suspension caused by the powder is reduced. The utilization rate of coal gas is improved, the preheating of furnace charge is facilitated, the energy consumption is reduced, the reduction degree is increased, and the coke ratio of the blast furnace and the pig iron yield are improved.
Drawings
The invention will be further described with reference to the following drawings and detailed description:
FIG. 1 is a structural form of an algorithm;
FIG. 2 is a flow chart of an algorithm;
FIG. 3 is a program structure of a start and end section;
FIG. 4 is a timing diagram of the turn-on delay timer;
FIG. 5 is a program structure of a loop count section;
FIG. 6 is a program structure of the circulation control section;
FIG. 7 is a timing diagram of a pulse timer;
fig. 8 is a timing diagram of the turn-off delay timer.
Detailed Description
For better understanding of the technical solutions and advantages of the present invention, the following detailed description of the present invention is provided with specific examples, it should be understood that the specific embodiments described herein are only for understanding of the present invention and are not intended to limit the present invention, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts are within the protection scope of the present invention.
The whole algorithm consists of three program segments, namely a setting and resetting control part, a cycle counting part and a cycle control part of the program.
1-Loop Algorithm Start and end
In this section, a [ reset priority type trigger ] and a [ turn-on delay timer ] are used for starting and ending the algorithm, and the program structure is as shown in fig. 3
1.1 Module functional description
[ reset priority type trigger ]
The following steps are described: and if the signal state of the S input end is 1 and the signal state of the R1 input end is 0, setting and resetting the priority type flip-flop. Otherwise, if the signal state of the S input end is '0' and the signal state of the R input end is '1', the reset priority type flip-flop is set and reset. If the signal states at both inputs are "1", the order of execution of the instructions is most important. The set-reset priority flip-flop executes the set instruction first and then the reset instruction and remains reset during execution of the remainder of the program scan.
[ ON-TIME DELAY TIMER ]
The description is as follows: turning on the delay timer starts an internal timer if there is a rising edge at the start IN input. The signal change is always a necessary condition to enable the timer. The timer runs at intervals set at the PT input as long as the signal state at the IN input is "1". The timer reaches a set time without error and the signal state at the IN input remains "1", the signal state at the Q output is "1". If the signal state at the IN input changes from "1" to "0" during the timer running, the timer will stop. In this case, the signal state at the Q output is "0".
Timing diagram: characteristic curve of turn-on delay timer as shown in FIG. 4
When the IN input end is changed to '1', the internal timer (ET) starts to time;
when the time of the timer reaches a preset time value of the PT input end, the Q output end becomes 1;
when the IN input end is changed to be 0, the Q output end is changed to be 0, and meanwhile, the internal timer (ET) stops timing and is reset;
when the timer time does not reach the preset time value of the PT input end, the IN input end is changed into 0, the timer stops timing and resets, and the Q output end is not influenced and is changed into 1.
1.2 Program segment algorithm parsing
When a start button (the button should be in a pulse signal mode) is clicked on a monitoring picture, a 'running instruction' (Run _ order) is sent out, a digital quantity 'running activation' (Run _ act) is set to be '1' through a 'reset priority type trigger', a loop on-off algorithm starts to be executed, and the 'running activation' (Run _ act) is reset to be 0 and the algorithm is ended until the state of a program internal variable 'running end' (Run _ finish) is '1'. And meanwhile, after the variable 'Run end' (Run _ finish) is delayed for 0.5 seconds by a 'turn-on delay timer', a 'Run end delay' (Run _ finish _ delay) signal is sent out, and the purpose of increasing the delay is to eliminate abnormal signal fluctuation.
2. Circulation counting part
The part uses a [ increment counter ] module for calculating the cycle number in the program operation, when the preset cycle number is reached, an end signal is sent out, and the program structure is as shown in figure 5
2.1 Description of Module function
The following steps are described: if the signal state at the CU input end is switched from '0' to '1' and the value of the counter is smaller than '999', the value of the counter is increased by 1; if the state of the R input end is 1, resetting the counter and setting the count value to be zero; if the counting value is larger than or equal to the PV set value of the input end, the signal state of the Q output end is 1.
2.2 Program segment algorithm parsing
The PV end is connected with an external variable 'cycle number setting' (Repeat _ num), parameters can be modified on a monitoring picture at any time, the 'Run _ out' counter counts once when the signal state of the variable 'Run _ out' is changed from '0' to '1', and the 'Run _ finish' variable at the output end of the module is set to '1' when the accumulated count is equal to the 'cycle number setting' (Repeat _ num) variable set value. When the variable "Run active" (Run _ act) or "Run end delay" (Run _ finish _ delay) is changed to "1", the count of the up counter is cleared, and a new round of up count is prepared. The two variables are used as the conditions for resetting the counter (ascending counter) in a parallel mode, the purpose is that every time the algorithm starts to Run, a running activation (Run _ act) variable is used for clearing the counter, after the algorithm is finished, a running finishing delay (Run _ finish _ delay) is used for clearing the counter again, the action is the same, the action which seems to be repeated is also used for eliminating the abnormal state, meanwhile, the two variables use a contact point of positive jump delay detection, because the running activation (Run _ act) variable is executed from the beginning of the algorithm until the algorithm is finished, the signal state is always 1, and if the contact point of positive jump delay detection is not used, the ascending counter is always in the reset state, the counting cannot be carried out.
3. Implementation of on-off control
The part is the key of the whole algorithm, the control of the setting and resetting time of the external variable 'running output' (Run _ out) is realized through a pulse timer module and a break delay timer module, and the program structure is shown in figure 6
3.1 Description of module function
[ pulse timer ]
The description is as follows: if there is a rising edge at the IN input, the pulse timer will start. The signal change is always a necessary condition for enabling the timer. The timer is run at a time interval set at the PT input terminal, even before the time interval is over, the signal state at the IN input terminal becomes "0". As long as the timer runs, the signal state at the Q output is always "1".
Timing diagram: pulse timer characteristic curve as follows FIG. 7
When the IN input end is changed into 1, the Q output end is changed into 1, and the internal timer starts to time;
when the internal timer reaches the preset time value of the PT input, the Q output becomes "0" (not affected by the IN input);
when the internal timer stops timing, if the IN input end is changed into 0, the internal timer is reset;
when the internal timer does not reach the preset time value of the PT input end, the internal timer is not influenced by the change of the IN input end variable;
when the internal timer reaches the preset time value of the PT input terminal, if the IN input terminal becomes "0", the counting is stopped and reset, and the Q output terminal becomes "0".
[ BREAK DELAY TIMER ]
The following steps are described: if there is a falling edge at the IN input, TOF (turn off delay timer) will start the timer. The signal change is always a necessary condition for enabling the timer. If the signal state at the IN input is "1", or the timer is running, the signal state at the Q output is "1". When the timer reaches a preset time value and the signal state of the IN input terminal is still "0", the signal state of the Q output terminal becomes "0". The timer will be reset if the signal state at the IN input changes from "0" to "1" during timer operation. The timer can only be restarted after the signal state at the IN input changes from "1" to "0" again.
Timing diagram: disconnect delay timer characteristic as follows in fig. 8
When the IN input becomes "1", the Q output becomes "1";
when the IN input end is changed to be 0, the internal timer starts to time;
when the internal timer reaches the preset time value of the PT input end, the Q output end becomes 0;
after the internal timer stops timing, if the IN input end is changed into 1, the internal timer is reset, and meanwhile, the Q output end is changed into 1;
when the internal timer does not reach the preset time value of the PT input end, the IN input end is changed into '1', the timer stops timing and resets, and the Q output end is not influenced and is changed into '0'.
[ Positive jump delay detection ] (| P |): the signal change of the variable from '0' to '1' is detected, and when the variable changes from '0' to '1', a pulse signal '1' is sent out.
[ negative jump delay detection ] (| N agent): the signal change of the variable from '1' to '0' is detected, and when the variable changes from '1' to '0', a pulse signal '1' is sent out.
3.2 Program segment algorithm parsing
When the 'Run active' (Run _ act) state is changed to '1', 'positive jump delay detection' contact sends out a pulse signal '1', a 'pulse timer' module is activated, the internal timer starts to time, and the Q output end outputs '1', after the 'break delay timer' module is passed, the 'Run interrupt' (Run _ break) signal state connected with the Q output end is changed to '1', and at the moment, the 'Run output' (Run _ out) is set to '1'.
When an internal timer of a module reaches the time of running on-time setting (Run _ time), the state of an output end of the module Q is changed into 0, running output (Run _ out) is reset into 0, the module is simultaneously activated and the internal timer starts to time, when the internal timer of the module reaches the time of running off-time setting (Run _ break), running interrupt (Run _ break) is reset into 0, and when a contact detection variable of negative jump delay detection connected with an input end of the module IN is changed from 1 to 0, a pulse signal of 1 is sent out, and the cycle is restarted.
Therefore, the setting time of the variable "Run out" (Run _ out) is the preset time of the variable "Run on time setting" (Run _ time), and the resetting time is the preset time of the variable "Run off time setting" (Run _ break). It should be noted here that [ negative jump delay detection ] a normally open contact "Run active" (Run _ act) is required before a contact "Run interrupt" (Run _ break) as a condition, so that after the algorithm loop is finished, "Run active" (Run _ act) resets "0", the bypass program is not executed any more, otherwise, the dead loop is entered and the execution is continued.
It is noted that in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Claims (6)
1. An algorithm of a controllable cyclic on-off program, which is characterized in that: the device comprises a setting and resetting control part, a cycle counting part and a cycle control part;
in the cycle control part, a reset priority type trigger and a switch-on delay timer are used for starting and ending an algorithm, when a start button is clicked on a monitoring picture, a 'running instruction' is sent out, a digital quantity 'running activation' is set to be '1' through the reset priority type trigger, the cycle switch-on and switch-off algorithm starts to be executed, the 'running activation' is reset to be 0 after a variable 'running end' state in a program is '1', the algorithm is ended, meanwhile, the variable 'running end' is delayed for 0.5 seconds through the switch-on delay timer, a 'running end delay' signal is sent out, and the purpose of increasing the delay is to eliminate abnormal signal fluctuation;
in the cycle counting part, an up-counter module is used for calculating the cycle times in the program running process, and when the preset cycle times are reached, an end signal is sent out;
IN the setting and resetting control part, the control of the setting and resetting time of the external variable ' operation output ' is realized by a pulse timer and a disconnection delay timer, when the ' operation activation ' state is changed to ' 1 ', a pulse signal ' 1 ' is sent out by a positive delay detection contact, a pulse timer module is activated, the internal timer of the pulse timer module starts to time, and the ' 1 ' is output by a Q output end, after the disconnection delay timer module, the ' operation interruption ' signal state connected with the Q output end is changed to ' 1 ', at the moment, the ' operation output ' is set to ' 1 ', when the internal timer of the pulse timer module reaches the ' operation on time setting ' time, the state of the Q output end of the module is changed to ' 0 ', the ' operation output ' is also reset to ' 0 ', the disconnection delay timer module is activated, the internal timer starts to time, when the internal timer of the disconnection delay timer module reaches the ' operation off time setting ' time ', the ' operation interruption ' reset ' 0 ', and when the negative delay detection variable connected with the input end of the pulse timer module is changed from ' 1 ' to ' 0 ', a pulse signal ' 1 ' is sent out again, and a cycle is started.
2. The algorithm of claim 1, wherein: in the reset priority type flip-flop, if the signal state of the S input terminal is "1", the signal state of the R1 input terminal is "0", the reset priority type flip-flop is set, otherwise, if the signal state of the S input terminal is "0", the signal state of the R input terminal is "1", the reset priority type flip-flop is set, if the signal states of both the input terminals are "1", the execution sequence of the instructions is most important, the set reset priority type flip-flop executes the set instruction first, then executes the reset instruction, and maintains the reset state during execution of the rest of the program scan.
3. The algorithm of claim 1, wherein: IN the on-delay timer, if there is a rising edge at the start IN input, the on-delay timer will start an internal timer, the signal change is always a necessary condition for starting the timer, as long as the signal state of the IN input is "1", the timer will run at a time interval set at the PT input, the timer reaches a set time without error, and when the signal state of the IN input is still "1", the signal state of the Q output is "1", if the signal state of the IN input changes from "1" to "0" during the timer running, the timer will stop, IN which case the signal state of the Q output is "0".
4. The algorithm for a controlled cycling program according to claim 1, wherein: the PV end of the ascending counter module is connected with an external variable 'cycle time setting', parameters can be modified on a monitoring picture at any time, the ascending counter counts once after the signal state of the variable 'operation output' is changed from '0' to '1', the 'operation ending' variable at the output end of the module is set to '1' when the accumulated count is equal to the 'cycle time setting' variable given value, and the count of the ascending counter is cleared to prepare the new round of ascending count after the variable 'operation activation' or the 'operation ending delay' positive jump is changed to '1'.
5. The algorithm of claim 1, wherein: IN a pulse timer, the pulse timer will start if there is a rising edge at the IN input, the signal change is always a requirement to enable the timer, the timer runs at a time interval set at the PT input, even if the signal state at the IN input becomes "0" before the time interval ends, the signal state at the Q output is always "1" as long as the timer runs.
6. The algorithm of claim 1, wherein: IN the off-delay timer, if there is a falling edge at the IN input terminal, the off-delay timer will start the timer, the signal change is always the necessary condition for starting the timer, if the signal state of the IN input terminal is "1", or the timer is running, the signal state of the Q output terminal is "1", the timer reaches the preset time value, and when the signal state of the IN input terminal is still "0", the signal state of the Q output terminal becomes "0", if the signal state of the IN input terminal is changed from "0" to "1" during the timer running, the timer will be reset, and after the signal state of the IN input terminal is changed from "1" to "0" again, the timer can be restarted.
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| US9287884B2 (en) * | 2013-02-21 | 2016-03-15 | Microchip Technology Incorporated | Enhanced numerical controlled oscillator |
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