CN110299362A - A kind of 3D nand memory and preparation method thereof - Google Patents

A kind of 3D nand memory and preparation method thereof Download PDF

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Publication number
CN110299362A
CN110299362A CN201910640261.2A CN201910640261A CN110299362A CN 110299362 A CN110299362 A CN 110299362A CN 201910640261 A CN201910640261 A CN 201910640261A CN 110299362 A CN110299362 A CN 110299362A
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layer
channel
nand memory
channel hole
preparation
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殷华湘
侯朝昭
李春龙
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Abstract

The present invention provides a kind of 3D nand memory and preparation method thereof, is related to semiconductor memory technologies field, the storage density of 3D nand memory not only can be improved, can also with common process channel layer can be integrated in vertical channel hole.A kind of 3D nand memory, comprising: substrate；The stepped construction being set on the substrate；Along the thickness direction of the substrate, the stepped construction includes alternating and the multiple control gate layer being stacked and multiple interlayer dielectric layers, and each control gate layer is between the two neighboring interlayer dielectric layer；The stepped construction includes through the channel hole of the multiple control gate layer and the multiple interlayer dielectric layer；Channel layer is filled in the channel hole, the material of the channel layer includes polycrystalline Si1‑xGex。

Description

A kind of 3D nand memory and preparation method thereof
Technical field
The present invention relates to semiconductor memory technologies fields more particularly to a kind of 3D nand memory and preparation method thereof.
Background technique
In the past few years, 3D NAND(three-dimensional flash memory memory) as it is a kind of low cost and high-density storage by Concern, is currently mass produced.As 2D NAND(two dimension flash memories below 1X nm node) substitute of flash memory, Several method has been proposed to carry out vertical stacking 3D NAND cell, such as cost extended pattern position (BiCS), too bit stores Lattice array (TCAT) and stacking storage array transistor (SMArT) etc..
Current 3D NAND device mainly uses polysilicon (poly-Si) as channel material.However, polycrystalline silicon channel Lower electron mobility and high trap density can reduce the performance of device, such as lower, the threshold voltage vt h that reads electric current Id Change greatly.Also, read electric current Id reduces with the increase for increasing stack layer, this is for increasing memory heap lamination Number, and it is unfavorable for further increasing storage density.Especially when the stacking number in 3D nand flash memory reaches certain number of plies When (such as 128 layers), the increase of device channel length causes storage unit to read electric current reduction, and which has limited the following 3D NAND Stacking number further increases.
In order to improve the performance of memory, at present frequently with selective epitaxy growth single crystalline Si Ge, single crystalline Si, monocrystalline III- The high electron mobility materials such as V compound mention high read current Id.Meanwhile it can also make the crystal boundary and defect of epitaxial grown material It further decreases.
In order to realize application of the mobility channel in 3D NAND device, need using macaroni relevant to industry Device architecture, structure are as shown on the right.Very thin channel is deposited on gate-dielectric to form macaroni structure, intermediate Gap is filled with dielectric.Control of the grid to channel can be improved using macaroni structure, and by control channel thickness, made It is thinner than depletion widths Wd, to inhibit cut-off current.
However, for current technology, by high electron mobilities such as single crystalline Si Ge, single crystalline Si, monocrystalline III-V compounds The technique that rate material is integrated in multilayer vertical-channel is very difficult.
Summary of the invention
The present invention provides a kind of 3D nand memory and preparation method thereof, and depositing for 3D nand memory not only can be improved Density is stored up, can also with common process mobility channel layer can be integrated in vertical channel hole.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
In a first aspect, providing a kind of 3D nand memory, comprising: substrate；The stepped construction being set on substrate；Along substrate Thickness direction, stepped construction include alternating and the multiple control gate layer being stacked and multiple interlayer dielectric layers, each control Grid layer is between two neighboring interlayer dielectric layer；Stepped construction includes running through multiple control gate layer and multiple inter-level dielectrics The channel hole of layer；Channel layer is filled in channel hole, the material of channel layer includes polycrystalline Si1-xGex.Optionally, 0.1 < x < 0.9, Polycrystalline Si1-xGexCrystal grain diameter range be 3nm ~ 300nm, film thickness 3nm ~ 500nm.
Optionally, side wall stacked structure is also filled in channel hole；A side wall in a channel hole, along channel hole Be directed toward the direction of side wall corresponding thereto, side wall stacked structure include the barrier layer being cascading, electric charge capture layer and Tunnel layer；Barrier layer, electric charge capture layer and tunnel layer are respectively positioned between the side wall and channel layer in channel hole.
Optionally, the material of barrier layer and tunnel layer includes oxide isolated material, and the material of electric charge capture layer includes nitridation Insulating materials.
Optionally, protective layer is also filled in channel hole；Protective layer is located at the side in channel hole of the channel layer where it Wall side.
It optionally, further include the barrier oxide layers for surrounding control gate layer.
Second aspect provides a kind of preparation method of 3D nand memory, comprising: sequentially form on substrate stacking and The multiple interlayer medium films and multiple sacrificial layers being arranged alternately, each interlayer medium film be located at two neighboring sacrificial layer it Between；The channel hole for running through multiple interlayer medium films and multiple sacrificial layers is formed, to obtain interlayer dielectric layer；It is filled out into channel hole Channel layer is filled, the material of channel layer includes polycrystalline Si1-xGex。
Optionally, 0.1 < x < 0.9, polycrystalline Si1-xGexCrystal grain diameter range be 3nm ~ 300nm, film thickness 3nm ~ 500nm。
Optionally, after forming channel hole, before formation channel layer, the preparation method of 3D nand memory further include: The filled sidewall stacked structure in channel hole；In a channel hole, a side wall along channel hole is directed toward side corresponding thereto The direction of wall, side wall stacked structure include the barrier layer being cascading, electric charge capture layer and tunnel layer.
Optionally, the material of barrier layer and tunnel layer includes oxide isolated material, and the material of electric charge capture layer includes nitridation Insulating materials.
Optionally, after forming channel layer, the preparation method of 3D nand memory further include: formed in channel hole Protective layer.
Optionally, after forming channel layer, the preparation method of 3D nand memory further include: removal sacrificial layer, in phase Hollow-out parts are formed between adjacent two interlayer dielectric layers；Barrier oxide layers, control gate layer are sequentially formed in hollow-out parts, are aoxidized Object barrier layer surrounds control gate layer.
The embodiment of the present invention provides a kind of 3D nand memory and preparation method thereof, makees by using polycrystalline Si 1-xGex For the material of channel layer, on the one hand, mobility (usually 50 ~ 450cm of polycrystalline Si 1-xGex raw material2/ Vs) it is greater than it Mobility (usually 30 ~ 150cm of his polysilicon raw materials2/ Vs), compared to other polycrystalline silicon materials, 3D NAND is deposited The influence of the reading electric current Id and threshold voltage vt h of reservoir is smaller, and the storage density of 3D nand memory can be improved；It is another Aspect, polycrystalline Si 1-xGex belong to polycrystalline silicon material, and multilayered structure, phase can be prepared using existing CVD or ALD technique Compared with high electron mobility materials such as the single crystalline Si Ge of selective epitaxy growth, single crystalline Si, monocrystalline III-V compounds, it is easier to ditch Channel layer is integrated in vertical channel hole.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with It obtains other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of 3D nand memory provided by the invention；
Fig. 2 is a kind of structural schematic diagram of 3D nand memory provided by the invention；
Fig. 3 is a kind of schematic top plan view of 3D nand memory provided by the invention；
Fig. 4 is a kind of flow diagram for preparing 3D nand memory provided by the invention；
Fig. 5 is a kind of process schematic for preparing 3D nand memory provided by the invention；
Fig. 6 is a kind of process schematic for preparing 3D nand memory provided by the invention；
Fig. 7 is a kind of process schematic for preparing 3D nand memory provided by the invention；
Fig. 8 is a kind of process schematic for preparing 3D nand memory provided by the invention；
Fig. 9 is a kind of process schematic for preparing 3D nand memory provided by the invention.
Appended drawing reference:
10- substrate；11- interlayer dielectric layer；111- interlayer medium film；12- control gate layer；13- channel layer；14- side wall heap Stack structure；The barrier layer 141-；142- electric charge capture layer；143- tunnel layer；15- barrier oxide layers；17- protective layer；18- sacrifices Layer；101- channel hole；102- wordline hole.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of 3D nand memory, as shown in Figure 1, comprising: substrate 10；It is set to substrate 10 On stepped construction；Along the thickness direction of substrate 10, stepped construction includes the multiple control gate layer 12 alternately and being stacked With multiple interlayer dielectric layers 11, each control gate layer 12 is between two neighboring interlayer dielectric layer 11；Stepped construction includes Through the channel hole of multiple control gate layer 12 and multiple interlayer dielectric layers 11；Channel layer 13, channel layer are filled in channel hole 13 material includes polycrystalline Si1-xGex。
Wherein, 0.1 < x < 0.9, polycrystalline Si1-xGexCrystal grain diameter range be 3nm ~ 300nm, film thickness 3nm ~ 500nm。
In some embodiments, the material of substrate 10 can be semiconductor, for example, the material of substrate 10 is silicon (Si), germanium (Ge) etc..
Certainly, the material of substrate 10 can also be other materials, the embodiment of the present invention to this without limiting, with reality Subject to.
In some embodiments, the material of interlayer dielectric layer 11 is not defined, is with actual process and customer demand It is quasi-.
Exemplary, the material of interlayer dielectric layer 11 is the silica (SiO of low-k k2).
In some embodiments, the material of control gate layer 12 is not defined, control gate layer 12 can should at least expire Foot conduction demand, and can be formed on semiconductor material.
Exemplary, the material of control gate layer 12 is metals such as copper (Cu).
In some embodiments, the number of plies of control gate layer 12 is not defined, is subject to actual demand.
Exemplary, the number of plies of control gate layer 12 can be 32 layers, 64 layers, 128 layers etc..
In some embodiments, each control gate layer 12 is between two neighboring interlayer dielectric layer 11, it may be assumed that stacking knot In structure apart from substrate 10 recently and it is farthest be interlayer dielectric layer 11.
In some embodiments, through the channel hole of multiple control gate layer 12 and multiple interlayer dielectric layers 11, that is, channel All control gate layer 12 and all interlayer dielectric layers 11 are run through in hole.
In some embodiments, the generation type for forming channel layer 13 is not defined, specifically, can be by walking as follows It is rapid to be formed:
S11, as shown in fig. 6, being provided with stacking and the multiple interlayer dielectric layers 11 and multiple sacrificial layers that are arranged alternately on substrate 10 21, multiple interlayer dielectric layers 11 and multiple sacrificial layers 21 include channel hole；Later, it is carried on the back in the sacrificial layer 21 farthest apart from substrate 10 Polycrystalline Si is formed from 10 side of substrate1-xGexFilm.
Wherein it is possible to using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) or atomic layer Deposit process deposits polycrystalline Sis such as (Atomic layer deposition, abbreviation ALD)1-xGexFilm.
S12, in polycrystalline Si1-xGexFilm forms photoetching agent pattern away from 10 side of substrate, and to polycrystalline Si1-xGexFilm It performs etching, to form channel layer 13.
In some embodiments, it as shown in figure 3, not carried out to the arrangement mode in channel hole 101, limits, with actual demand Subject to.Fig. 3 only shows multiple channel holes 101 and is arranged in array.
The embodiment of the present invention provides a kind of 3D nand memory, by using polycrystalline Si1-xGexMaterial as channel layer 13 Material, on the one hand, polycrystalline Si1-xGexMobility (usually 50 ~ 450cm of raw material2/ Vs) it is greater than other polysilicon raw materials Mobility (usually 30 ~ 150cm2/ Vs), compared to other polycrystalline silicon materials, to the reading electric current of 3D nand memory The influence of Id and threshold voltage vt h are smaller, and the storage density of 3D nand memory can be improved；On the other hand, polycrystalline Si1- xGexBelong to polycrystalline silicon material, multilayered structure can be prepared using existing CVD or ALD technique, it is raw compared to selective epitaxy The high electron mobility materials such as long single crystalline Si Ge, single crystalline Si, monocrystalline III-V compound, are easier to for channel layer 13 being integrated in vertical In straight channel hole 101.
It optionally, can be using charge trap type storage organization as storage unit, as shown in Figure 1, in channel hole 101 also Filled with 101 side wall stacked structure 14 of channel hole；In a channel hole 101, a side wall along channel hole 101 is directed toward and it The direction of opposite side wall, 101 side wall stacked structure 14 of channel hole include the barrier layer 141 being cascading, electric charge capture Layer 142 and tunnel layer 143；Barrier layer 141, electric charge capture layer 142 and tunnel layer 143 are respectively positioned on the side in channel hole 101 Between wall and channel layer 13.
Herein, electric charge capture layer 142 is also accumulation layer, for storing charge.
In some embodiments, the material on barrier layer 141 may include oxide isolated material, such as SiO2。
The material of electric charge capture layer 142 may include nitridation insulating materials, such as silicon nitride (Si3N4).
The material of tunnel layer 143 may include oxide isolated material, such as SiO2。
Certainly, side wall stacked structure 14 can also be other structures and material.For example, optional, side wall stacked structure 14 Including barrier layer 141, floating gate layer and the tunnel layer 143 being cascading.Wherein, floating gate layer is polysilicon or metal.
Optionally, as shown in Fig. 2, being also filled with protective layer 17 in channel hole 101；Protective layer 17 is located at channel layer 13 and deviates from The side wall side in the channel hole 101 where it.
In some embodiments, the material of protective layer 17 for example can be inorganic insulation layer, for protecting channel layer 13 not Corroded by steam, oxygen.
In some embodiments, for example, can channel hole 101 using CVD technique to channel layer 13 where it side Wall side deposited oxide material；Later, using photoetching process, oxidation material is performed etching, to form protective layer 17, protective layer 17 are only located in channel hole 101.
Optionally, as Figure 1-Figure 2,3D nand memory further includes the oxide barrier for surrounding control gate layer 12 Layer 15.
In some embodiments, the material of barrier oxide layers 15 for example can be aluminum oxide (Al2O3).
Optionally, as shown in figure 3, stepped construction further includes through multiple interlayer dielectric layers 11 and multiple control gate layer 12 Wordline hole (WL CNT) 102, no overlap between wordline hole 102 and channel hole 101.
In some embodiments, channel hole 101 and the arrangement mode in wordline hole 102 are not defined.
The embodiment of the present invention also provides a kind of preparation method of 3D nand memory, as shown in figure 4, can be by walking as follows It is rapid to realize:
S111, as shown in figure 5, sequentially forming stacking on substrate 10 and multiple interlayer medium films 111 for being arranged alternately and more A sacrificial layer 18, each interlayer medium film 111 is between two neighboring sacrificial layer 12.
In some embodiments, the material of substrate 10 can be semiconductor, for example, the material of substrate 10 is Si, Ge etc..
Certainly, the material of substrate 10 can also be other materials, the embodiment of the present invention to this without limiting, with reality Subject to.
In some embodiments, interlayer medium film 111 is used to form interlayer dielectric layer 11, not to interlayer medium film 111 material is defined, and is subject to actual process and customer demand.
Exemplary, the material of interlayer medium film 111 is the SiO of low-k k2。
In some embodiments, the material of sacrificial layer 18 is not defined, as long as after the material of sacrificial layer 18 does not influence It is continuous to form barrier layer 141, electric charge capture layer 142, tunnel layer 143 and channel layer 13.
Exemplary, the material of sacrificial layer 18 is Si3N4。
In some embodiments, the number of plies of sacrificial layer 18 is the number of plies for the control gate layer 12 being subsequently formed, not to sacrifice The number of plies of layer 18 is defined, and is subject to the number of plies of actually required control gate layer 12 to be formed.
Exemplary, the number of plies of sacrificial layer 18 can be 32 layers, 64 layers, 128 layers etc..
In some embodiments, each sacrificial layer 18 is between two neighboring interlayer medium film 111, it may be assumed that multiple In interlayer medium film 111 and multiple sacrificial layers 18, apart from substrate 10 recently and it is farthest be interlayer medium film 111.
S112, as shown in fig. 6, formed run through multiple interlayer medium films 111 and multiple sacrificial layers 18 channel hole 101, To obtain interlayer dielectric layer 11.
In some embodiments, through the channel hole of multiple sacrificial layers 18 and multiple interlayer medium films 111, that is, channel All sacrificial layers 18 and all interlayer medium films 111 are run through in hole.
In some embodiments, the step of forming channel hole 101 includes: in the interlayer medium film farthest apart from substrate 10 111 form photoetching agent pattern away from 10 side of substrate, and perform etching to all interlayer medium films 111 and sacrificial layer 18, with Form channel hole 101；Finally, stripping photoresist pattern.
In some embodiments, it as shown in figure 3, not carried out to the arrangement mode in channel hole 101, limits, with actual demand Subject to.Fig. 3 only shows multiple channel holes 101 and is arranged in array.
S113, as shown in figure 8, into channel hole 101 fill channel layer 13, the material of channel layer 13 includes polycrystalline Si1- xGex。
Wherein, 0.1 < x < 0.9, polycrystalline Si1-xGexCrystal grain diameter range be 3nm ~ 300nm.
In some embodiments, the step of forming channel layer 13 includes: to deviate from the sacrificial layer 18 farthest apart from substrate 10 10 side of substrate forms polycrystalline Si1-xGexFilm, and in polycrystalline Si1-xGexFilm forms photoetching agent pattern away from 10 side of substrate； Later, to polycrystalline Si1-xGexFilm performs etching, to obtain channel layer 13.
Herein, polycrystalline Si can be formed using process deposits such as CVD or ALD1-xGexFilm.
The embodiment of the present invention provides a kind of preparation method of 3D nand memory, by using polycrystalline Si1-xGexAs ditch The material of channel layer 13, on the one hand, polycrystalline Si1-xGexMobility (usually 50 ~ 450cm of raw material2/ Vs) it is more greater than other Mobility (usually 30 ~ 150cm of crystal silicon raw material2/ Vs), compared to other polycrystalline silicon materials, to 3D nand memory Reading electric current Id and threshold voltage vt h influence it is smaller, the storage density of 3D nand memory can be improved；Another party Face, polycrystalline Si1-xGexBelong to polycrystalline silicon material, multilayered structure can be prepared using existing CVD or ALD technique, compared In high electron mobility materials such as the single crystalline Si Ge of selective epitaxy growth, single crystalline Si, monocrystalline III-V compounds, it is easier to channel Layer 13 is integrated in vertical channel hole 101.
It optionally, as shown in fig. 7, can be using charge trap type storage organization as storage unit.Forming channel hole After 101, formed before channel layer 13, the preparation method of 3D nand memory further include: the filled sidewall in channel hole 101 Stacked structure 14；In a channel hole, the direction of side wall corresponding thereto, side wall are directed toward along a side wall in channel hole 101 Stacked structure 14 includes barrier layer 141, electric charge capture layer 142 and the tunnel layer 143 being cascading.
Herein, electric charge capture layer 142 is also accumulation layer, for storing charge.
In some embodiments, the material on barrier layer 141 may include oxide isolated material, such as SiO2。
The material of electric charge capture layer 142 may include nitridation insulating materials, such as silicon nitride (Si3N4).
The material of tunnel layer 143 may include oxide isolated material, such as SiO2。
Certainly, side wall stacked structure 14 can also be other structures and material.For example, optional, side wall stacked structure 14 Including barrier layer 141, floating gate layer and the tunnel layer 143 being cascading.Wherein, floating gate layer is polysilicon or metal.
It in some embodiments, include: first in channel hole the step of filled sidewall stacked structure 14 in channel hole 101 Barrier layer 141 is filled in 101；And then electric charge capture layer 142 is filled in channel hole 101；Finally, being filled out in channel hole 101 Fill tunnel layer 143.
Optionally, as shown in figure 9, after forming channel layer 13, the preparation method of 3D nand memory further include: Protective layer 17 is formed in channel hole 101.
In some embodiments, the material of protective layer 17 for example can be inorganic insulation layer, for protecting channel layer 13 not Corroded by steam, oxygen.
In some embodiments, for example, can channel hole 101 using CVD technique to channel layer 13 where it side Wall side deposited oxide material；Later, using photoetching process, oxidation material is performed etching, to form protective layer 17, protective layer 17 are only located in channel hole 101.
Optionally, after forming channel layer, the preparation method of 3D nand memory further include:
S114, removal sacrificial layer 18, form hollow-out parts between two neighboring interlayer dielectric layer 11.
In some embodiments, such as sacrificial layer 18 can be removed using photoetching process.
S115, as depicted in figs. 1 and 2, barrier oxide layers 15, control gate layer 12, oxygen are sequentially formed in hollow-out parts Compound barrier layer 15 surrounds control gate layer 12.
In some embodiments, in the case where 3D nand memory includes protective layer 17, formed protective layer 17 the step of After step sl 13 with step S114 and step S115.
So, it can be initially formed protective layer 17, then carry out step S114 and step S115；Alternatively, first carrying out step S114 and step S115, re-forms protective layer 17.
Herein, it is contemplated that during preparing 3D nand memory, if not protected to channel layer 13, steam It will be entered in channel layer 13 with oxygen.Therefore, the embodiment of the present invention is preferably initially formed protective layer 17, then carries out step S114 With step S115.
In some embodiments, the material of barrier oxide layers 15 for example can be Al2O3。
In some embodiments, the material of control gate layer 12 is not defined, control gate layer 12 can should at least expire Foot conduction demand, and can be formed on semiconductor material.
Exemplary, the material of control gate layer 12 is the metals such as Cu.
More than, only a specific embodiment of the invention, but scope of protection of the present invention is not limited thereto, and it is any to be familiar with Those skilled in the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all cover Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.

Claims (12)

1. a kind of 3D nand memory characterized by comprising
Substrate；
The stepped construction being set on the substrate；Along the thickness direction of the substrate, the stepped construction includes alternating and layer The multiple control gate layer and multiple interlayer dielectric layers, each control gate layer of folded setting are located at the two neighboring interlayer Between dielectric layer；The stepped construction includes the channel through the multiple control gate layer and the multiple interlayer dielectric layer Hole；
Channel layer is filled in the channel hole, the material of the channel layer includes polycrystalline Si1-xGex。
2. 3D nand memory according to claim 1, which is characterized in that 0.1 < x < 0.9, polycrystalline Si1-xGexCrystal grain Diameter range is 3nm ~ 300nm, film thickness 3nm ~ 500nm.
3. 3D nand memory according to claim 1 or 2, which is characterized in that be also filled with side wall in the channel hole Stacked structure；
In a channel hole, the direction of side wall corresponding thereto, the side wall heap are directed toward along a side wall in the channel hole Stack structure includes the barrier layer being cascading, electric charge capture layer and tunnel layer；
The barrier layer, the electric charge capture layer and the tunnel layer are respectively positioned on the side wall and the channel in the channel hole Between layer.
4. 3D nand memory according to claim 3, which is characterized in that the material on the barrier layer and the tunnel layer Material includes oxide isolated material, and the material of the electric charge capture layer includes nitridation insulating materials.
5. 3D nand memory according to claim 1 or 2, which is characterized in that be also filled with protection in the channel hole Layer；
The protective layer is located at the side wall side in the channel hole of the channel layer where it.
6. 3D nand memory according to claim 1 or 2, which is characterized in that further include surrounding the control gate layer Barrier oxide layers.
7. a kind of preparation method of 3D nand memory characterized by comprising
The multiple interlayer medium films and multiple sacrificial layers for sequentially forming stacking on substrate and being arranged alternately, each interlayer Dielectric film is between the two neighboring sacrificial layer；
The channel hole for running through the multiple interlayer medium film and the multiple sacrificial layer is formed, to obtain interlayer dielectric layer；
Channel layer is filled into the channel hole, the material of the channel layer includes polycrystalline Si1-xGex。
8. the preparation method of 3D nand memory according to claim 7, which is characterized in that 0.1 < x < 0.9, polycrystalline Si1-xGexCrystal grain diameter range be 3nm ~ 300nm, film thickness 3nm ~ 500nm.
9. the preparation method of 3D nand memory according to claim 7 or 8, which is characterized in that forming the channel After hole, formed before the channel layer, the preparation method of the 3D nand memory further include:
The filled sidewall stacked structure in the channel hole；In a channel hole, a side wall along the channel hole is directed toward The direction of side wall corresponding thereto, the side wall stacked structure include the barrier layer being cascading, electric charge capture layer and Tunnel layer.
10. the preparation method of 3D nand memory according to claim 9, which is characterized in that the barrier layer and described The material of tunnel layer includes oxide isolated material, and the material of the electric charge capture layer includes nitridation insulating materials.
11. the preparation method of 3D nand memory according to claim 7 or 8, which is characterized in that forming the ditch After channel layer, the preparation method of the 3D nand memory further include:
Protective layer is formed in the channel hole.
12. the preparation method of 3D nand memory according to claim 7 or 8, which is characterized in that forming the ditch After channel layer, the preparation method of the 3D nand memory further include:
The sacrificial layer is removed, forms hollow-out parts between the two neighboring interlayer dielectric layer；
Barrier oxide layers, control gate layer are sequentially formed in the hollow-out parts, the barrier oxide layers surround the control Grid layer processed.
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CN113097216A (en) * 2020-01-16 2021-07-09 长江存储科技有限责任公司 Three-dimensional memory and preparation method thereof

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