CN110299298A - Wafer defect scan method and system, fault detection board - Google Patents
Wafer defect scan method and system, fault detection board Download PDFInfo
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- CN110299298A CN110299298A CN201910555991.2A CN201910555991A CN110299298A CN 110299298 A CN110299298 A CN 110299298A CN 201910555991 A CN201910555991 A CN 201910555991A CN 110299298 A CN110299298 A CN 110299298A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The present invention provides a kind of wafer defect scan method and system, fault detection board, wafer defect scan method includes: that each area to be tested on a wafer is divided into compact district and non-dense set area；The compact district and the non-dense set area to each area to be tested carry out Defect Scanning respectively with the first pixel unit and the second pixel unit；Wherein, the pixel of first pixel unit is less than the pixel of second pixel unit.The scanning speed and output of fault detection board can be improved using scheme provided by the invention.
Description
Technical field
The present invention relates to semiconductor defect detection technique field more particularly to a kind of wafer defect scan method and system,
Fault detection board, computer readable storage medium.
Background technique
In the stage of current semiconductor rapid development, the competitiveness of the manufacturing works Fab of a semiconductor production is depended on
Two conditions of product yield and production cycle.While promoting yield, the output for promoting the board of Fab is also always a heat
Door topic.The board output promotion of Fab can reduce board quantity required, shorten the term of delivery to reduce production cost.?
In Fab production procedure, fault detection is essential a part, so, the output for promoting fault detection board equally can be with
Reduce the Fab production cycle.
For light field fault detection board during carrying out wafer defect scanning, the same inspection formula is with the same picture
Plain unit (pixel size) does fault detection, and pixel unit is the minimum verification unit that Examination region is divided into, pixel
Unit is smaller, and testing accuracy is higher.In order to guarantee the recall rate of the defect on wafer, often an inspection formula be all take compared with
Small pixel size improves the sensitivity of inspection.But fault detection board will affect using lesser pixel size
Scanning speed reduces the output of board.
Summary of the invention
The purpose of the present invention is to provide a kind of wafer defect scan methods and system, fault detection board, computer can
Storage medium is read, to improve the scanning speed and output of fault detection board.Specific technical solution is as follows:
In a first aspect, the present invention provides a kind of wafer defect scan methods, comprising:
Each area to be tested on one wafer is divided into compact district and non-dense set area；
The compact district and the non-dense set area to each area to be tested are respectively with the first pixel unit and
Two pixel units carry out Defect Scanning；
Wherein, the pixel of first pixel unit is less than the pixel of second pixel unit.
Optionally, each area to be tested is identical.
Optionally, each area to be tested is divided into compact district and non-dense set area, comprising:
According to the key message of device on the wafer, each area to be tested is divided into compact district and non-dense set area.
Optionally, each area to be tested is divided into compact district and non-dense set area, comprising:
Prescan is carried out to the wafer, obtains the grey value profile of area to be tested described in the wafer；
According to the grey value profile, each area to be tested is divided into compact district and non-dense set area.
Optionally, it is described to the compact district of each area to be tested and the non-dense set area respectively with described
One pixel unit and second pixel unit carry out Defect Scanning, comprising:
The verification unit that the compact district is arranged in Defect Scanning formula is first pixel unit, is arranged described non-
The verification unit of close quarters is second pixel unit；
Defect is carried out to the area to be tested each on the wafer according to the Defect Scanning formula after setting to sweep
It retouches.
Optionally, the Defect Scanning formula according to after setting is to each area to be detected on the wafer
Domain carries out Defect Scanning, comprising:
During Defect Scanning, the incident light aperture and/or emergent light aperture of defect checking machine platform are automatically adjusted, so that
The pixel of current trial unit reaches the pixel of first pixel unit, so that the defect checking machine platform is with first picture
Plain unit carries out Defect Scanning to the compact district of each area to be tested；And
The incident light aperture and/or emergent light aperture for automatically adjusting defect checking machine platform, so that the picture of current trial unit
Element reaches the pixel of second pixel unit, so that the defect checking machine platform is with second pixel unit to each to be checked
The non-dense set area for surveying region carries out Defect Scanning.
Optionally, the magnitude range of first pixel unit is 0.065um~0.09um.
Optionally, the magnitude range of second pixel unit is 0.12um~0.2um.
Second aspect, the present invention also provides a kind of wafer defect scanning systems, comprising:
Region division module, for each area to be tested on a wafer to be divided into compact district and non-dense set area；
Defect Scanning module, for each area to be tested the compact district and the non-dense set area respectively with
First pixel unit and the second pixel unit carry out Defect Scanning；Wherein, the pixel of first pixel unit is less than described the
The pixel of two pixel units.
Optionally, each area to be tested is identical.
Optionally, each area to be tested is divided into the method packet in compact district and non-dense set area by the region division module
It includes:
According to the key message of device on the wafer, each area to be tested is divided into compact district and non-dense set area.
Optionally, each area to be tested is divided into the method packet in compact district and non-dense set area by the region division module
It includes:
Prescan is carried out to the wafer, obtains the grey value profile of area to be tested described in the wafer；
According to the grey value profile, each area to be tested is divided into compact district and non-dense set area.
Optionally, the Defect Scanning module, comprising:
Setting unit, the verification unit for the compact district to be arranged in Defect Scanning formula are the first pixel list
Member, the verification unit that the non-dense region is arranged is second pixel unit；
Scanning element, for according to the Defect Scanning formula after setting to the area to be detected each on the wafer
Domain carries out Defect Scanning.
Optionally, the scanning element is according to the Defect Scanning formula after setting to each described on the wafer
Area to be tested carry out Defect Scanning method include:
During Defect Scanning, the incident light aperture and/or emergent light aperture of defect checking machine platform are automatically adjusted, so that
The pixel of current trial unit reaches the pixel of first pixel unit, so that the defect checking machine platform is with first picture
Plain unit carries out Defect Scanning to the compact district of each area to be tested；And
The incident light aperture and/or emergent light aperture for automatically adjusting defect checking machine platform, so that the picture of current trial unit
Element reaches the pixel of second pixel unit, so that the defect checking machine platform is with second pixel unit to each to be checked
The non-dense set area for surveying region carries out Defect Scanning.
Optionally, the magnitude range of first pixel unit is 0.065um~0.09um.
Optionally, the magnitude range of second pixel unit is 0.12um~0.2um.
The third aspect, the present invention also provides a kind of fault detection board, including processor, communication interface, memory and
Communication bus, wherein the processor, the communication interface, the memory are completed each other by the communication bus
Communication；
The memory, for storing computer program；
The processor when for executing the program stored on the memory, is realized described in above-mentioned first aspect
The step of wafer defect scan method.
Fourth aspect, the present invention also provides a kind of computer readable storage medium, the computer readable storage medium
It is inside stored with computer program, the computer program realizes wafer defect described in above-mentioned first aspect when being executed by processor
The step of scan method.
Compared with prior art, technical solution of the present invention has the advantages that
Area to be tested on wafer is divided into compact district and non-dense set area, to compact district and non-dense set area respectively with
One pixel unit and the second pixel unit carry out Defect Scanning, the picture of the pixel of the first pixel unit less than the second pixel unit
Element, as a result, by compact district with biggish verification unit carry out Defect Scanning, to non-dense set area with lesser verification unit into
Row Defect Scanning, can guarantee compact district defect detection rate in the case where, improve fault detection board scanning speed and
Output, and then reduce the production cycle of Fab.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the flow diagram for the wafer defect scan method that one embodiment of the invention provides；
Fig. 2 is the schematic diagram for the GDS file that one embodiment of the invention provides；
Fig. 3 is the corresponding scan image in partial region in the region to be tested that one embodiment of the invention provides；
Fig. 4 is index path of the fault detection board of one embodiment of the invention offer when carrying out Defect Scanning；
Fig. 5 is the structural schematic diagram for the wafer defect scanning system that one embodiment of the invention provides；
Fig. 6 is the structural schematic diagram for the fault detection board that one embodiment of the invention provides.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of wafer defect scan method proposed by the present invention and system, defect
Board and computer readable storage medium is examined to be described in further detail.According to claims and following explanation, the present invention
The advantages of and feature will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-accurate ratio,
Only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
To solve problem of the prior art, the embodiment of the invention provides a kind of wafer defect scan method and system, lack
It falls into and examines board and computer readable storage medium.
Fig. 1 is a kind of flow diagram for wafer defect scan method that one embodiment of the invention provides.Referring to FIG. 1,
A kind of wafer defect scan method may include steps of:
Each area to be tested on one wafer is divided into compact district and non-dense set area by step S101.
In the present embodiment, the wafer includes multiple area to be tested, and multiple area to be tested on wafer are identical.
In subsequent encapsulation process, each area to be tested on wafer will be cut into small chip by scribing process
(die)。
It will be appreciated by persons skilled in the art that compact district refers to that the region of figure comparatively dense inside crystal grain (is such as patrolled
Collect area, memory block, pixel region etc.), non-dense set area refers to that figure is compared with the region of dispersion inside crystal grain.
In one implementation, include: by the method that each area to be tested is divided into compact district and non-dense set area
According to the key message of device on the wafer, each area to be tested is divided into compact district and non-dense set area.
It is understood that the key message of device may include: size, distribution and line width of device etc. on the wafer
Information, these key messages can pass through the corresponding GDS of the wafer (Graphic Design System, graphic designs system
System) file acquisition.The key message of device can be directly in each area to be tested on the wafer according to GDS file
Distinguish compact district and non-dense set area.GDS file as shown in Figure 2, each area to be tested in the GDS file, on wafer
In be labeled with Dense (intensive) region, Parallel line (parallel line shaped figure) region, the area SRAM (static storage) II,
Therefore Dummy (filling figure) region, the area SARAM I (static storage) I directly can will according to the mark of the GDS file
The region Dense, the area SRAM II, SARAM I area definition are compact district, and the region Parallel line, the region Dummy are defined as
Non-dense set area.
In another implementation, include: by the method that each area to be tested is divided into compact district and non-dense set area
Prescan is carried out to the wafer, obtains the grey value profile of area to be tested described in the wafer；
According to the grey value profile, each area to be tested is divided into compact district and non-dense set area.
Prescan is carried out to the wafer specifically, can use fault detection board, the scan image obtained to scanning
Gray analysis is carried out, the grey value profile of area to be tested described in the wafer is obtained.It is understood that area to be tested
Compact district and the grey value profile in non-dense set area be different, compact district is risen and fallen due to figure comparatively dense and in height, is caused
The reflection signal of light is weaker, so the brightness in this region is darker in scan image, rather than compact district is since figure is sparse and table
Face is flat, causes the reflection signal of light stronger, so the brightness in this region is brighter in scan image, therefore passes through grey value profile
The compact district and non-dense set area of area to be tested can be distinguished.
Fig. 3 illustratively shows the corresponding scan image in partial region in a region to be tested, as shown in figure 3, area
The brightness in domain 101 and region 102 is darker, therefore region 101 and region 102 belong to compact district, and the brightness in region 102 is brighter, because
This region 103 belongs to non-dense set area.It should be noted that Fig. 3 does not mark out all compact district and non-dense set area completely, only
Region 101,102,103 is marked out as example to be illustrated to compact district and non-dense set area.
Step S102, the compact district and the non-dense set area to each area to be tested are respectively with the first pixel
Unit and the second pixel unit carry out Defect Scanning.
Wherein, the pixel of first pixel unit is less than the pixel of second pixel unit.
In practical applications, the verification unit that the compact district can be arranged in Defect Scanning formula is first picture
Plain unit, the verification unit that the non-dense region is arranged is second pixel unit, then, according to described scarce after setting
It falls into scanning formula and Defect Scanning is carried out to the area to be tested each on the wafer.
Since each area to be tested has been divided into compact district and non-dense set area in step S101, wafer is carried out
Defect Scanning, that is, Defect Scanning is carried out to each compact district and non-dense set area.During the scanning process, when scanning is to each close
It is scanned when collecting area with the first pixel unit for minimum verification unit, when each non-dense set area is arrived in scanning with the second pixel list
Member is scanned for minimum verification unit.Pixel of the pixel of first pixel unit less than the second pixel unit, that is to say, that right
Compact district carries out Defect Scanning with lesser verification unit, carries out Defect Scanning to non-dense set area with biggish verification unit.By
Imperfection sensitivity in compact district is stronger, can guarantee the defect detection rate of compact district using lesser verification unit.To non-close
Although Ji Qu reduces defect detection rate using biggish verification unit to a certain extent, since the defect in non-dense set area is quick
Perception is lower, and reducing defect detection rate will not influence the function in non-dense set area, while the defect that can promote non-dense set area is swept
Speed is retouched, and then promotes the bulk velocity of whole wafer Defect Scanning, improves the output of fault detection board.
Specifically, according to the Defect Scanning formula after setting to each area to be tested on the wafer into
The method of row Defect Scanning includes:
During Defect Scanning, the incident light aperture and/or emergent light aperture of defect checking machine platform are automatically adjusted, so that
The pixel of current trial unit reaches the pixel of first pixel unit, so that the defect checking machine platform is with first picture
Plain unit carries out Defect Scanning to the compact district of each area to be tested；And
The incident light aperture and/or emergent light aperture for automatically adjusting defect checking machine platform, so that the picture of current trial unit
Element reaches the pixel of second pixel unit, so that the defect checking machine platform is with second pixel unit to each to be checked
The non-dense set area for surveying region carries out Defect Scanning.
Minimum defect size decision of the size of first pixel unit based on the required scanning in compact district, the second pixel unit
Size based on the required scanning in non-dense set area minimum defect size determine.In the present embodiment, the size of the first pixel unit
It may range from 0.065um~0.09um, the magnitude range of the second pixel unit can be 0.12um~0.2um.
Fig. 4 illustratively shows index path of the fault detection board when carrying out Defect Scanning, as shown in Figure 4, defect
The size of verification unit when scanning can be by incident light aperture and/or emergent light pore size control, by changing incident light aperture
And/or emergent light aperture, the size of available required verification unit.When to scan a certain compact district, automatic adjustment
Incident light aperture and/or emergent light aperture can make the pixel of current trial unit switch to the corresponding picture of the first pixel unit
Element, and incident light aperture and emergent light aperture after adjusting are kept, so that defect checking machine platform is close to this with the first pixel unit
Ji Qu carries out Defect Scanning.When will from the scan conversion of the compact district to when being scanned to an adjacent non-dense set area, then
Secondary adjusting incident light aperture and/or emergent light aperture make the pixel of current trial unit by the corresponding pixel of the first pixel unit
It is switched to the corresponding pixel of the second pixel unit, and keeps incident light aperture and emergent light aperture after adjusting, so that defect is examined
It surveys board and Defect Scanning is carried out to the non-dense set area with the second pixel unit.
In conclusion the area to be tested on wafer is divided into compact district and non-dense set area by the present embodiment, to compact district
Defect Scanning is carried out with the first pixel unit and the second pixel unit respectively with non-dense set area, the pixel of the first pixel unit is less than
The pixel of second pixel unit, as a result, by compact district with biggish verification unit carry out Defect Scanning, to non-dense set area with
Lesser verification unit carries out Defect Scanning, can improve fault detection in the case where guaranteeing the defect detection rate of compact district
The scanning speed and output of board, and then reduce the production cycle of Fab.
Corresponding to above method embodiment, one embodiment of the invention additionally provides a kind of wafer defect scanning system.It please join
Fig. 5 is examined, Fig. 5 is a kind of structural schematic diagram for wafer defect scanning system that one embodiment of the invention provides, a kind of wafer defect
Scanning system may include:
Region division module 201, for each area to be tested on a wafer to be divided into compact district and non-dense set area；
Defect Scanning module 202, for each area to be tested the compact district and the non-dense set distinguish
Defect Scanning is not carried out with the first pixel unit and the second pixel unit；Wherein, the pixel of first pixel unit is less than institute
State the pixel of the second pixel unit.
Optionally, each area to be tested is identical.
Optionally, each area to be tested is divided into the side of compact district and non-dense set area by the region division module 201
Method includes:
According to the key message of device on the wafer, each area to be tested is divided into compact district and non-dense set area.
Optionally, each area to be tested is divided into the side of compact district and non-dense set area by the region division module 201
Method includes:
Prescan is carried out to the wafer, obtains the grey value profile of area to be tested described in the wafer；
According to the grey value profile, each area to be tested is divided into compact district and non-dense set area.
Optionally, the Defect Scanning module 202, comprising:
Setting unit, the verification unit for the compact district to be arranged in Defect Scanning formula are the first pixel list
Member, the verification unit that the non-dense region is arranged is second pixel unit；
Scanning element, for according to the Defect Scanning formula after setting to the area to be detected each on the wafer
Domain carries out Defect Scanning.
Optionally, the scanning element is according to the Defect Scanning formula after setting to each described on the wafer
Area to be tested carry out Defect Scanning method include:
During Defect Scanning, the incident light aperture and/or emergent light aperture of defect checking machine platform are automatically adjusted, so that
The pixel of current trial unit reaches the pixel of first pixel unit, so that the defect checking machine platform is with first picture
Plain unit carries out Defect Scanning to the compact district of each area to be tested；And
The incident light aperture and/or emergent light aperture for automatically adjusting defect checking machine platform, so that the picture of current trial unit
Element reaches the pixel of second pixel unit, so that the defect checking machine platform is with second pixel unit to each to be checked
The non-dense set area for surveying region carries out Defect Scanning.
Optionally, the magnitude range of first pixel unit is 0.065um~0.09um.
Optionally, the magnitude range of second pixel unit is 0.12um~0.2um.
Area to be tested on wafer is divided into compact district and non-dense set area by the present embodiment, to compact district and non-dense set area
Defect Scanning is carried out with the first pixel unit and the second pixel unit respectively, the pixel of the first pixel unit is less than the second pixel list
The pixel of member, as a result, by carrying out Defect Scanning to compact district with biggish verification unit, to non-dense set area with lesser inspection
Unit carries out Defect Scanning, can improve the scanning of fault detection board in the case where guaranteeing the defect detection rate of compact district
Speed and output, and then reduce the production cycle of Fab.
One embodiment of the invention additionally provides a kind of fault detection board, and Fig. 6 is one kind that one embodiment of the invention provides
The structural schematic diagram of fault detection board.Referring to FIG. 6, a kind of fault detection board include processor 301, communication interface 302,
Memory 303 and communication bus 304, wherein processor 301, communication interface 302, memory 303 are complete by communication bus 304
At mutual communication,
Memory 303, for storing computer program；
Processor 301 when for executing the program stored on memory 303, realizes following steps:
Each area to be tested on one wafer is divided into compact district and non-dense set area；
The compact district and the non-dense set area to each area to be tested are respectively with the first pixel unit and
Two pixel units carry out Defect Scanning；
Wherein, the pixel of first pixel unit is less than the pixel of second pixel unit.
Specific implementation and relevant explanation content about each step of this method may refer to above-mentioned method shown in FIG. 1
Embodiment, this will not be repeated here.
In addition, processor 301 execute the program stored on memory 303 and the wafer defect scan method realized its
His implementation, it is identical as implementation mentioned by preceding method embodiment part, it also repeats no more here.
Area to be tested on wafer is divided into compact district and non-dense set area by the present embodiment, to compact district and non-dense set area
Defect Scanning is carried out with the first pixel unit and the second pixel unit respectively, the pixel of the first pixel unit is less than the second pixel list
The pixel of member, as a result, by carrying out Defect Scanning to compact district with biggish verification unit, to non-dense set area with lesser inspection
Unit carries out Defect Scanning, can improve the scanning of fault detection board in the case where guaranteeing the defect detection rate of compact district
Speed and output, and then reduce the production cycle of Fab.
The communication bus that drawbacks described above examines board to mention can be Peripheral Component Interconnect standard (Peripheral
Component Interconnect, PCI) bus or expanding the industrial standard structure (Extended Industry Standard
Architecture, EISA) bus etc..The communication bus can be divided into address bus, data/address bus, control bus etc..For just
It is only indicated with a thick line in expression, figure, it is not intended that an only bus or a type of bus.
Communication interface examines the communication between board and other equipment for drawbacks described above.
Memory may include random access memory (Random Access Memory, RAM), also may include non-easy
The property lost memory (Non-Volatile Memory, NVM), for example, at least a magnetic disk storage.Optionally, memory may be used also
To be storage device that at least one is located remotely from aforementioned processor.
Above-mentioned processor can be general processor, including central processing unit (Central Processing Unit,
CPU), network processing unit (Network Processor, NP) etc.；It can also be digital signal processor (Digital Signal
Processing, DSP), it is specific integrated circuit (Application Specific Integrated Circuit, ASIC), existing
It is field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete
Door or transistor logic, discrete hardware components.
One embodiment of the invention additionally provides a kind of computer readable storage medium, the computer readable storage medium memory
Computer program is contained, which realizes above-mentioned wafer defect scan method when being executed by processor the step of.
Area to be tested on wafer is divided into compact district and non-dense set area by the present embodiment, to compact district and non-dense set area
Defect Scanning is carried out with the first pixel unit and the second pixel unit respectively, the pixel of the first pixel unit is less than the second pixel list
The pixel of member, as a result, by carrying out Defect Scanning to compact district with biggish verification unit, to non-dense set area with lesser inspection
Unit carries out Defect Scanning, can improve the scanning of fault detection board in the case where guaranteeing the defect detection rate of compact district
Speed and output, and then reduce the production cycle of Fab.
Described it should be noted that each embodiment in this specification is all made of relevant mode, each embodiment it
Between same and similar part may refer to each other, each embodiment focuses on the differences from other embodiments.
For system, fault detection board, computer readable storage medium embodiment, since it is substantially similar to method
Embodiment, so being described relatively simple, the relevent part can refer to the partial explaination of embodiments of method.
Herein, relational terms such as first and second and the like be used merely to by an entity or operation with it is another
One entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this reality
Relationship or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to the packet of nonexcludability
Contain, so that the process, method, article or equipment for including a series of elements not only includes those elements, but also including
Other elements that are not explicitly listed, or further include for elements inherent to such a process, method, article, or device.
In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element
Process, method, article or equipment in there is also other identical elements.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (16)
1. a kind of wafer defect scan method characterized by comprising
Each area to be tested on one wafer is divided into compact district and non-dense set area；
The compact district and the non-dense set area to each area to be tested is respectively with the first pixel unit and the second picture
Plain unit carries out Defect Scanning；
Wherein, the pixel of first pixel unit is less than the pixel of second pixel unit.
2. wafer defect scan method as described in claim 1, which is characterized in that each area to be tested is identical.
3. wafer defect scan method as claimed in claim 2, which is characterized in that each area to be tested to be divided into intensively
Area and non-dense set area, comprising:
According to the key message of device on the wafer, each area to be tested is divided into compact district and non-dense set area.
4. wafer defect scan method as claimed in claim 2, which is characterized in that each area to be tested to be divided into intensively
Area and non-dense set area, comprising:
Prescan is carried out to the wafer, obtains the grey value profile of area to be tested described in the wafer；
According to the grey value profile, each area to be tested is divided into compact district and non-dense set area.
5. wafer defect scan method as described in claim 1, which is characterized in that described to each area to be tested
The compact district and the non-dense set area carry out Defect Scanning respectively with first pixel unit and second pixel unit,
Include:
The verification unit that the compact district is arranged in Defect Scanning formula is first pixel unit, and the non-dense set is arranged
The verification unit in region is second pixel unit；
Defect Scanning is carried out to the area to be tested each on the wafer according to the Defect Scanning formula after setting.
6. wafer defect scan method as claimed in claim 5, which is characterized in that the defect according to after setting is swept
It retouches formula and Defect Scanning is carried out to each area to be tested on the wafer, comprising:
During Defect Scanning, the incident light aperture and/or emergent light aperture of defect checking machine platform are automatically adjusted, so that currently
The pixel of verification unit reaches the pixel of first pixel unit, so that the defect checking machine platform is with the first pixel list
Member carries out Defect Scanning to the compact district of each area to be tested；And
The incident light aperture and/or emergent light aperture for automatically adjusting defect checking machine platform, so that the pixel of current trial unit reaches
To the pixel of second pixel unit, so that the defect checking machine platform is with second pixel unit to each area to be detected
The non-dense set area in domain carries out Defect Scanning.
7. wafer defect scan method as claimed in any one of claims 1 to 6, which is characterized in that first pixel unit
Magnitude range is 0.065um~0.09um.
8. wafer defect scan method as claimed in any one of claims 1 to 6, which is characterized in that second pixel unit
Magnitude range is 0.12um~0.2um.
9. a kind of wafer defect scanning system characterized by comprising
Region division module, for each area to be tested on a wafer to be divided into compact district and non-dense set area；
Defect Scanning module, for each area to be tested the compact district and the non-dense set area respectively with first
Pixel unit and the second pixel unit carry out Defect Scanning；Wherein, the pixel of first pixel unit is less than second picture
The pixel of plain unit.
10. wafer defect scanning system as claimed in claim 9, which is characterized in that each area to be tested is identical.
11. wafer defect scanning system as claimed in claim 10, which is characterized in that the region division module by it is each to
Detection zone is divided into compact district and the method in non-dense set area includes:
According to the key message of device on the wafer, each area to be tested is divided into compact district and non-dense set area.
12. wafer defect scanning system as claimed in claim 10, which is characterized in that the region division module by it is each to
Detection zone is divided into compact district and the method in non-dense set area includes:
Prescan is carried out to the wafer, obtains the grey value profile of area to be tested described in the wafer；
According to the grey value profile, each area to be tested is divided into compact district and non-dense set area.
13. wafer defect scanning system as claimed in claim 9, which is characterized in that the Defect Scanning module, comprising:
Setting unit, the verification unit for the compact district to be arranged in Defect Scanning formula are first pixel unit,
The verification unit that the non-dense region is arranged is second pixel unit；
Scanning element, for according to the Defect Scanning formula after setting to the area to be tested each on the wafer into
Row Defect Scanning.
14. wafer defect scanning system as claimed in claim 13, which is characterized in that after the scanning element is according to setting
The method that the Defect Scanning formula carries out Defect Scanning to each area to be tested on the wafer includes:
During Defect Scanning, the incident light aperture and/or emergent light aperture of defect checking machine platform are automatically adjusted, so that currently
The pixel of verification unit reaches the pixel of first pixel unit, so that the defect checking machine platform is with the first pixel list
Member carries out Defect Scanning to the compact district of each area to be tested；And
The incident light aperture and/or emergent light aperture for automatically adjusting defect checking machine platform, so that the pixel of current trial unit reaches
To the pixel of second pixel unit, so that the defect checking machine platform is with second pixel unit to each area to be detected
The non-dense set area in domain carries out Defect Scanning.
15. a kind of fault detection board, which is characterized in that including processor, communication interface, memory and communication bus, wherein
The processor, the communication interface, the memory complete mutual communication by the communication bus；
The memory, for storing computer program；
The processor when for executing the program stored on the memory, realizes any side claim 1-8
Method step.
16. a kind of computer readable storage medium, which is characterized in that be stored with computer in the computer readable storage medium
Program realizes claim 1-8 described in any item method and steps when the computer program is executed by processor.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115656190A (en) * | 2022-12-13 | 2023-01-31 | 广州粤芯半导体技术有限公司 | Defect scanning detection method and device, scanning equipment and readable storage medium |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326436A (en) * | 2005-12-06 | 2008-12-17 | 芝浦机械电子装置股份有限公司 | Appearance inspecting device |
| CN102422405A (en) * | 2009-03-13 | 2012-04-18 | 恪纳腾公司 | Methods and systems for generating an inspection process for a wafer |
| CN103646059A (en) * | 2013-11-29 | 2014-03-19 | 上海华力微电子有限公司 | Scanning machine program control method |
| CN104201130A (en) * | 2014-09-01 | 2014-12-10 | 上海华力微电子有限公司 | Optical detection method for defect classification |
| CN104201132A (en) * | 2014-09-02 | 2014-12-10 | 上海华力微电子有限公司 | Method for improving defect scanning accuracy of bright field machine station |
| CN105931976A (en) * | 2016-05-25 | 2016-09-07 | 上海华力微电子有限公司 | Detection method capable of automatically defining scanning area for bright field scanning device |
| CN106165078A (en) * | 2014-03-25 | 2016-11-23 | 科磊股份有限公司 | Δ nude film and the inspection of Δ database |
| CN106898564A (en) * | 2015-12-18 | 2017-06-27 | 超科技公司 | Holocrystalline chip detection method with optional picture element density |
| CN109560000A (en) * | 2018-11-30 | 2019-04-02 | 上海华力微电子有限公司 | A kind of wafer defect scan method |
| CN109712903A (en) * | 2018-12-27 | 2019-05-03 | 上海华力微电子有限公司 | Electron beam scanning machine electron beam aperture dynamic adjustment structure and test method |
-
2019
- 2019-06-25 CN CN201910555991.2A patent/CN110299298A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326436A (en) * | 2005-12-06 | 2008-12-17 | 芝浦机械电子装置股份有限公司 | Appearance inspecting device |
| CN102422405A (en) * | 2009-03-13 | 2012-04-18 | 恪纳腾公司 | Methods and systems for generating an inspection process for a wafer |
| CN103646059A (en) * | 2013-11-29 | 2014-03-19 | 上海华力微电子有限公司 | Scanning machine program control method |
| CN106165078A (en) * | 2014-03-25 | 2016-11-23 | 科磊股份有限公司 | Δ nude film and the inspection of Δ database |
| CN104201130A (en) * | 2014-09-01 | 2014-12-10 | 上海华力微电子有限公司 | Optical detection method for defect classification |
| CN104201132A (en) * | 2014-09-02 | 2014-12-10 | 上海华力微电子有限公司 | Method for improving defect scanning accuracy of bright field machine station |
| CN106898564A (en) * | 2015-12-18 | 2017-06-27 | 超科技公司 | Holocrystalline chip detection method with optional picture element density |
| CN105931976A (en) * | 2016-05-25 | 2016-09-07 | 上海华力微电子有限公司 | Detection method capable of automatically defining scanning area for bright field scanning device |
| CN109560000A (en) * | 2018-11-30 | 2019-04-02 | 上海华力微电子有限公司 | A kind of wafer defect scan method |
| CN109712903A (en) * | 2018-12-27 | 2019-05-03 | 上海华力微电子有限公司 | Electron beam scanning machine electron beam aperture dynamic adjustment structure and test method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115656190A (en) * | 2022-12-13 | 2023-01-31 | 广州粤芯半导体技术有限公司 | Defect scanning detection method and device, scanning equipment and readable storage medium |
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