CN110290378A - A kind of MIPI DSI TX test method and equipment based on FPGA - Google Patents
A kind of MIPI DSI TX test method and equipment based on FPGA Download PDFInfo
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- CN110290378A CN110290378A CN201910550996.6A CN201910550996A CN110290378A CN 110290378 A CN110290378 A CN 110290378A CN 201910550996 A CN201910550996 A CN 201910550996A CN 110290378 A CN110290378 A CN 110290378A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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Abstract
The present invention relates to interface testing field, in particular to a kind of MIPI DSI TX test method and equipment based on FPGA.A kind of MIPI DSI TX test method based on FPGA parses the DSI TX signal according to analysis protocol and obtains video relevant parameter, the video relevant parameter includes: video timing and video data comprising steps of receiving DSI TX signal；By comparing the video relevant parameter and predefined video relevant parameter, test result is obtained.By the above method, directly remove intermediate conversion chip, not only reduces hardware debugging difficulty and without extra time configuration register.
Description
Technical field
The present invention relates to interface testing field, in particular to a kind of MIPI DSI TX test method based on FPGA and set
It is standby.
Background technique
MIPI (Mobile Industry Processor Interface) is 2003 by ARM, Nokia, ST, TI etc.
The alliance that company sets up, it is therefore an objective to the interface such as camera, display screen interface, radio frequency/baseband interface etc. of interior of mobile phone
Standardization, to reduce the complexity of Cell Phone Design and increase design flexibility.
DSI (Display Serial Interface), defines a height between processor and display module
Fast serial line interface is that the interface specification that display working group formulates has TX (transmitter) and RX (receiver).Now
DSI TX is added all on the embeded processor for oneself and connects as display for many SOC (System On Chip) manufacturers
Mouthful, so test of the DSI TX interface before factory is necessary.
Current test method is that MIPI DSI TX signal is converted to LVDS vision signal by FPGA by conversion chip
Whether correct carry out test interface.Such test method, not only needs conversion chip, it is also necessary to go the deposit of configuration conversion chip
Device increases debugging difficulty and increases the testing time.
Summary of the invention
For this reason, it may be necessary to a kind of MIPI DSI TX test method and equipment based on FPGA be provided, to solve existing FPGA
Test MIPI DSI TX signal is needed through conversion chip, and also needs the register of configuration conversion chip, and debugging difficulty is big and surveys
Try the problem of time length.Specific technical solution is as follows:
A kind of MIPI DSI TX test method based on FPGA is assisted comprising steps of receiving DSI TX signal according to parsing
View parses the DSI TX signal and obtains video relevant parameter, and the video relevant parameter includes: video timing and video data；It is logical
The video relevant parameter and predefined video relevant parameter are crossed, test result is obtained.
Further, described " parse the DSI TX signal according to analysis protocol and obtain video relevant parameter ", further includes step
It is rapid: identification DSI TX signal, and the operation mode to be entered is selected according to recognition result；The operation mode includes: to flee from mould
Formula, control model and high speed transmission mode.
Further, described " parse the DSI TX signal according to analysis protocol and obtain video relevant parameter ", further includes step
It is rapid: using the clock of DSI TX as reference source, the signal of every data line being converted into the data flow of 8bit；Search for the 8bit
Data flow homing sequence；The data flow of the 8bit for the every data line for searching homing sequence is integrated, and from whole
The data packet of long frame and short frame is extracted in data flow after conjunction, and obtains video phase from the data packet of the long frame and short frame
Close parameter.
Further, it further comprises the steps of: and graphically illustrates data flow or portion's dividing control signal to PC.
Further, acquisition test relevant information is further comprised the steps of:, and the test relevant information is printed；Institute
State the data packet that test relevant information includes: test result, video time sequence parameter, the data packet of long frame and/or short frame.
In order to solve the above technical problems, additionally providing a kind of MIPI DSI TX test equipment based on FPGA, particular technique
Scheme is as follows:
A kind of MIPI DSI TX test equipment based on FPGA, comprising: parsing module and video measurement module；The solution
Analysis module is used for: being received DSI TX signal, is parsed the DSI TX signal according to analysis protocol and obtain video relevant parameter, the view
Frequency relevant parameter includes: video timing and video data；The video measurement module is used for: being joined by comparing the video correlation
Several and predefined video relevant parameter obtains test result.
Further, the parsing module further include: pattern recognition module；The pattern recognition module is used for: identification DSI
TX signal, and the operation mode to be entered is selected according to recognition result；The operation mode includes: the mode of fleeing from, control model
And high speed transmission mode.
Further, the parsing module further include: string turns and module, phase alignment module and decoder module；It is described
String turns and module is used for: using the clock of DSI TX as reference source, the signal of every data line being converted into the data flow of 8bit；
The phase alignment module is used for: searching for the homing sequence of the data flow of the 8bit；The decoder module is used for: to search
Data flow to the 8bit of every data line of homing sequence is integrated, and extract from the data flow after integration long frame and
The data packet of short frame, and video relevant parameter is obtained from the data packet of the long frame and short frame.
Further, further includes: logic analyser module；The logic analyser module is used for: by data flow or part
Control signal is graphically illustrated to PC.
Further, further includes: test information search module；The test information search module is used for: obtaining test phase
Information is closed, and the test relevant information is printed；The test relevant information includes: test result, video timing ginseng
The data packet of several, long frame and/or the data packet of short frame.
The beneficial effects of the present invention are: being connected directly by FPGA and MIPI DSI TX interface, DSI TX signal is received,
The DSI TX signal is parsed according to analysis protocol by FPGA and obtains video relevant parameter, by comparing the video relevant parameter with
Predefined video relevant parameter obtains test result.Directly remove intermediate conversion chip, not only reduces hardware debugging difficulty
And it is not necessarily to extra time configuration register.
Further, by graphically illustrating data flow or portion's dividing control signal to PC；Or obtain the related letter of test
Breath, and the test relevant information is printed.Both help intuitive observation signal, quick positioning searching problem.
Detailed description of the invention
Fig. 1 is a kind of flow chart of the MIPI DSI TX test method based on FPGA described in specific embodiment；
Fig. 2 is a kind of module diagram one of the MIPI DSI TX test equipment based on FPGA described in specific embodiment；
Fig. 3 is a kind of module diagram two of the MIPI DSI TX test equipment based on FPGA described in specific embodiment；
Fig. 4 is a kind of module diagram three of the MIPI DSI TX test equipment based on FPGA described in specific embodiment；
Fig. 5 is a kind of module diagram four of the MIPI DSI TX test equipment based on FPGA described in specific embodiment；
Fig. 6 is a kind of module diagram five of the MIPI DSI TX test equipment based on FPGA described in specific embodiment；
Fig. 7 is a kind of schematic diagram of the MIPI DSI TX test equipment based on FPGA described in specific embodiment.
Description of symbols:
200, a kind of MIPI DSI TX test equipment based on FPGA,
201, parsing module,
202, video measurement module,
203, logic analyser module,
204, information search module is tested,
2011, pattern recognition module,
2012, string turns simultaneously module,
2013, phase alignment module,
2014, decoder module.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.
Referring to Fig. 1, in the present embodiment, a kind of MIPI DSI TX test method based on FPGA can be applicable to one
In MIPI DSI TX test equipment of the kind based on FPGA, a kind of MIPI DSI TX test equipment based on FPGA, comprising:
Parsing module and video measurement module.
The MIPI DSI TX test method to a kind of based on FPGA is specifically unfolded to illustrate below:
Step S101: receiving DSI TX signal, parses the DSI TX signal according to analysis protocol and obtains video relevant parameter,
The video relevant parameter includes: video timing and video data.
Step S102: by comparing the video relevant parameter and predefined video relevant parameter, test result is obtained.
It is connected directly by FPGA and MIPI DSI TX interface, DSI TX signal is received, by FPGA according to analysis protocol solution
It analyses the DSI TX signal and obtains video relevant parameter, by comparing the video relevant parameter and predefined video relevant parameter,
Obtain test result.Directly remove intermediate conversion chip, not only reduce hardware debugging difficulty and is configured without extra time
Register.
In the present embodiment, further, described " the DSI TX signal to be parsed according to analysis protocol and obtains video correlation
Parameter " further comprises the steps of: identification DSI TX signal, and selects the operation mode to be entered according to recognition result；The operation mould
Formula includes: the mode of fleeing from, control model and high speed transmission mode.
Further, described " parse the DSI TX signal according to analysis protocol and obtain video relevant parameter ", further includes step
It is rapid: using the clock of DSI TX as reference source, the signal of every data line being converted into the data flow of 8bit；Search for the 8bit
Data flow homing sequence；The data flow of the 8bit for the every data line for searching homing sequence is integrated, and from whole
The data packet of long frame and short frame is extracted in data flow after conjunction, and obtains video phase from the data packet of the long frame and short frame
Close parameter.Specifically it can be used such as under type:
It should be noted that in the present embodiment, above-mentioned steps can be surveyed by a kind of MIPI DSI TX based on FPGA
It tries the string in equipment and turns simultaneously module, phase alignment module and decoder module realization.Wherein string turns and module is according to DSI TX's
The signal of each data line is converted into the data flow of 8bit as reference source by clock.Phase alignment module can be in 8bit number
Homing sequence (SOT) is searched for according in stream, if searched, it will locking data stream, if can not find SOT in a period of time,
The delay value that IO will be adjusted, until detecting SOT in a stream.Decoder module is by the 8bit data flow of every data line
It integrates, extracts long frame and short frame data packet, therefrom obtain video time sequence parameter and video data.
It, can be by comparing the video relevant parameter and predefined view after obtaining video time sequence parameter and video data
Frequency relevant parameter obtains test result.
It further, in the present embodiment, is preferably assistance analysis agreement and debugging.It further comprises the steps of: data
Stream or portion's dividing control signal are graphically illustrated to PC.
It further, in the present embodiment, is preferably assist in debugging.Acquisition test relevant information is further comprised the steps of:,
And the test relevant information is printed；The test relevant information includes: test result, video time sequence parameter, long frame
Data packet and/or short frame data packet.In other embodiments, other required for can also printing according to the actual situation
Test relevant information.
Fig. 2 to Fig. 7 is please referred to, in the present embodiment, a kind of MIPI DSI TX test equipment 200 based on FPGA
Specific embodiment is as follows:
A kind of MIPI DSI TX test equipment 200 based on FPGA, comprising: parsing module 201 and video measurement module
202；The parsing module 201 is used for: being received DSI TX signal, is parsed the DSI TX signal according to analysis protocol and obtain video phase
Parameter is closed, the video relevant parameter includes: video timing and video data；The video measurement module 202 is used for: passing through ratio
The video relevant parameter and predefined video relevant parameter obtain test result.
It is connected directly by FPGA and MIPI DSI TX interface, DSI TX signal is received, by the parsing module 201 of FPGA
The DSI TX signal is parsed according to analysis protocol and obtains video relevant parameter, and video measurement module 202 is by comparing the video
Relevant parameter and predefined video relevant parameter obtain test result.Directly remove intermediate conversion chip, not only reduces hard
Part debugging difficulty and be not necessarily to extra time configuration register.
Further, referring to Fig. 3, the parsing module 201 further include: pattern recognition module 2011；The mode is known
Other module 2011 is used for: identification DSI TX signal, and selects the operation mode to be entered according to recognition result；The operation mode
It include: the mode of fleeing from, control model and high speed transmission mode.
Further, referring to Fig. 4, the parsing module 201 further include: string turns and module 2012, phase alignment module
2013 and decoder module 2014；The string turns and module 2012 is used for: using the clock of DSI TX as reference source, by every number
The data flow of 8bit is converted into according to the signal of line；The phase alignment module 2013 is used for: searching for the data flow of the 8bit
Homing sequence；The decoder module 2014 is used for: being flowed into the data of the 8bit for the every data line for searching homing sequence
Row integration, and extract from the data flow after integration the data packet of long frame and short frame, and from the data of the long frame and short frame
Video relevant parameter is obtained in packet.Specifically it can be used such as under type:
String turn and module 2012 according to the clock of DSI TX as reference source, the signal of each data line is converted into
The data flow of 8bit.Phase alignment module 2013 can search for homing sequence (SOT) in 8bit data flow, if searched,
Will locking data stream, if can not find SOT in a period of time, it will the delay value for adjusting IO, until detecting in a stream
To SOT.Decoder module 2014 integrates the 8bit data flow of every data line, extracts long frame and short frame data packet,
Therefrom obtain video time sequence parameter and video data.
After obtaining video time sequence parameter and video data, video measurement module 202 can be by comparing the video phase
Parameter and predefined video relevant parameter are closed, test result is obtained.
Further, referring to Fig. 5, in the present embodiment, analyzing agreement and debugging for preferably assistance.Further include:
Logic analyser mould, 203；The logic analyser module 203 is used for: by data flow or portion's dividing control signal graphically illustrate to
On PC.
Further, referring to Fig. 6, in the present embodiment, for preferably assist in debugging.Further include: test information is searched
Collect module 204；The test information search module 204 is used for: obtain test relevant information, and to the test relevant information into
Row printing；The test relevant information includes: the data of test result, video time sequence parameter, the data packet of long frame and/or short frame
Packet.
Wherein, a kind of overall schematic of MIPI DSI TX test equipment 200 based on FPGA is as shown in Figure 7.
It should be noted that being not intended to limit although the various embodiments described above have been described herein
Scope of patent protection of the invention.Therefore, it based on innovative idea of the invention, change that embodiment described herein is carried out and is repaired
Change, or using equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it directly or indirectly will be with
Upper technical solution is used in other related technical areas, is included within scope of patent protection of the invention.
Claims (10)
1. a kind of MIPIDSI TX test method based on FPGA, which is characterized in that comprising steps of
DSI TX signal is received, the DSI TX signal is parsed according to analysis protocol and obtains video relevant parameter, the video is related
Parameter includes: video timing and video data；
By comparing the video relevant parameter and predefined video relevant parameter, test result is obtained.
2. a kind of MIPIDSI TX test method based on FPGA according to claim 1, which is characterized in that " the root
The DSI TX signal, which is parsed, according to analysis protocol obtains video relevant parameter ", it further comprises the steps of:
It identifies DSI TX signal, and the operation mode to be entered is selected according to recognition result；
The operation mode includes: the mode of fleeing from, control model and high speed transmission mode.
3. a kind of MIPIDSI TX test method based on FPGA according to claim 1, which is characterized in that " the root
The DSI TX signal, which is parsed, according to analysis protocol obtains video relevant parameter ", it further comprises the steps of:
Using the clock of DSI TX as reference source, the signal of every data line is converted into the data flow of 8bit；
Search for the homing sequence of the data flow of the 8bit；
The data flow of the 8bit for the every data line for searching homing sequence is integrated, and is taken out from the data flow after integration
The data packet of long frame and short frame is taken out, and obtains video relevant parameter from the data packet of the long frame and short frame.
4. a kind of MIPIDSI TX test method based on FPGA according to claim 1, which is characterized in that further include step
It is rapid:
Data flow or portion's dividing control signal are graphically illustrated to PC.
5. a kind of MIPIDSI TX test method based on FPGA according to claim 1, which is characterized in that further include step
It is rapid:
Test relevant information is obtained, and the test relevant information is printed；
The test relevant information includes: the data packet of test result, video time sequence parameter, the data packet of long frame and/or short frame.
6. a kind of MIPIDSI TX test equipment based on FPGA characterized by comprising parsing module and video measurement mould
Block；
The parsing module is used for: being received DSI TX signal, is parsed the DSI TX signal according to analysis protocol and obtain video correlation
Parameter, the video relevant parameter include: video timing and video data；
The video measurement module is used for: by comparing the video relevant parameter and predefined video relevant parameter, being surveyed
Test result.
7. a kind of MIPIDSI TX test equipment based on FPGA according to claim 6, which is characterized in that the parsing
Module further include: pattern recognition module；
The pattern recognition module is used for: identification DSI TX signal, and selects the operation mode to be entered according to recognition result；Institute
Stating operation mode includes: the mode of fleeing from, control model and high speed transmission mode.
8. a kind of MIPIDSI TX test equipment based on FPGA according to claim 6, which is characterized in that the parsing
Module further include: string turns and module, phase alignment module and decoder module；
The string turns and module is used for: using the clock of DSI TX as reference source, the signal of every data line being converted into 8bit
Data flow；
The phase alignment module is used for: searching for the homing sequence of the data flow of the 8bit；
The decoder module is used for: the data flow of the 8bit for the every data line for searching homing sequence integrated, and
The data packet of long frame and short frame is extracted from the data flow after integration, and is regarded from the data packet of the long frame and short frame
Frequency relevant parameter.
9. a kind of MIPIDSI TX test equipment based on FPGA according to claim 6, which is characterized in that further include:
Logic analyser module；
The logic analyser module is used for: data flow or portion's dividing control signal are graphically illustrated to PC.
10. a kind of MIPIDSI TX test equipment based on FPGA according to claim 6, which is characterized in that further include:
Test information search module；
The test information search module is used for: being obtained test relevant information, and is printed to the test relevant information；Institute
State the data packet that test relevant information includes: test result, video time sequence parameter, the data packet of long frame and/or short frame.
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Cited By (1)
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Application publication date: 20190927 |