CN110288087A - A kind of method, circuit, chip and system realizing tanh function and calculating - Google Patents
A kind of method, circuit, chip and system realizing tanh function and calculating Download PDFInfo
- Publication number
- CN110288087A CN110288087A CN201910536062.7A CN201910536062A CN110288087A CN 110288087 A CN110288087 A CN 110288087A CN 201910536062 A CN201910536062 A CN 201910536062A CN 110288087 A CN110288087 A CN 110288087A
- Authority
- CN
- China
- Prior art keywords
- decimal
- value
- place
- integer
- binary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Computational Linguistics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Complex Calculations (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The present invention discloses a kind of method, circuit, chip and system realizing tanh function and calculating, this method comprises: obtaining the decimal system variate-value of tanh function to be processed；Variate-value is converted into binary system and using complement representation；Obtain the complemented value of binary variable, the integer place value and decimal place value of presetting digit capacity；Logical conversion is carried out to the integer place value and decimal place value according to complemented value, obtains binary output value；The logical conversion includes the combination of logic add, logic multiply and complement operation；Binary output value is converted into the decimal system and is exported.It is big that the program solves the problems, such as that chip power consumes, and circuit realizes approximate calculation, improves calculating speed, and reduce power consumption.
Description
Technical field
The present invention relates to technical field of data processing, especially a kind of method for realizing the calculating of tanh function, circuit, chip
And system.
Background technique
Tanh is one of the widest activation primitive applied in deep learning algorithm, and expression formula is as shown in above formula.This
It is one to surmount function, tanh function is as a kind of most basic arithmetical operation function, it is in neural network deep learning and instruction
There is extensive and important application in white silk.The calculating of its full precision be generally basede on general purpose microprocessor by software programming iteration into
Row.The required calculating time is long, and power dissipation overhead is big.The function is difficult to map directly to hardware simultaneously.Existing method calculates
The problem that the computation delay of tanh activation primitive is long, power dissipation overhead is big, at present temporarily without preferable solution.Although processor
Performance rise year by year with improving for technology, but processor its calculating process when carrying out functional operation still needs
Expend a large amount of calculating time.
As deep learning algorithm progresses into the real-times such as automated driving system, mobile phone, wearable device field and embedding
Enter formula field, traditional general purpose microprocessor cannot be met the requirements in speed and power consumption.At the same time, although it is research shows that deep
The training of degree study needs higher precision, but the reasoning process of deep learning does not need too high precision.Therefore, appropriateness
Reduction computational accuracy, to design the computing circuit of high speed low-power consumption, in embedded real time system use deep learning
Technology has very important significance.
Summary of the invention
The present invention provides a kind of method, system and chip realizing tanh function and calculating, hard in the prior art for overcoming
Part resource consumption is big, calculates the defects such as cost height, realizes and saves hardware resource, reduce unnecessary consumption, reduces and calculate cost.
To achieve the above object, the present invention proposes a kind of method realizing tanh function and calculating, comprising the following steps:
Obtain the decimal system variate-value of tanh function to be processed；
Variate-value is converted into binary system and using complement representation；
Obtain the complemented value of binary variable, the integer place value and decimal place value of presetting digit capacity；
Logical conversion is carried out to the integer place value and decimal place value according to complemented value, obtains binary output value；It is described
Logical conversion includes the combination of logic add, logic multiply and complement operation；
Binary output value is converted into the decimal system and is exported.
To achieve the above object, the present invention also provides a kind of circuits realizing tanh function and calculating, comprising:
Sampling module, for obtaining the decimal system variate-value of tanh function to be processed；
Binary arithmetic operation module, for variate-value to be converted to binary system and using complement representation；
Acquisition module, for obtaining the complemented value of binary variable, the integer place value and decimal place value of presetting digit capacity；
Logical operation module is obtained for carrying out logical conversion to the integer place value and decimal place value according to complemented value
Binary output value；Including with or NOT logic gate circuit；
Decimal arithmetic module, for binary output value to be converted to the decimal system and is exported.
To achieve the goals above, the present invention also provides a kind of chips, realize what tanh function calculated including above-mentioned realization
Circuit.
To achieve the goals above, the present invention also provides a kind of system realizing tanh function and calculating, including it is host computer, defeated
Enter circuit, output circuit and the chip；The chip connects the host computer, the input circuit and the output
Circuit.
Method, circuit, chip and the system provided by the invention realizing tanh function and calculating, proposes the Tanh of deep learning
The fast circuit of activation primitive is realized, with the approximate method of combinational logic, finds out fast electric of the tanh function under finite accuracy
The calculating speed of activation primitive can be greatly improved in the implementation method on road, reduce power consumption, and reduce chip area simultaneously, reduce
The chip cost of embedded and real-time deep study.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 is that the binary representation of the variable to be calculated provided in inventive embodiments one corresponds to table；
Fig. 2 is that the binary system of the output provided in the embodiment of the present invention one states corresponding table.
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute is only used in the embodiment of the present invention
In explaining in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, if should
When particular pose changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being such as related to " first ", " second " in the present invention is used for description purposes only, and should not be understood as
Its relative importance of indication or suggestion or the quantity for implicitly indicating indicated technical characteristic.Define as a result, " first ",
The feature of " second " can explicitly or implicitly include at least one of the features.In the description of the present invention, " multiple " contain
Justice is at least two, such as two, three etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " connection ", " fixation " etc. shall be understood in a broad sense,
For example, " fixation " may be a fixed connection, it may be a detachable connection, or integral；It can be mechanical connection, be also possible to
Electrical connection can also be physical connection or wireless communication connection；It can be directly connected, the indirect phase of intermediary can also be passed through
Even, the connection inside two elements or the interaction relationship of two elements be can be, unless otherwise restricted clearly.For this
For the those of ordinary skill in field, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
It in addition, the technical solution between each embodiment of the present invention can be combined with each other, but must be general with this field
Based on logical technical staff can be realized, it will be understood that when the combination of technical solution appearance is conflicting or cannot achieve this
The combination of technical solution is not present, also not the present invention claims protection scope within.
The present invention proposes a kind of method and system.
Embodiment one
Referring to Fig. 1, Fig. 2, the present invention provides a kind of method realizing tanh function and calculating, comprising the following steps:
S1 obtains the decimal system variate-value of tanh function to be processed；
Variate-value is converted to binary system and using complement representation by S2；
S3 obtains the complemented value of binary variable, the integer place value of presetting digit capacity and decimal place value；
S4 carries out logical conversion to the integer place value and decimal place value according to complemented value, obtains binary output value；Institute
State the combination that logical conversion includes logic add, logic multiply and complement operation；
Binary output value is converted to the decimal system and exported by S5.
The present invention proposes a kind of quick calculation method of Tanh function, directly passes through a small amount of basic logical gate circuit counting
The output valve of Tanh function out has the arithmetic speed and minimum area overhead being exceedingly fast.All data of the invention all use 2
The mode of system describes, and received input has 3 decimal places, exports as 6 decimals.
Preferably, described that variate-value is converted into binary system and includes: using the step S2 of complement representation
Decimal system variate-value is converted to binary system by S21；
S22 is rounded numerical digit close to the front two of decimal point；
S23 takes front three of the decimal place close to decimal point；
S24, taking highest order is sign bit.
Consider that inputting function variable ρ to be processed is signed binary, and uses complement representation.Wherein highest order is
Sign bit S, two integer-bits close to decimal point are A and B, and 3 fractional fixed point positions are C, D, E.By the function expression of tanh
It is found that its output valve ε always number between one -1~1, then its integer part is always 0 or 1, emphasis need to consider its decimal
Partial calculating.Positive number negative all uses complement code, and the complement code of positive number is exactly its true form, and negative is negative using complement code.
Preferably, described that logical conversion is carried out to the integer place value and decimal place value according to complemented value, obtain binary system
The step S3 of output valve includes:
S31A is positive in the complemented value, and when binary variable is less than 11,
S32A exports binary integer position and six decimals respectively；
S33A, the Binary Conversion be the decimal system after export.
Preferably, described that logical conversion is carried out to the integer place value and decimal place value according to complemented value, obtain binary system
The step S3 of output valve includes:
S31B is negative in the complemented value, and when binary variable is less than 11,
S32B obtains binary integer position and six decimals respectively；
The Binary Conversion after the decimal system, is taken negative value to export by S33B.
Step S32A, S32B for exporting binary integer position and six decimals respectively includes:
It will be close to second and third after the integer-bit front two value, the product of decimal place front two and decimal point of decimal point
The sum of products of position is as output the first place value of binary fraction position；
It will be close to integer-bit front two value, first decimal place, the complement of second decimal place and the third position of decimal point
The sum of products of the complement of the product of decimal place complement and first decimal place and second decimal place and third position decimal place is made
To export the second place value of binary fraction position；
It will be close to the second integer-bit of decimal point, close to first integer-bit of decimal point and multiplying for first decimal place
Product, the product of first decimal place and the complement of third position decimal place, is leaned on the product of first decimal place and second decimal place
The not anxious of the complement and second decimal place of first integer-bit of nearly decimal point and third position decimal place, close to decimal point the
The sum of products of one integer-bit and second decimal place and third position decimal place is as output binary fraction position third place value；
It will be close to the complement and the first decimal place of the second integer-bit of decimal point, first integer-bit of close decimal point
Complement and the second decimal place product, the complement of first integer-bit close to decimal point and the complement of the first decimal place and the
The product of three decimal places, close to decimal point first integer-bit and second decimal place and third position decimal place complement, the
The product of one decimal place and second decimal place and third position decimal place, close to decimal point first integer-bit complement with
The sum of products of the complement of the complement and third position decimal place of first decimal place and second decimal place is as output binary system
The 4th place value of decimal place；
Will be close to the second integer-bit of decimal point, the complement of the second decimal place with the product of third decimal place, close to small
Product, the complement of the first decimal place of the complement of first integer-bit of several points and the complement of the first decimal place and the second decimal place
The 5th place value with the sum of products of the second decimal place and the complement of third decimal place as output binary fraction position；
Will be close to the complement of the second integer-bit of decimal point and the complement of the second decimal place and third decimal place product,
Close to the second integer-bit of decimal point and product, first decimal place and the complement of second decimal place of the second decimal place
Product, the complement of first integer-bit close to decimal point and the complement of first decimal place and second decimal place and third are small
The sum of products of the product of the complement of numerical digit, first decimal place and third position decimal place is as exporting the of binary fraction position
Six place values.Referring specifically to the following table 1:
Table 1
Note: wherein "+" indicates logic or operation, and "×" indicates logic and operation, and horizontal line "-" indicates logic NOT fortune on letter
It calculates.
Preferably, described that logical conversion is carried out to the integer place value and decimal place value according to complemented value, obtain binary system
The step 3 of output valve includes:
S301A is positive in the complemented value, and binary variable be greater than or equal to 11 when,
S302A exports binary integer position and six decimals respectively；
S303A, integer-bit is 1 after the decimal system of the Binary Conversion position, the equal position 0 of six decimal places.
Preferably, described that logical conversion is carried out to the integer place value and decimal place value according to complemented value, obtain binary system
The step S3 of output valve includes:
S301B is negative in the complemented value, and binary variable be greater than or equal to 11 when,
S302B exports binary integer position and six decimals respectively；
S303B, integer-bit is 1 after the decimal system of the Binary Conversion position, the equal position 0 of six decimal places, take it is negative after export.
It is that specific embodiment is illustrated respectively below by two:
Specific embodiment 1:
The technical solution that the present invention calculates tanh is divided into 2 kinds of situations.The first situation, as ρ > 0, steps are as follows for calculating:
Step 1: then terminating to calculate if it is 0 that ρ >=3, ε integer part, which is 1,6 decimals (ε f0~ε f5),；
If ρ < 3, into second step；
Step 2: the integer part of ε is that 0,6 decimals are calculated by the logical expression in table 1 respectively.
Assuming that ρ=2.85, it is expressed as binary system: 010.111, wherein be rounded after decimal point 4 by nearby principle.That
:
A=1 B=0 C=1 D=1 E=1
It is calculated from table 1:
ε f0=1+0+1 × 1+1 × 1=1
F1=1+0+1 × 0 ε × 0+0 × 1 × 1=1
ε f2=1+0 × 1+1 × 1+1 × 0+1 × 1 × 0+0 × 1 × 1=1
F3=1+1 × 0 ε × 1+1 × 0 × 1+0 × 1 × 0+1 × 1 × 1+1 × 1 × 0 × 0=1
F4=1+0 × 1+1 × 0 ε × 1+0 × 1 × 0=1
F5=0 × 0 ε × 1+1 × 1+1 × 0+1 × 0 × 1 × 0+1 × 1=1
The result that this method is calculated is ε=(0.111111)2=(0.984375)10, and accurately counted by general algorithm
Known to calculating tanh (2.85)=0.99333.This algorithm only has about 1% error known to comparison.
Specific embodiment 2:
For second situation as ρ < 0, steps are as follows for calculating:
Step 1: taking opposite number to obtain ρ ' ρ, ρ ' is a positive number
Step 2: being based on the first situation, ε '=tanh (ρ ') is calculated
Step 3: the opposite number of ε ' is taken to obtain ε (i.e. ε=- ε ').
It illustrates.Assuming that ρ=- 1.7, takes its opposite number, ρ '=1.7.ρ ' is expressed as binary system: 001.110, wherein
It is rounded after decimal point 4 by nearby principle.So: A=0B=1C=1D=1E=0.It is calculated from table 1:
ε f0=0+1+1 × 1+1 × 0=1
F1=0+1+1 × 0 ε × 1+0 × 1 × 0=1
ε f2=0+1 × 1+1 × 1+1 × 1+0 × 1 × 1+1 × 1 × 0=1
F3=0+0 × 0 ε × 1+0 × 0 × 0+1 × 1 × 1+1 × 1 × 0+0 × 1 × 0 × 1=1
F4=0+0 × 0+0 × 0 ε × 1+0 × 1 × 1=0
F5=1 × 0 ε × 0+0 × 1+1 × 0+0 × 0 × 1 × 1+1 × 0=0
The result ε ' that this method is calculated is (0.111100)2。
Take opposite number ε=- ε '=(- 0.111100)2=(- 0.9375)10, and accurately calculated by general algorithm and know tanh
(- 1.7)=- 0.9354.This algorithm only has the error less than 0.01% known to comparison.
Embodiment two
Based on the above embodiment one, the present invention also provides a kind of circuits realizing tanh function and calculating, comprising:
Sampling module, for obtaining the decimal system variate-value of tanh function to be processed；
Binary arithmetic operation module, for variate-value to be converted to binary system and using complement representation；
Acquisition module, for obtaining the complemented value of binary variable, the integer place value and decimal place value of presetting digit capacity；
Logical operation module is obtained for carrying out logical conversion to the integer place value and decimal place value according to complemented value
Binary output value；Including with or NOT logic gate circuit, respectively carry out add operation, multiplying and non-(supplementary set) operation；
Decimal arithmetic module, for binary output value to be converted to the decimal system and is exported.
Operation of the invention only by it is a small number of with or NOT logic operation, and these basic logic operations are highly susceptible to
The hardware realization on silicon integrated circuit reduces power consumption, and reduce chip simultaneously so that the calculating speed of activation primitive be greatly improved
Area reduces the chip cost of embedded and real-time deep study.
Embodiment three
Based on embodiment two, the present invention also proposes a kind of chip, including the above-mentioned circuit for realizing the calculating of tanh function
Any embodiment.
Example IV
Based on the above embodiment three, the present invention also proposes a kind of system realizing tanh function and calculating, including host computer, defeated
Enter any embodiment of circuit, output circuit and above-mentioned chip；The chip connects the host computer, the input circuit
And the output circuit.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all at this
Under the inventive concept of invention, using equivalent structure transformation made by description of the invention and accompanying drawing content, or directly/use indirectly
It is included in other related technical areas in scope of patent protection of the invention.
Claims (10)
1. a kind of method realizing tanh function and calculating, which comprises the following steps:
Obtain the decimal system variate-value of tanh function to be processed；
Variate-value is converted into binary system and using complement representation；
Obtain the complemented value of binary variable, the integer place value and decimal place value of presetting digit capacity；
Logical conversion is carried out to the integer place value and decimal place value according to complemented value, obtains binary output value；The logic
Transformation includes the combination of logic add, logic multiply and complement operation；
Binary output value is converted into the decimal system and is exported.
2. realizing the method that tanh function calculates as described in claim 1, which is characterized in that described that variate-value is converted to two
System and using complement representation the step of includes:
Decimal system variate-value is converted into binary system；
Numerical digit is rounded close to the front two of decimal point；
Take front three of the decimal place close to decimal point；
Taking highest order is sign bit.
3. as claimed in claim 2 realize tanh function calculate method, which is characterized in that it is described according to complemented value to described
The step of integer place value and decimal place value carry out logical conversion, obtain binary output value include:
It is positive in the complemented value, and when binary variable is less than 11,
Binary integer position and six decimals are exported respectively；
The Binary Conversion be the decimal system after export.
4. as claimed in claim 2 realize tanh function calculate method, which is characterized in that it is described according to complemented value to described
The step of integer place value and decimal place value carry out logical conversion, obtain binary output value include:
It is negative in the complemented value, and when binary variable is less than 11,
Binary integer position and six decimals are obtained respectively；
By the Binary Conversion be the decimal system after, take negative value to export.
5. as described in claim 3 or 4 realize tanh function calculate method, which is characterized in that it is described respectively output two into
The step of integer-bit processed and six decimals includes:
It will be close to second and third position after the integer-bit front two value, the product of decimal place front two and decimal point of decimal point
The sum of products is as output the first place value of binary fraction position；
It will be close to integer-bit front two value, first decimal place, the complement of second decimal place and the third position decimal of decimal point
The product and complement and the second decimal place of first decimal place and the sum of products of third position decimal place of position complement are as defeated
The second place value of binary fraction position out；
Will be close to decimal point second integer-bit, close to decimal point first integer-bit and first decimal place product,
It is the product of first decimal place and second decimal place, the product of first decimal place and the complement of third position decimal place, close
The complement and second decimal place of first integer-bit of decimal point and the not anxious of third position decimal place, close to decimal point first
The sum of products of position integer-bit and second decimal place and third position decimal place is as output binary fraction position third place value；
It will be close to the benefit of the second integer-bit of decimal point, the complement of first integer-bit of close decimal point and the first decimal place
Several and the second decimal place product, the complement and third of the complement and the first decimal place of first integer-bit of close decimal point are small
The complement of the product of numerical digit, first integer-bit close to decimal point and second decimal place and third position decimal place, first
The complement and first of the product of decimal place and second decimal place and third position decimal place, first integer-bit of close decimal point
The sum of products of the complement of the complement and third position decimal place of position decimal place and second decimal place is as output binary fraction
The 4th place value of position；
It will be close to the second integer-bit of decimal point, the product of the complement of the second decimal place and third decimal place, close to decimal point
The complement of first integer-bit and the product of the complement of the first decimal place and the second decimal place, the complement of the first decimal place and the
Fiveth place value of the sum of products of the complement of two decimal places and third decimal place as output binary fraction position；
It will be close to the complement of the second integer-bit of decimal point and the product of the complement of the second decimal place and third decimal place, close
Product, first decimal place of the second integer-bit of decimal point and the second decimal place multiply with the complement of second decimal place
Product, the complement of first integer-bit close to decimal point and the complement of first decimal place and second decimal place and third decimal
The sum of products of the product of the complement of position, first decimal place and third position decimal place is as exporting the 6th of binary fraction position
Place value.
6. as claimed in claim 2 realize tanh function calculate method, which is characterized in that it is described according to complemented value to described
The step of integer place value and decimal place value carry out logical conversion, obtain binary output value include:
Be positive in the complemented value, and binary variable be greater than or equal to 11 when,
Binary integer position and six decimals are exported respectively；
Integer-bit is 1 after the decimal system of the Binary Conversion position, the equal position 0 of six decimal places.
7. as claimed in claim 2 realize tanh function calculate method, which is characterized in that it is described according to complemented value to described
The step of integer place value and decimal place value carry out logical conversion, obtain binary output value include:
Be negative in the complemented value, and binary variable be greater than or equal to 11 when,
Binary integer position and six decimals are exported respectively；
Integer-bit is 1 after the decimal system of the Binary Conversion position, the equal position 0 of six decimal places, takes and exports after bearing.
8. a kind of circuit realizing tanh function and calculating characterized by comprising
Sampling module, for obtaining the decimal system variate-value of tanh function to be processed；
Binary arithmetic operation module, for variate-value to be converted to binary system and using complement representation；
Acquisition module, for obtaining the complemented value of binary variable, the integer place value and decimal place value of presetting digit capacity；
Logical operation module, for carrying out logical conversion to the integer place value and decimal place value according to complemented value, obtain two into
Output valve processed；Including with logic gates or logic gates, NOT logic gate circuit；
Decimal arithmetic module, for binary output value to be converted to the decimal system and is exported.
9. a kind of chip, which is characterized in that the circuit calculated including realization tanh function according to any one of claims 8.
10. it is a kind of realize tanh function calculate system, which is characterized in that including host computer, input circuit, output circuit and
Chip as claimed in claim 9；The chip connects the host computer, the input circuit and the output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910536062.7A CN110288087B (en) | 2019-06-20 | 2019-06-20 | Method, circuit, chip and system for realizing tanh function calculation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910536062.7A CN110288087B (en) | 2019-06-20 | 2019-06-20 | Method, circuit, chip and system for realizing tanh function calculation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110288087A true CN110288087A (en) | 2019-09-27 |
| CN110288087B CN110288087B (en) | 2020-11-20 |
Family
ID=68004720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910536062.7A Active CN110288087B (en) | 2019-06-20 | 2019-06-20 | Method, circuit, chip and system for realizing tanh function calculation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110288087B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108021537A (en) * | 2018-01-05 | 2018-05-11 | 南京大学 | A kind of softmax implementations based on hardware platform |
| CN109508784A (en) * | 2018-12-28 | 2019-03-22 | 四川那智科技有限公司 | A kind of design method of neural network activation primitive |
-
2019
- 2019-06-20 CN CN201910536062.7A patent/CN110288087B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108021537A (en) * | 2018-01-05 | 2018-05-11 | 南京大学 | A kind of softmax implementations based on hardware platform |
| CN109508784A (en) * | 2018-12-28 | 2019-03-22 | 四川那智科技有限公司 | A kind of design method of neural network activation primitive |
Non-Patent Citations (2)
| Title |
|---|
| VISHNU P. NAMBIAR等: "Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function", 《NEUROCOMPUTING》 * |
| XJTU_NOC_WEI: "sigmoid函数导数的硬件实现(verilog)", 《HTTPSBLOG.CSDN.NETXJTU_NOC_WEIARTICLEDETAILS53613599》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110288087B (en) | 2020-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3660629B1 (en) | Data processing apparatus and method | |
| Guo et al. | Software-hardware codesign for efficient neural network acceleration | |
| US20190102671A1 (en) | Inner product convolutional neural network accelerator | |
| CN104598432B (en) | Computer and method for solving mathematical functions | |
| CN106951211B (en) | A kind of restructural fixed and floating general purpose multipliers | |
| CN110084221A (en) | A kind of serializing face critical point detection method of the tape relay supervision based on deep learning | |
| US20210350210A1 (en) | Method and apparatus for keeping statistical inference accuracy with 8-bit winograd convolution | |
| CN110163363A (en) | A kind of computing device and method | |
| CN107305484A (en) | A kind of nonlinear function arithmetic unit and method | |
| CN111797982A (en) | Image processing system based on convolution neural network | |
| CN105426156B (en) | A kind of non-precision multiplier of high-performance and its application process | |
| Kumar et al. | Analysis of effectiveness of power on refined numerical models of floating point arithmetic unit for biomedical applications | |
| Juang et al. | Circuit implementation of data-driven TSK-type interval type-2 neural fuzzy system with online parameter tuning ability | |
| Jovanović et al. | A survey of hardware self-organizing maps | |
| CN111033462A (en) | Providing efficient floating point operations using matrix processors in processor-based systems | |
| Adapa et al. | Coordinate Rotation-Based Low Complexity $ K $-Means Clustering Architecture | |
| Jia et al. | Exploiting approximate feature extraction via genetic programming for hardware acceleration in a heterogeneous microprocessor | |
| US20210397414A1 (en) | Area and energy efficient multi-precision multiply-accumulate unit-based processor | |
| CN110288087A (en) | A kind of method, circuit, chip and system realizing tanh function and calculating | |
| Lin et al. | A fully digital SRAM-based four-layer in-memory computing unit achieving multiplication operations and results store | |
| Chung et al. | Tightly coupled machine learning coprocessor architecture with analog in-memory computing for instruction-level acceleration | |
| Wu et al. | Design and realization of short range defence radar target tracking system based on DSP/FPGA | |
| CN110245750A (en) | A kind of neural network method for numerical simulation based on FPGA | |
| CN104823153B (en) | Processor, method, communication equipment, machine readable media, the equipment and equipment for process instruction of normalization add operation for execute instruction | |
| CN102073473A (en) | Field programmable gata array (FPGA)-based metric floating-point multiplier design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220314 Address after: 410205 building 15, phase I, Changsha Zhongdian Software Park, No. 39, Jianshan Road, high tech Development Zone, Changsha, Hunan Patentee after: HUNAN GREATWALL GALAXY TECHNOLOGY Co.,Ltd. Patentee after: National University of Defense Technology Address before: 410000 rooms 2-8 and 2-13, podium building of Changsha Zhongdian software park headquarters building, No. 39 Jianshan Road, high tech Development Zone, Changsha, Hunan Patentee before: HUNAN GREATWALL GALAXY TECHNOLOGY Co.,Ltd. |