CN110287030A - Memory application method and device - Google Patents

Memory application method and device Download PDF

Info

Publication number
CN110287030A
CN110287030A CN201910579175.5A CN201910579175A CN110287030A CN 110287030 A CN110287030 A CN 110287030A CN 201910579175 A CN201910579175 A CN 201910579175A CN 110287030 A CN110287030 A CN 110287030A
Authority
CN
China
Prior art keywords
address
range
memory
subaddressing
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910579175.5A
Other languages
Chinese (zh)
Other versions
CN110287030B (en
Inventor
何晓明
刘硕
李峰
宋炳雨
许晓梦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Weichai Power Co Ltd
Original Assignee
Weichai Power Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Weichai Power Co Ltd filed Critical Weichai Power Co Ltd
Priority to CN201910579175.5A priority Critical patent/CN110287030B/en
Publication of CN110287030A publication Critical patent/CN110287030A/en
Application granted granted Critical
Publication of CN110287030B publication Critical patent/CN110287030B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory

Abstract

The embodiment of the present application provides a kind of memory application method and device, this method comprises: obtaining total address range of the assigned memory of processing unit;Compiling file corresponding each subaddressing range when obtaining code compilation;According to the corresponding each subaddressing range of total address range and compiling file, determine processing unit to the utilization rate of memory;The memory being not used by memory is used according to utilization rate.The processing unit that the embodiment of the present application obtains is more accurate to the utilization rate of memory, the utilization rate for the memory being assigned according to processing unit uses the memory being not used by memory, it can also realize the reasonable distribution to the memory of processing unit, improve the utilization rate to the memory of processing unit.

Description

Memory application method and device
Technical field
The present embodiments relate to computer technology more particularly to a kind of memory application method and devices.
Background technique
With the fast development of computer field, it is increasing that data are stored in the effect that the field occupies.For chip The effective use of storage resources is widely paid close attention to.
The method of statistics chip memory source utilization rate is mainly and reads to use from the compiling file that compiling generates at present Chip memory source the last one address, subtract the first address of chip memory source, the chip memory used Resource obtains chip memory source utilization rate according to the chip memory source and not used chip memory source that have used.
And compiler usually requires to be aligned with its byte length in the address of compile-time variable in memory, therefore, no With byte length variable interlock define may result in compiler be variable distribution address it is discontinuous, therefore, the above method The method for obtaining chip memory source utilization rate is inaccurate.
Summary of the invention
The embodiment of the present application provides a kind of memory application method and device, and available accurate chip memory source uses Rate.
In a first aspect, the embodiment of the present application provides a kind of memory application method, which comprises obtain processing unit quilt Total address range of the memory of distribution;Compiling file corresponding each subaddressing range when obtaining code compilation;According to the processing The total address range and the corresponding each subaddressing range of the compiling file of the assigned memory of unit, determine the processing unit To the utilization rate of the memory;The memory being not used by the memory is used according to the utilization rate.
In the present solution, the total address range and the corresponding each subaddressing of compiling file of the memory being assigned according to processing unit Range determines processing unit to the utilization rate of the memory, and obtained processing unit is more accurate to the utilization rate of memory, according to place The utilization rate of the assigned memory of unit is managed using the memory being not used by memory, can also realize the memory to processing unit Reasonable distribution, improve the utilization rate to the memory of processing unit.
With reference to first aspect, described according to total address range in a kind of possible implementation of first aspect Each subaddressing range corresponding with the compiling file, determines the processing unit to the utilization rate of the memory, comprising: in institute It states in each address that total address range includes, with determining the target for being contained in the corresponding subaddressing range of the compiling file Location;According to the number for the address that the number of the destination address and total address range include, the processing unit pair is determined The utilization rate of the memory.
Utilization rate of the available accurate processing unit of this programme to memory.
With reference to first aspect, in a kind of possible implementation of first aspect, described according to the mark address The number for the address that number and total address range include, before determining the processing unit to the utilization rate of the memory, Include: the memory being assigned using the processing unit each address as each first key value, and by described each first The corresponding numerical value of key value is set to the first numerical value, to construct the first dictionary;The corresponding numerical value of the destination address is counted from first Value is updated to second value;The number of the second value is counted, the number of the second value is the number of the destination address Mesh.
Present solution provides a kind of specific implementations for counting destination address number.
With reference to first aspect, in a kind of possible implementation of first aspect, include in total address range In each address, the destination address for being contained in the corresponding subaddressing range of the compiling file is determined, comprising: with the compiling text The mark of the corresponding each subaddressing range of part as each second key value, using the corresponding initial address of subaddressing range as The first numerical value and termination address of corresponding second key value of the subaddressing range are closed as the subaddressing range corresponding second The second value of key assignments, to construct the second dictionary;According to second dictionary, in each address that total address range includes In, determine the destination address for being contained in the corresponding subaddressing range of the compiling file.
This programme passes through building mapping datatypes, total address model of the assigned memory of more intuitive display processing unit Enclose the address range of the middle memory used.
With reference to first aspect, in a kind of possible implementation of first aspect, the acquisition processing unit is assigned Memory total address range, comprising: total address range of the assigned memory of the processing unit is obtained from threaded file.
Present solution provides a kind of concrete modes of total address range in memory that acquisition processing unit is assigned.
Second aspect, the embodiment of the present application provide a kind of device that memory uses, including obtain module, processing module and answer With module, which is characterized in that the acquisition module, for obtaining total address range of the assigned memory of processing unit;It obtains Compiling file corresponding each subaddressing range when code compilation;The processing module is used for according to total address range and the compiling The corresponding each subaddressing range of file, determines the processing unit to the utilization rate of the memory;The application module is used for root The memory being not used by the memory is used according to the utilization rate.
In conjunction with second aspect, in a kind of possible implementation of second aspect, the processing module is used for according to institute Total address range and the corresponding each subaddressing range of the compiling file are stated, determines use of the processing unit to the memory Rate, comprising: the processing module is specifically used in each address that total address range includes, and determination is contained in the volume The destination address of the corresponding subaddressing range of translation part;Include according to the number of the destination address and total address range The number of address determines the processing unit to the utilization rate of the memory.
In conjunction with second aspect, in a kind of possible implementation of second aspect, the processing module is being used for basis The number for the address that the number of the destination address and total address range include, determines the processing unit to the memory Utilization rate before, be also used to: using the processing unit be assigned memory each address as each first key value, and The corresponding numerical value of each first key value is set to the first numerical value, to construct the first dictionary;The destination address is corresponding Numerical value be updated to second value from the first numerical value;The number of the second value is counted, the number of the second value is institute State the number of destination address.
In conjunction with second aspect, in a kind of possible implementation of second aspect, the processing module is used for described In each address that total address range includes, the destination address for being contained in the corresponding subaddressing range of the compiling file is determined, It include: that the processing module is specifically used for using the mark of the corresponding each subaddressing range of the compiling file as each second Key value, using the corresponding initial address of subaddressing range as the first numerical value of corresponding second key value of the subaddressing range and Second value of the termination address as corresponding second key value of the subaddressing range, to construct the second dictionary;According to described Two dictionaries, in each address that total address range includes, determination is contained in the corresponding subaddressing model of the compiling file The destination address enclosed.
In conjunction with second aspect, in a kind of possible implementation of second aspect, the acquisition module is at acquisition Manage total address range of the assigned memory of unit, comprising: the processing module is specifically used for from threaded file described in acquisition Total address range of the assigned memory of processing unit.
The third aspect, the embodiment of the present application provide a kind of electronic equipment, including processor and memory, which is characterized in that Instruction is stored in the memory, the processor executes first aspect and first aspect is appointed for calling described instruction Method described in one possible implementation.
Fourth aspect, the embodiment of the present application provides a kind of computer readable storage medium, including program or instruction, when described When program or instruction are run on computers, method quilt described in first aspect and any possible implementation of first aspect It executes.
Memory application method provided by the present application and device, through the processing unit total address range of assigned memory and When code compilation, the corresponding each subaddressing range of compiling file determines that processing unit to the utilization rate of memory, makes according to utilization rate With the memory being not used by memory.Obtained processing unit is more accurate to the utilization rate of memory, can also realize to processing The reasonable distribution of the memory of unit improves the utilization rate to the memory of processing unit.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair Bright some embodiments for those of ordinary skill in the art without any creative labor, can be with It obtains other drawings based on these drawings.
Fig. 1 is the flow chart one of memory application method provided by the embodiments of the present application;
Fig. 2 is the flowchart 2 of memory application method provided by the embodiments of the present application;
Fig. 3 is the structural schematic diagram for the device that memory provided by the embodiments of the present application uses;
Fig. 4 is the structural schematic diagram of electronic equipment provided by the embodiments of the present application.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Fig. 1 is the flow chart one of memory application method provided by the embodiments of the present application, and memory provided in this embodiment uses Method can be applied to memory use device.Memory use device can be a part that computer is also possible to computer, calculate Machine can be terminal, such as car-mounted terminal, can also be server.As shown in Figure 1, the method for the present embodiment may include:
Step S101, total address range of the assigned memory of processing unit is obtained.
Wherein, processing unit can be the processing unit in computer, for example processing unit is applied in automobile ECU, the other processing units being also possible in computer are not intended to limit in the application.
Wherein, total address range of the assigned memory of processing unit include in the assigned memory of processing unit it is all not The address range of the address range of the memory used and all used memories.
Acquisition for total address range of the assigned memory of processing unit obtains processing unit in a kind of mode Total address range of assigned memory, comprising: total address model of the assigned memory of processing unit is obtained from threaded file It encloses.
Threaded file refers to a kind of file generated in compilation process, is assigned in threaded file comprising processing unit interior The total address range deposited, can from threaded file the assigned memory of reading processing unit total address range.
Total address range that the assigned memory of processing unit can also be obtained by other means, here, the application is not It is limited.
Step S102, compiling file corresponding each subaddressing range when obtaining code compilation.
It wherein, can be to processing unit write-in program, during write-in program in the integrating process of current processing unit One or more compiling files can be generated, such as in code compilation process to code compilation, during to code compilation The compiling file of " .MAP " type generated.It include the corresponding each subaddressing range of compiling file, compiling file in compiling file Corresponding each subaddressing range is therefore the range for the address that compiling file occupies can read compiling from compiling file The corresponding each subaddressing range of file.
It is understood that address included by each subaddressing range corresponding to compiling file is assigned for processing unit Memory total address range in address.Address included by each subaddressing range corresponding to compiling file is processing unit The address used in assigned memory.
Wherein, the corresponding each subaddressing of compiling file may range from the corresponding each address of each object in compiling file Range.The corresponding each address range of object is the range for the address that the object occupies.Wherein, object include but is not limited to variable, Function.
Step S103, according to the corresponding each subaddressing range of total address range and compiling file, determine processing unit to for The utilization rate of the memory of processing unit distribution.
In order to which " utilization rate of the processing unit to the memory distributed for processing unit " is expressed as by the convenience of subsequent statement " utilization rate of the processing unit to memory "
As described in step S102, address included by each subaddressing range corresponding to compiling file is that processing unit is divided The address used in the memory matched, therefore, each subaddressing range and processing unit according to corresponding to compiling file are assigned Total address range of memory, it may be determined that utilization rate of the processing unit corresponding to current processing unit integrating process to memory.
It will be appreciated by those skilled in the art that processing unit corresponding to current processing unit integrating process makes memory The processing unit corresponding to rate therewith pretreatment unit integrating process is processing unit to memory to the sum of utilization rate of memory Overall availability.
Step S104, it is not used by the memory being assigned according to utilization rate of the processing unit to memory using processing unit Memory.
The utilization rate for the memory being assigned according to processing unit can determine specific in the memory being assigned in processing unit How many memory has been used and also how many memory can be used, and in the follow-up process, processing can be used in processing unit Not used memory in the assigned memory of unit.
Illustratively, processing unit ECU, when ECU is integrated, it is assumed that the memory usage of ECU is 30%, can be determined Memory in ECU assigned memory there are also 70% is not used by, can be according to ECU when integrate again to ECU chip 70% memory being not used by assigned memory, carries out the distribution of memory.
Total address range of memory assigned through the processing unit and the corresponding each son ground of compiling file in the present embodiment Location range determines the utilization rate of the assigned memory of processing unit, since the corresponding each subaddressing range of compiling file is compiling The corresponding each address range of each object in file does not include the address being not used by, therefore, the processing that the present embodiment determines Unit is more accurate to the utilization rate of memory.The utilization rate for the memory being assigned according to processing unit in memory using being not used by Memory, can also realize the reasonable distribution to the memory of processing unit, improve the utilization rate to the memory of processing unit.
Several specific embodiments are used below, illustrate the specific determining method of the memory usage in an embodiment.
Fig. 2 is the flowchart 2 of memory application method provided by the embodiments of the present application, and the method for the present embodiment may include:
Step S201, in each address that total address range includes, determination is contained in the corresponding subaddressing of compiling file The destination address of range.
Wherein, each address son ground corresponding with compiling file in the total address range for memory processing unit being assigned Location range compares, if some address for the memory that processing unit is assigned is in the corresponding subaddressing range of compiling file It is interior, then it can determine that this address is the address used in the assigned memory of processing unit, i.e. destination address.
In one implementation, in each address that total address range includes, determine that being contained in compiling file corresponds to Subaddressing range destination address, comprising:
A1, using the mark of the corresponding each subaddressing range of compiling file as each second key value, with subaddressing model First numerical value of the corresponding initial address as corresponding second key value of the subaddressing range is enclosed, it is corresponding with subaddressing range Second value of the termination address as corresponding second key value of the subaddressing range, to construct the second dictionary.
That is the construction of the second dictionary is as follows: using the mark of the corresponding each subaddressing range of compiling file as the second key Value, i.e. key (key) value.Any one first subaddressing range in each subaddressing range corresponding for compiling file, by First numerical value (i.e. first of the corresponding initial address of one subaddressing range as corresponding second key value of the first subaddressing range Value value), using the corresponding termination address of the first subaddressing range as the of corresponding second key value of the first subaddressing range Two numerical value (i.e. the 2nd value value), obtain the second dictionary.Wherein, corresponding second key value of subaddressing range is son ground The mark of location range.
Wherein, dictionary is a kind of mapping datatypes, and working principle is similar to Hash table, by key-value (key-value) to structure At.The dictionary is also possible to other mapping datatypes, here, in the application with no restrictions.
A2, according to the second dictionary, in each address that total address range includes, determine that be contained in compiling file corresponding The destination address of subaddressing range.
According to each address that the numerical value of each second key value in the second dictionary and total address range include, determination includes In the destination address of the corresponding subaddressing range of compiling file.The first address that even a certain total address range includes is a certain the Address between the two values of two key values or the two values, then the first address is destination address.
Illustratively, total address range of the assigned memory of processing unit is 1~address of address 20, and compiling file is corresponding Each subaddressing range be 1~address of address 3,5~address of address 8, by processing unit be assigned memory total address range Including each address each subaddressing range corresponding with compiling file compare, it may be determined that processing unit be assigned it is interior The address 1 in total address range deposited, address 2, address 3, address 5, address 6, address 7, that address 8 is in compiling file is corresponding Within the scope of subaddressing, therefore destination address is address 1, address 2, address 3, address 5, address 6, address 7, address 8.
Step S202, the ground for including according to total address range of the assigned memory of the number of destination address and processing unit The number of location determines processing unit to the utilization rate of memory.
Since corresponding processing unit in the integrating process of current processing unit is to utilization rate=current place of memory Manage the integrating process of unit, the assigned corresponding total address of memory of number/processing unit of address used in compiling file Number.Number, that is, current processing unit integrating process of destination address, the number of address used in compiling file, processing The memory that the number i.e. processing unit for the address that total address range of the assigned memory of unit includes is assigned is corresponding generally The number of location, therefore the number for the address for including according to the number of destination address and total address range, it is available currently processed Utilization rate of the processing unit to memory in the integrating process of unit.
It is understood that the number for the address for including according to the number of destination address and total address range, determines processing Before unit is to the utilization rate of memory, further includes: determine the number of destination address.
A kind of implementation for the number for determining destination address is illustrated below.
Determine the number of destination address, comprising:
B1, the memory being assigned using processing unit each address as each first key value, and by described each the The corresponding numerical value of one key value is set to the first numerical value, to construct the first dictionary.
Optionally, the first numerical value can be 0.
By taking above-mentioned key-value is to the dictionary of composition as an example, each address for the memory being assigned using processing unit is as first Corresponding numerical value (value) value of each first key value is set to the first numerical value, to construct first by key value, i.e. key (key) value Dictionary.
Illustratively, total address range of the assigned memory of processing unit is 1~address of address 25, by this 25 addresses As key assignments, corresponding first numerical value of key assignments can be set to 0, to construct the first dictionary.
B2, the corresponding numerical value of destination address is updated to second value from the first numerical value.
Optionally, second value can be 1.
Illustratively, total address range of the assigned memory of processing unit is 1~address of address 25, and destination address is ground This corresponding first numerical value 0 of 4 destination addresses in dictionary 1 is updated to second value 1 by location 1, address 2, address 5, address 6.
B3, the number for counting second value, the number of second value are the number of destination address.
After determining the number of destination address, the address that can include according to the number and total address range of destination address Number determines processing unit to the utilization rate of memory.
Illustratively, the number for counting second value in the first dictionary counts 1 in the first dictionary when second value is 1 Number, the number of second value 1 is the number of destination address in the first dictionary.
In each address that the total address range for the memory that processing unit is assigned includes, determination is contained in the present embodiment The destination address of the corresponding subaddressing range of compiling file, the number of addresses for including according to the number of destination address and total address range Mesh determines processing unit to the utilization rate of memory, so that the processing unit determined is more accurate to the utilization rate of memory, and method Simply, it is easy to accomplish.
Memory application method provided by the embodiments of the present application is illustrated above, below using specifically embodiment pair Device provided by the embodiments of the present application is illustrated.
Fig. 3 is the structural schematic diagram for the device that memory provided by the embodiments of the present application uses.As shown in figure 3, the present embodiment Device may include: to obtain module 31, processing module 32 and application module 33.
The acquisition module 31, for obtaining total address range of the assigned memory of processing unit;Obtain code compilation When the corresponding each subaddressing range of compiling file;The processing module 32 is used for according to total address range and the compiling file pair Each subaddressing range answered, determines the processing unit to the utilization rate of the memory;The application module 33 is used for according to institute It states utilization rate and uses the memory being not used by the memory.
Optionally, as one embodiment, the processing module 32 is used for according to total address range and the compiling The corresponding each subaddressing range of file, determines the processing unit to the utilization rate of the memory, comprising: the processing module tool Body is used in each address that total address range includes, and determination is contained in the corresponding subaddressing range of the compiling file Destination address;According to the number for the address that the number of the destination address and total address range include, the place is determined Unit is managed to the utilization rate of the memory.
Optionally, as one embodiment, the processing module 32 for according to the destination address number and institute The number for stating the address that total address range includes is also used to before determining the processing unit to the utilization rate of the memory: with Each address of the assigned memory of the processing unit is as each first key value, and by each first key value pair The numerical value answered is set to the first numerical value, to construct the first dictionary;The corresponding numerical value of the destination address is updated to from the first numerical value Second value;The number of the second value is counted, the number of the second value is the number of the destination address.
Optionally, as one embodiment, the processing module 32 be used for total address range include eachly In location, the destination address for being contained in the corresponding subaddressing range of the compiling file is determined, comprising: the processing module is specifically used In using the mark of the corresponding each subaddressing range of the compiling file as each second key value, corresponded to subaddressing range Initial address as corresponding second key value of the subaddressing range the first numerical value and termination address as the subaddressing model The second value of corresponding second key value is enclosed, to construct the second dictionary;According to second dictionary, in total address range Including each address in, determine and be contained in the destination address of the corresponding subaddressing range of the compiling file.
Optionally, as one embodiment, the module 32 that obtains is used to obtain the total of the assigned memory of processing unit Address range, comprising: the processing module is specifically used for obtaining the assigned memory of the processing unit from threaded file Total address range.
Fig. 4 is the structural schematic diagram of electronic equipment 40 provided by the embodiments of the present application, as shown in figure 4, the electricity of the present embodiment Sub- equipment, including processor 41 and memory 42, instruction is stored in memory 42, and processor 41 is used for call instruction, control Execute method described in any embodiment in above-described embodiment.
The specific implementation process of processor 41 can be found in above method embodiment, and it is similar that the realization principle and technical effect are similar, Details are not described herein again for the present embodiment.
The application also provides a kind of computer readable storage medium, and calculating is stored in the computer readable storage medium Machine executes instruction, and when processor executes the computer executed instructions, realizes memory application method as above.
Above-mentioned computer readable storage medium, above-mentioned readable storage medium storing program for executing can be by any kind of volatibility or non- Volatile storage devices or their combination realize that, such as static random access memory (SRAM), electrically erasable is only It reads memory (EEPROM), Erasable Programmable Read Only Memory EPROM (EPROM), programmable read only memory (PROM) is read-only to deposit Reservoir (ROM), magnetic memory, flash memory, disk or CD.Readable storage medium storing program for executing can be general or specialized computer capacity Any usable medium enough accessed.
A kind of illustrative readable storage medium storing program for executing is coupled to processor, to enable a processor to from the readable storage medium storing program for executing Information is read, and information can be written to the readable storage medium storing program for executing.Certainly, readable storage medium storing program for executing is also possible to the composition portion of processor Point.Processor and readable storage medium storing program for executing can be located at specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC) in.Certainly, processor and readable storage medium storing program for executing can also be used as discrete assembly and be present in equipment In.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above-mentioned each method embodiment can lead to The relevant hardware of program instruction is crossed to complete.Program above-mentioned can be stored in a computer readable storage medium.The journey When being executed, execution includes the steps that above-mentioned each method embodiment to sequence;And storage medium above-mentioned include: ROM, RAM, magnetic disk or The various media that can store program code such as person's CD.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations;To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement;And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (12)

1. a kind of memory application method characterized by comprising
Obtain total address range of the assigned memory of processing unit;
Compiling file corresponding each subaddressing range when obtaining code compilation;
According to the corresponding each subaddressing range of total address range and the compiling file, determine the processing unit to described The utilization rate of memory;
The memory being not used by the memory is used according to the utilization rate.
2. the method according to claim 1, wherein described according to total address range and the compiling file Corresponding each subaddressing range, determines the processing unit to the utilization rate of the memory, comprising:
In each address that total address range includes, determination is contained in the corresponding subaddressing range of the compiling file Destination address;
According to the number for the address that the number of the destination address and total address range include, the processing unit pair is determined The utilization rate of the memory.
3. according to the method described in claim 2, it is characterized in that, according to the number of the destination address and total address model Enclose including address number, before determining the processing unit to the utilization rate of the memory, further includes:
It is closed as each first key value, and by described each first each address for the memory being assigned using the processing unit The corresponding numerical value of key assignments is set to the first numerical value, to construct the first dictionary;
The corresponding numerical value of the destination address is updated to second value from the first numerical value;
The number of the second value is counted, the number of the second value is the number of the destination address.
4. according to the method described in claim 2, it is characterized in that, in each address that total address range includes, really Surely it is contained in the destination address of the corresponding subaddressing range of the compiling file, comprising:
Using the mark of the corresponding each subaddressing range of the compiling file as each second key value, with subaddressing range pair The initial address answered as corresponding second key value of the subaddressing range the first numerical value and termination address as the subaddressing The second value of corresponding second key value of range, to construct the second dictionary;
According to second dictionary, in each address that total address range includes, determination is contained in the compiling file The destination address of corresponding subaddressing range.
5. method according to claim 1-4, which is characterized in that described to obtain the assigned memory of processing unit Total address range, comprising:
Total address range of the assigned memory of the processing unit is obtained from threaded file.
6. a kind of device that memory uses, including obtain module, processing module and application module, which is characterized in that the acquisition Module, for obtaining total address range of the assigned memory of processing unit;
Compiling file corresponding each subaddressing range when obtaining code compilation;
The processing module is used to determine the place according to the corresponding each subaddressing range of total address range and the compiling file Unit is managed to the utilization rate of the memory;
The application module is used to use the memory being not used by the memory according to the utilization rate.
7. device according to claim 6, which is characterized in that the processing module be used for according to total address range and The corresponding each subaddressing range of the compiling file, determines the processing unit to the utilization rate of the memory, comprising:
The processing module is specifically used in each address that total address range includes, and determines and is contained in the compiling text The destination address of the corresponding subaddressing range of part;
According to the number for the address that the number of the destination address and total address range include, the processing unit pair is determined The utilization rate of the memory.
8. device according to claim 7, which is characterized in that the processing module is for according to the destination address The number for the address that number and total address range include, before determining the processing unit to the utilization rate of the memory, It is also used to:
It is closed as each first key value, and by described each first each address for the memory being assigned using the processing unit The corresponding numerical value of key assignments is set to the first numerical value, to construct the first dictionary;
The corresponding numerical value of the destination address is updated to second value from the first numerical value;
The number of the second value is counted, the number of the second value is the number of the destination address.
9. device according to claim 7, which is characterized in that the processing module for including in total address range Each address in, determine and be contained in the destination address of the corresponding subaddressing range of the compiling file, comprising:
The processing module is specifically used for using the mark of the corresponding each subaddressing range of the compiling file as each second Key value, using the corresponding initial address of subaddressing range as the first numerical value of corresponding second key value of the subaddressing range and Second value of the termination address as corresponding second key value of the subaddressing range, to construct the second dictionary;
According to second dictionary, in each address that total address range includes, determination is contained in the compiling file The destination address of corresponding subaddressing range.
10. according to the described in any item devices of claim 6-9, which is characterized in that the acquisition module is single for obtaining processing Total address range of the assigned memory of member, comprising:
The processing module is specifically used for obtaining total address range of the assigned memory of the processing unit from threaded file.
11. a kind of electronic equipment, including processor and memory, which is characterized in that instruction is stored in the memory, it is described For processor for calling described instruction, perform claim requires the described in any item methods of 1-5.
12. a kind of computer readable storage medium, including program or instruction, which is characterized in that when described program or instruction are being counted When running on calculation machine, any method of claim 1-5 is performed.
CN201910579175.5A 2019-06-28 2019-06-28 Memory use method and device Active CN110287030B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910579175.5A CN110287030B (en) 2019-06-28 2019-06-28 Memory use method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910579175.5A CN110287030B (en) 2019-06-28 2019-06-28 Memory use method and device

Publications (2)

Publication Number Publication Date
CN110287030A true CN110287030A (en) 2019-09-27
CN110287030B CN110287030B (en) 2021-08-20

Family

ID=68019766

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910579175.5A Active CN110287030B (en) 2019-06-28 2019-06-28 Memory use method and device

Country Status (1)

Country Link
CN (1) CN110287030B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080162793A1 (en) * 2006-12-28 2008-07-03 Genesys Logic, Inc. Management method for reducing utilization rate of random access memory (ram) used in flash memory
CN102063363A (en) * 2010-01-26 2011-05-18 深圳市同洲电子股份有限公司 Memory footprint statistical device and method
CN102734896A (en) * 2012-07-06 2012-10-17 青岛海尔空调电子有限公司 Method and device for monitoring operation environments of multi-split air-conditioning system
CN102831069A (en) * 2012-06-30 2012-12-19 华为技术有限公司 Memory processing method and memory management equipment
CN106469118A (en) * 2015-08-19 2017-03-01 深圳市博巨兴实业发展有限公司 A kind of memorizer Memory Allocation access method and device
CN107015914A (en) * 2016-01-28 2017-08-04 长城汽车股份有限公司 Data scaling method and system
CN108319504A (en) * 2018-03-19 2018-07-24 武汉斗鱼网络科技有限公司 EMS memory occupation optimization method, device and readable storage medium storing program for executing
CN109710396A (en) * 2017-10-26 2019-05-03 华为技术有限公司 A kind of method and device of information collection and memory release

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080162793A1 (en) * 2006-12-28 2008-07-03 Genesys Logic, Inc. Management method for reducing utilization rate of random access memory (ram) used in flash memory
CN102063363A (en) * 2010-01-26 2011-05-18 深圳市同洲电子股份有限公司 Memory footprint statistical device and method
CN102831069A (en) * 2012-06-30 2012-12-19 华为技术有限公司 Memory processing method and memory management equipment
CN102734896A (en) * 2012-07-06 2012-10-17 青岛海尔空调电子有限公司 Method and device for monitoring operation environments of multi-split air-conditioning system
CN106469118A (en) * 2015-08-19 2017-03-01 深圳市博巨兴实业发展有限公司 A kind of memorizer Memory Allocation access method and device
CN107015914A (en) * 2016-01-28 2017-08-04 长城汽车股份有限公司 Data scaling method and system
CN109710396A (en) * 2017-10-26 2019-05-03 华为技术有限公司 A kind of method and device of information collection and memory release
CN108319504A (en) * 2018-03-19 2018-07-24 武汉斗鱼网络科技有限公司 EMS memory occupation optimization method, device and readable storage medium storing program for executing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
李江雄: "嵌入式linux内存管理设计与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 *
颜丽: "嵌入式系统内存自动化统计方法研究", 《萍乡学院学报》 *

Also Published As

Publication number Publication date
CN110287030B (en) 2021-08-20

Similar Documents

Publication Publication Date Title
CN109976761B (en) Software development kit generation method and device and terminal equipment
JP5868429B2 (en) Method, computer program product, and apparatus for progressively unloading classes using a region-based garbage collector
CN102722432B (en) Follow the trail of the method and apparatus of internal storage access
CN110187832B (en) Data operation method, device and system
CN111324427A (en) Task scheduling method and device based on DSP
CN102591787B (en) The data processing method of JAVA card and device
CN106020735A (en) Data storage method and device
CN108984328A (en) A kind of method and device of Stack back trace
CN109582649A (en) A kind of metadata storing method, device, equipment and readable storage medium storing program for executing
CN102855137B (en) Methods and procedures design system for the programming of automation component
JP2019215847A (en) Reducing buffer overflow
CN110781016B (en) Data processing method, device, equipment and medium
CN109460237A (en) The Compilation Method and device of code
US20130152049A1 (en) Warning of register and storage area assignment errors
CN109063210A (en) Resource object querying method, device, equipment and the storage medium of storage system
US8990515B2 (en) Aliasing buffers
CN110287030A (en) Memory application method and device
CN104516823B (en) A kind of date storage method and device
CN110333870B (en) Simulink model variable distribution processing method, device and equipment
CN112035380B (en) Data processing method, device and equipment and readable storage medium
CN108563507A (en) A kind of EMS memory management process, device, equipment and readable storage medium storing program for executing
CN111897745B (en) Data storage method and device, electronic equipment and storage medium
CN111967767A (en) Business risk identification method, device, equipment and medium
CN117406933B (en) Solid state disk data processing method and device, electronic equipment and storage medium
CN113220604B (en) Memory application method and device, electronic equipment and computer readable storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant