CN110266311B - TIADC system mismatch error calibration method, device, equipment and medium - Google Patents

TIADC system mismatch error calibration method, device, equipment and medium Download PDF

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CN110266311B
CN110266311B CN201910461906.6A CN201910461906A CN110266311B CN 110266311 B CN110266311 B CN 110266311B CN 201910461906 A CN201910461906 A CN 201910461906A CN 110266311 B CN110266311 B CN 110266311B
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tiadc
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CN110266311A (en
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曹喆
胡佳栋
赵雷
刘树彬
安琪
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University of Science and Technology of China USTC
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    • H03—ELECTRONIC CIRCUITRY
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    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
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Abstract

The utility model provides a TIADC system mismatch error calibration method, which relates to the technical field of signal processing and comprises the following steps: calculating direct current offset mismatch error, gain mismatch error and clock phase mismatch error of each sub-ADC channel, calculating reconstruction gain parameter, reconstruction direct current parameter and reconstruction phase parameter of each sub-ADC channel, adding reconstruction direct current parameter to the product of signal data and reconstruction gain parameter of each sub-ADC channel to obtain signal data correction data of each sub-ADC channel, splicing and filtering the signal data correction data of each sub-ADC channel, and adding the product of filtering waveform data and reconstruction phase parameter to the spliced data to obtain the data of the finally corrected analog signal. The disclosure also provides a TIADC system mismatch error calibration device, equipment and medium. The method provided by the disclosure unifies the calculation form for correcting the TIADC mismatch error, reduces the consumption of DSP resources in the calculation process, and simultaneously reduces the requirement on the functional diversity of the DSP.

Description

TIADC system mismatch error calibration method, device, equipment and medium
Technical Field
The present disclosure relates to the field of signal processing technologies, and in particular, to a method, an apparatus, a device, and a medium for calibrating a TIADC system mismatch error.
Background
In modern scientific research, many fields such as waveform digitization and wireless communication in physical experiments have increasingly high requirements on the sampling rate and precision of an Analog-to-Digital Converter (ADC). Therefore, a Time Interleaved Analog to Digital Converter (TIADC) using a plurality of sub-ADCs is one of effective methods for improving the sampling rate while maintaining high precision.
Due to inconsistency among sub-ADC channels in the TIADC, direct current offset mismatch error, gain mismatch error and clock phase mismatch error exist in signal transmission among the channels, and measurement accuracy of the TIADC is poor. Therefore, the mismatch error of the TIADC needs to be calibrated to improve the measurement accuracy of the TIADC.
Han Le Duc et al proposed a Digital Calibration method for TIADC mismatch errors (full Digital feed feedback Calibration of Clock skiws for Sub-Sampling TIADCs Using the polymeric phase composition). The method can estimate and correct the mismatch of input signals in any Nyquist zone of the TIADC, and is suitable for TIADC with any channel number. However, when the calibration method is implemented in a Field Programmable Gate Array (FPGA), the following disadvantages exist: (1) the calculation form of the correction method is not reasonable compared with a Digital Signal Processor (DSP for short) in the FPGA, and the waste of DSP resources is caused; (2) the calculation form of the correction method is not uniform, which is not beneficial to reducing the consumption of DSP resources through the time-sharing multiplexing of the DSP resources; (3) for a stable TIADC system, the mismatch error does not need to be estimated as often, so leaving the estimated part in the FPGA is a waste of DSP resources.
Disclosure of Invention
The technical problem to be solved by the present disclosure is to optimize the calculation form for correcting the signal data in the TIADC system mismatch error calibration method, unify the calculation form, fully utilize the calculation capability of the DSP resource in the FPGA, and reduce the consumption of the DSP resource in the calculation process.
One aspect of the present disclosure provides a TIADC system mismatch error calibration method, including: s1, calculating a direct current offset mismatch error, a gain mismatch error and a clock phase mismatch error generated when a standard sine signal is transmitted and sampled in each sub-ADC channel of the TIADC system; s2, calculating the reconstruction gain parameter, the reconstruction direct current parameter and the reconstruction phase parameter of each sub ADC channel based on the direct current bias mismatch error, the gain mismatch error and the clock phase mismatch error; s3, when analog signals are input into the TIADC system, acquiring signal data of each sub-ADC channel, wherein the correction data corresponding to the signal data of each sub-ADC channel is obtained by adding the corresponding reconstruction direct current parameter to the product of the signal data of each sub-ADC channel and the corresponding reconstruction gain parameter; and S4, splicing the corresponding correction data of the signal data of each sub-ADC channel to obtain TIADC waveform data, filtering the TIADC waveform data to obtain filtered waveform data, and adding the product of the filtered waveform data and the corresponding reconstruction phase parameter to the TIADC waveform data to obtain the finally corrected data of the analog signal.
Optionally, the calculating the reconstructed gain parameter, the reconstructed direct current parameter, and the reconstructed phase parameter of each sub-ADC channel based on the dc offset mismatch error and the gain mismatch error includes: respectively setting the DC bias mismatch error, the gain mismatch error and the clock phase mismatch error of each sub ADC channel as om、gmAnd tmThe reconstructed gain parameter, the reconstructed direct current parameter and the reconstructed phase parameter are g 'respectively'm、o′mAnd t'mWherein m represents the number of each sub-ADC channel, then:
Figure BDA0002076377710000021
Figure BDA0002076377710000022
t′m＝-tm。
optionally, the obtaining of the correction data corresponding to the signal data of each sub-ADC channel by adding the corresponding reconstruction direct-current parameter to the product of the signal data of each sub-ADC channel and the corresponding reconstruction gain parameter includes: let the signal data of each sub ADC channel be am[k]The corresponding correction data of the signal data of each sub ADC channel is bm[k]The reconstructed gain parameter is g'mThe reconstructed direct current parameter is o'mWherein m represents each sub-ADC channel number, k represents a sampling data serial number, then:
bm[k]＝am[k]×g′m+o′m。
optionally, the merging the correction data corresponding to the signal data of each sub-ADC channel to obtain TIADC waveform data, and performing filtering processing on the TIADC waveform data to obtain filtered waveform data includes: comparing the TIADC waveform data withA preset filter performs convolution calculation to obtain the filtering waveform data; let the TIADC waveform data be
Figure BDA0002076377710000031
The preset filter is h [ n ]]The corresponding correction data of the signal data of each sub ADC channel is bm[k]The filter waveform data is
Figure BDA0002076377710000032
Then:
Figure BDA0002076377710000033
Figure BDA0002076377710000034
wherein n denotes a serial number of TIADC waveform data obtained by combining correction data corresponding to the signal data of each sub-ADC channel, M denotes the number of sub-ADCs constituting the TIADC in the TIADC system, M denotes the number of each sub-ADC channel, M is 0, 1.
Optionally, the performing convolution calculation on the TIADC waveform data and a preset filter includes: the preset filter consists of a basic filter and a window function; wherein the base filter is symmetrically truncated; let the preset filter be h [ i ]]The basic filter is hb[i]The window function is w [ i ]]And then:
Figure BDA0002076377710000035
h[i]＝hb[i]×w[i]，-L≤i≤L；
where p denotes the p nyquist zone of the analog signal at the TIADC of the TIADC system, and L denotes the length of the truncation which symmetrizes the base filter.
Optionally, the obtaining data of the finally corrected analog signal by adding the product of the filtered waveform data and the corresponding reconstructed phase parameter to the TIADC waveform data includes: let the TIADC waveform data be
Figure BDA0002076377710000041
The filter waveform data is
Figure BDA0002076377710000042
The reconstruction phase parameter is t'mThe finally corrected data of the analog signal is y [ n ]]Wherein n denotes a serial number of the TIADC waveform data, M denotes the number of sub-ADCs constituting the TIADC in the TIADC system, M denotes a channel number of each sub-ADC, M is 0, 1.
Figure BDA0002076377710000043
Optionally, the calculating a dc offset mismatch error, a gain mismatch error, and a clock phase mismatch error generated when one standard sinusoidal signal is transmitted in each sub-ADC channel of the TIADC system includes: s11, inputting a standard sine signal into the TIADC system, and sampling the signal data of each sub-ADC channel; s12, fitting the signals of the sub ADC channels respectively based on the signal data to obtain the amplitude, the phase and the direct current offset of the signals of the sub ADC channels; s13, respectively carrying out direct current offset elimination and gain normalization processing on the signal data of each sub ADC channel; s14, splicing the data processed in the step S13 to obtain TIADC waveform data; s15, processing the TIADC waveform data to obtain the frequency of the standard sinusoidal signal shifted to the frequency of the first Nyquist zone of the TIADC system; s16, calculating the actual frequency of the standard sinusoidal signal based on the frequency of the standard sinusoidal signal in the first Nyquist zone of the TIADC system; s17, correspondingly adjusting the phase of the signal of each sub-ADC channel based on the actual frequency of the standard sinusoidal signal and the sampling rate of each sub-ADC channel to obtain the actual phase of the signal of each sub-ADC channel; s18, respectively calculating gain mismatch errors and direct current offset mismatch errors of the sub ADC channels based on the amplitude and the direct current offset of the signal of each sub ADC channel; calculating the clock phase mismatch error of each sub-ADC channel based on the actual phase of the signal of each sub-ADC channel.
Another aspect of the present disclosure provides a TIADC system mismatch error calibration apparatus, including: the first processing module is used for calculating a direct current offset mismatch error, a gain mismatch error and a clock phase mismatch error generated when a standard sinusoidal signal is transmitted in each sub-ADC channel of the TIADC system; the second processing module is used for calculating the reconstruction gain parameters and the reconstruction direct-current parameters of each sub ADC channel based on the direct-current offset mismatch errors and the gain mismatch errors; the third processing module is used for acquiring the signal data of each sub-ADC channel when an analog signal is input into the TIADC system, wherein the product of the signal data of each sub-ADC channel and the corresponding reconstruction gain parameter is added with the corresponding reconstruction direct current parameter to obtain the corresponding correction data of the signal data of each sub-ADC channel; and the fourth processing module is used for splicing the correction data corresponding to the signal data of each sub-ADC channel to obtain TIADC waveform data, filtering the TIADC waveform data to obtain filtered waveform data, and adding the product of the filtered waveform data and the corresponding reconstruction phase parameter to the TIADC waveform data to obtain the finally corrected data of the analog signal.
Another aspect of the present disclosure provides an electronic device including: memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the TIADC system mismatch error calibration method according to any of the first aspect when executing the computer program.
Another aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the TIADC system mismatch error calibration method of any one of the first aspect.
The embodiment of the present disclosure adopts at least one technical scheme that can achieve the following beneficial effects:
the invention provides a TIADC mismatch error calibration method, a TIADC mismatch error calibration device, TIADC mismatch error calibration equipment and TIADC mismatch error calibration media, wherein the TIADC mismatch error, the TIADC mismatch error and the TIADC mismatch error are estimated, and signals input into the TIADC system are corrected according to the TIADC mismatch error, the TIADC mismatch error and the TIADC mismatch error. The calculation forms of the correction method are calculation sequences of performing multiplication calculation and then performing addition calculation, bit widths of a DSP adder and a multiplier in an FPGA in a TIADC system can be effectively utilized, and due to the unification of the calculation forms, the correction method can be realized by using a multiplier-adder in the calculation form of 'P ═ A × B + C', so that the consumption of DSP resources is reduced, and meanwhile, the requirement on the functional diversity of the DSP is reduced. In addition, because the direct-current bias mismatch error, the gain mismatch error and the clock phase mismatch error of each sub-ADC only need to be estimated once, the estimation of the mismatch error can be implemented in an off-line manner, and the consumption of DSP resources in the FPGA is further reduced.
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For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 schematically illustrates a flow chart of a TIADC mismatch error calibration method according to an embodiment of the present disclosure;
FIG. 2 schematically illustrates a schematic diagram of steps S3-S4 in a TIADC mismatch error calibration method according to an embodiment of the present disclosure;
fig. 3A schematically illustrates a filter structure used for filtering in step S4 in a TIADC mismatch error calibration method according to an embodiment of the present disclosure;
FIG. 3B is a schematic diagram of another filter structure used for filtering in the digital calibration method for TIADC mismatch errors;
FIG. 4 schematically illustrates a block diagram of a TIADC mismatch error calibration apparatus according to an embodiment of the present disclosure; and
fig. 5 schematically shows a block diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
Some block diagrams and/or flow diagrams are shown in the figures. It will be understood that some blocks of the block diagrams and/or flowchart illustrations, or combinations thereof, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions, which execute via the processor, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
Accordingly, the techniques of this disclosure may be implemented in hardware and/or software (including firmware, microcode, etc.). In addition, the techniques of this disclosure may take the form of a computer program product on a computer-readable medium having instructions stored thereon for use by or in connection with an instruction execution system. In the context of this disclosure, a computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the instructions. For example, the computer readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of the computer readable medium include: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); a memory, such as a Random Access Memory (RAM) or a flash memory; and/or wired/wireless communication links.
The embodiment of the disclosure provides a TIADC mismatch error calibration method, a device, equipment and a medium, which are used for estimating a DC bias mismatch error, a gain mismatch error and a clock phase mismatch error of each sub-ADC of a TIADC system and correcting a signal input into the TIADC system according to the DC bias mismatch error, the gain mismatch error and the clock phase mismatch error.
Fig. 1 schematically illustrates a TIADC mismatch error calibration method according to an embodiment of the present disclosure.
As shown in fig. 1, a method for calibrating a TIADC mismatch error according to an embodiment of the disclosure includes the following steps:
and S1, calculating direct current offset mismatch error, gain mismatch error and clock phase mismatch error generated when a standard sine signal is transmitted and sampled in each sub-ADC channel of the TIADC system.
The estimation procedure for the TIADC mismatch error is described below.
S11, a standard sinusoidal signal is input into the TIADC system, and the signal data of each sub-ADC channel is sampled.
Let the number M of sub-ADCs forming the TIADC in the TIADC system be fsWith a sampling period of TsThen T iss＝1/fsEach sub-ADC has a sampling rate of f1＝fsThe sampling period of each sub ADC is T1＝MTs。
The signal data obtained by sampling each sub ADC channel is
Figure BDA0002076377710000081
Where M is 0, 1, …, M-1, and k denotes a sample data number.
In step S11, a standard sinusoidal signal is input into the TIADC system, and the reference values of the dc offset mismatch error, the gain mismatch error, and the clock phase mismatch error of each sub-ADC channel can be obtained by calculating the dc offset mismatch error, the gain mismatch error, and the clock phase mismatch error in each sub-ADC channel when the standard sinusoidal signal is transmitted in the TIADC system, and can be used for correcting analog signals input into the TIADC system.
And S12, fitting the signals of the sub ADC channels respectively based on the signal data to obtain the amplitude, the phase and the direct current offset of the signals of the sub ADC channels.
The signal fit for each sub-ADC channel used the sinusoidal four-parameter fit method given in IEEE Standard 1241-.
Let the signal data of each sub-ADC channel be
Figure BDA0002076377710000082
The amplitude, the phase and the DC offset of the signal of each sub ADC channel are respectively gm、φfit，m、omThe number obtained by fitting the signals of each sub-ADC channel is
Figure BDA0002076377710000083
Then:
Figure BDA0002076377710000084
wherein, M represents the number of sub-ADCs constituting the TIADC in the TIADC system, M is the number of each sub-ADC channel, and M is 0, 1.
And S13, respectively carrying out direct current offset elimination and gain normalization processing on the signal data of each sub ADC channel.
Let the processed signal data of each sub ADC channel be a'm[k]The processing formula is as follows:
Figure BDA0002076377710000091
and S14, combining the data obtained through the processing of the step S13 to obtain TIADC waveform data.
Let TIADC waveform data be
Figure BDA0002076377710000092
Then:
Figure BDA0002076377710000093
where n is Mk + M, M represents the number of sub-ADCs that make up the TIADC in the TIADC system, M represents each sub-ADC channel number, and M is 0, 1.
S15, the TIADC waveform data is processed, and the frequency of the obtained standard sinusoidal signal is shifted to the frequency of the first Nyquist zone of the TIADC system.
The four-parameter fitting method of sine given in IEEE Standard 1241-
Figure BDA0002076377710000095
Fitting or Fourier transforming the TIADC waveform data to obtain the frequency f 'of the signal represented by the TIADC waveform data after folding and shifting to the first Nyquist zone of the TIADC system'NB＝1。
S16, calculating an actual frequency of the standard sinusoidal signal based on a frequency of the standard sinusoidal signal in a first nyquist zone of the TIADC system.
Calculating the actual frequency f of a standard sinusoidal signalsinThe calculation formula of (2) is as follows:
Figure BDA0002076377710000094
where p denotes that the frequency of the standard sinusoidal signal is in the p-th nyquist zone of the TIADC.
Although the actual frequency of the standard sinusoidal signal is similar to the known standard sinusoidal signal frequency, since the frequencies of the sinusoidal signals calibrated by different systems have slight differences, the following f is used for calculating more accurate mismatch errorsinThe calculation is performed as the frequency of a standard sinusoidal signal.
And S17, correspondingly adjusting the phase of the signal of each sub-ADC channel based on the actual frequency of the standard sinusoidal signal and the sampling rate of each sub-ADC channel to obtain the actual phase of the signal of each sub-ADC channel.
From the above steps, the sampling rate of each sub-ADC channel is f1. Assuming that the standard sinusoidal signal is in the q-th Nyquist zone of each sub-ADC, then
Figure BDA0002076377710000107
According to the periodicity of the function(s),
Figure BDA0002076377710000101
can be rewritten as:
Figure BDA0002076377710000102
it should be noted that, in this embodiment, it is assumed that the sub-ADC channel 0 is designated as a reference channel, that is, the gain of the sub-ADC channel 0 is taken as an ideal gain, and the sampling time of the sub-ADC channel 0 is considered to be ideal, and there is no clock phase mismatch error.
If q is an even number, let phi0＝-φfit，0If q is an odd number, let phi0＝φfit，0Sampling clock sum according to sub-ADC channel 0The phase relationships between the sampling clocks of the remaining sub-ADC channels, for the mth channel, are:
Figure BDA0002076377710000103
wherein, M is 1, 2.
From this, it can be calculated that the integer λ that can make both sides of the above equation be closest, and the actual phase of the signal of each sub-ADC channel except the sub-ADC channel 0 is:
Figure BDA0002076377710000104
s18, respectively calculating gain mismatch errors and direct current bias mismatch errors of the sub ADC channels based on the amplitude and the direct current bias of the signal of each sub ADC channel; calculating the clock phase mismatch error of each sub-ADC channel based on the actual phase of the signal of each sub-ADC channel.
Let the DC offset mismatch error of each sub-ADC channel be omThe gain mismatch error of each sub-ADC channel relative to channel 0 is gmThe clock phase mismatch error of each channel relative to channel 0 is tmThe sampling period of the TIADC system is TsAnd then:
om＝om；
Figure BDA0002076377710000105
Figure BDA0002076377710000106
wherein, M is 0, 1.
For a stable TIADC system, the method can be applied to the correction of signals input into the TIADC system only by once estimating the DC bias mismatch error, the gain mismatch error and the clock phase mismatch error of each sub-ADC, so that the method for estimating the DC bias mismatch error, the gain mismatch error and the clock phase mismatch error of each sub-ADC can be implemented by additionally programming software offline, is not implemented in an FPGA of the TIADC system, and thus the consumption of DSP resources in the FPGA is reduced.
And S2, calculating the reconstruction gain parameter, the reconstruction direct current parameter and the reconstruction phase parameter of each sub ADC channel based on the direct current offset mismatch error, the gain mismatch error and the clock phase mismatch error.
Respectively setting the DC bias mismatch error, the gain mismatch error and the clock phase mismatch error of each sub ADC channel as om、gmAnd tmThe reconstructed gain parameter, the reconstructed direct current parameter and the reconstructed phase parameter are g'm、o′mAnd t'mWhere m denotes the number of each sub ADC channel, then:
Figure BDA0002076377710000111
Figure BDA0002076377710000112
t′m＝-tm；
where M is 0, 1, and M-1, M represents the number of sub-ADCs that make up the TIADC in the TIADC system.
And S3, when the analog signal is input into the TIADC system, acquiring the signal data of each sub-ADC channel, and adding the product of the signal data of each sub-ADC channel and the corresponding reconstruction gain parameter to the corresponding reconstruction direct current parameter to obtain the correction data corresponding to the signal data of each sub-ADC channel.
When an analog signal is input into the TIADC system, the analog signal is corrected, and signal data of the analog signal transmitted in each sub-ADC channel is collected firstly. In the embodiment of the present disclosure, the frequency component of the known signal needs to be removed from the frequency with the maximum dc external power, and only the signal within a certain frequency range needs to be corrected.
Signalling of sub-ADC channelsNumber am[k]The signal data of each sub ADC channel corresponds to correction data bm[k]The reconstructed gain parameter is g'mAnd the reconstructed direct current parameter is o'mWherein m represents each sub-ADC channel number, k represents a sampling data serial number, then:
bm[k]＝am[k]×g′m+o′m；
where M is 0, 1, and M-1, M represents the number of sub-ADCs that make up the TIADC in the TIADC system.
Step S4, the correction data corresponding to the signal data of each sub-ADC channel are merged to obtain TIADC waveform data, the TIADC waveform data is filtered to obtain filtered waveform data, and the final corrected data of the analog signal is obtained by adding the product of the filtered waveform data and the corresponding reconstruction phase parameter to the TIADC waveform data.
Splicing the corresponding correction data of the signal data of each sub-ADC channel to obtain TIADC waveform data, and filtering the TIADC waveform data to obtain filtered waveform data, wherein the filtering comprises the following steps:
performing convolution calculation on the TIADC waveform data and a preset filter to obtain filtering waveform data;
let TIADC waveform data be
Figure BDA0002076377710000121
Preset filter is h [ n ]]The signal data of each sub ADC channel corresponds to correction data bm[k]The filtered waveform data is
Figure BDA0002076377710000122
Then:
Figure BDA0002076377710000123
Figure BDA0002076377710000124
n represents the serial number of TIADC waveform data obtained by combining the correction data corresponding to the signal data of each sub-ADC channel, M represents the number of sub-ADCs forming the TIADC in the TIADC system, M represents the serial number of each sub-ADC channel, M is 0, 1, M-1, k represents the serial number of sampling data, n is Mk + M, i represents the data serial number of a preset filter, and L represents a positive integer.
Furthermore, on the basis, a plurality of preset filters h [ n ] and TIADC waveform data can be used for parallel calculation, so that the calculation rate of the process is improved.
Convolving the TIADC waveform data with a preset filter includes:
the preset filter consists of a basic filter and a window function;
wherein the basic filter is symmetrically truncated;
let the preset filter be h [ i ]]The fundamental filter is hb[i]The window function is w [ i ]]And then:
Figure BDA0002076377710000125
h[i]＝hb[i]×w[i]，-L≤i≤L；
where p denotes the p nyquist zone of the analog signal at the TIADC of the TIADC system, and L denotes the length of the truncation which symmetrizes the base filter.
Due to the fact thatb[i]Cut off to h [ i ]]Limited length, truncation hb[i]The filter should be cut off symmetrically, that is, only the part where-L is not less than i not more than L, L is a positive integer, and finally the length of the preset filter is 2L + 1. If the truncation is not performed symmetrically, it will cause the preset filter to be distorted after multiplying with the TIADC waveform data, resulting in a decrease in the mismatch error correction performance.
The window function may be a hanning window, whose expression is:
Figure BDA0002076377710000131
the obtaining of the final modified analog signal data by adding the filtered waveform data multiplied by the corresponding reconstructed phase parameter to the TIADC waveform data comprises:
let TIADC waveform data be
Figure BDA0002076377710000132
The filtered waveform data is
Figure BDA0002076377710000133
The reconstructed phase parameter is t'mThe final modified analog signal has data of y [ n ]]Wherein n represents the serial number of the TIADC waveform data, M represents the number of sub-ADCs constituting the TIADC in the TIADC system, M represents each sub-ADC channel number, M is 0, 1.
Figure BDA0002076377710000134
The method illustrated in FIG. 1 is further described with reference to FIGS. 2, 3A, and 3B in conjunction with specific embodiments.
FIG. 2 schematically shows a schematic diagram of steps S3-S4 in a TIADC mismatch error calibration method according to an embodiment of the disclosure.
In principle, the calculation method for eliminating the dc offset mismatch error and the gain mismatch error for the signal data sampled by each sub ADC is as follows:
let the signal data of each sub ADC channel be am[k]The signal data of each sub ADC channel corresponds to correction data bm[k]，
Figure BDA0002076377710000135
Wherein, M represents the number of sub-ADCs composing the TIADC in the TIADC system, M represents each sub-ADC channel number, and M is 0, 1.
However, there are problems with using a DSP to do the calculations in this manner in an FPGA. In the FPGA produced by mainstream manufacturers, the structure of the DSP includes a pre-adder, a multiplier, and an adder, in the data flow direction, the calculation result of the pre-adder is sent to the multiplier for multiplication, and the result of the multiplication is sent to the adder for addition or subtraction, so that the bit width of the input data of the pre-adder is limited by the bit width of the input data of the multiplier, which is much smaller than the bit width of the input data of the adder. The calculation method for correcting the dc offset mismatch error and the gain mismatch error needs to use a pre-adder and a multiplier in the DSP, which easily results in that the calculation cannot be realized due to the bit width limitation of the pre-adder.
For example, let am[k]Is an integer of 12 bits, omThe decimal fraction is a decimal fraction of an integer part of 3 bits and a decimal part of 10 bits, and the decimal fraction participates in addition calculation in the form of fixed point number in the FPGA, the input data bit width of the pre-adder is required to be at least 22 bits, and the requirement cannot be met even by high-end FPGAs produced by mainstream manufacturers, such as FPGAs of the Altera Stratix5 series.
In order to solve the problem, the more reasonable method is to change the calculation form and convert the calculation mode into the multiply-add calculation, so that the calculation capability of the DSP can be fully utilized, and the portability of the correction method between the FPGAs is improved.
Therefore, in this embodiment, the correction of the dc offset mismatch error and the gain mismatch error is performed by using a multiply-add calculation, that is, a multiply-add unit in a calculation form of "P ═ a × B + C" is used to correct the dc offset mismatch error and the gain mismatch error, the multiplier in the DSP is used to perform the multiplication calculation first, and then the adder in the DSP is used to perform the addition calculation.
Specifically, in this embodiment, the calculation form for eliminating the dc offset mismatch error and the gain mismatch error for the signal data sampled by each sub-ADC is modified as follows:
bm[k]＝αm[k]×g′m+o′m；
wherein, g'mTo reconstruct the gain parameter, o'mTo reconstruct the dc parameters.
The calculation is performed in a multiplier-adder in the form of "P ═ a × B + C", and in the FPGA the data are all involved in the calculation in the form of binary fixed-point numbers of "1 bit sign bit + N1bit integer bit + N2bit decimal bit", let a bem[k]Is an integer of "1 +11+0 ═ 12 bit", g'mIs a decimal, o 'of "1 +1+10 ═ 12 bit'mIs a fraction of "1 +12+10 ═ 23 bit", which requires the adder to have an input data bit width of at least 23bit, but this requirement is easily met for the adder because the adder in the DSP allows a much wider input data bit width than the pre-adder allows.
In the method illustrated in fig. 1, the calculation of the convolution of the TIADC waveform data with a filter and the calculation of the finally corrected analog signal data also use the form of "a × B + C" calculation, and the formula is as follows:
Figure BDA0002076377710000151
Figure BDA0002076377710000152
according to the calibration method proposed by Han Le Duc et al,
Figure BDA0002076377710000153
and t0，t1，…，tM-1Multiplying in turn to obtain a pseudo-aliasing signal
Figure BDA0002076377710000154
Subtracting the pseudo aliasing signal to obtain a corrected waveform y [ n ]]The concrete formula is as follows:
Figure BDA0002076377710000155
to accomplish this, a multiplier-adder with the function "P-C-a × B" needs to be used, and to implement such a multiplier-adder with a DSP, higher demands are made on the diversity of DSP functions.
To reduce the requirement of the multiplier-adder implementation on DSP functional diversity and unify the multiplier-adder for use in the rest of the computations, let t 'in the embodiment of the present disclosure'm＝-tmThen the above calculation may be changed to:
Figure BDA0002076377710000156
this part of the calculation can then be done using a multiplier-adder with the function "P ═ a × B + C", which corresponds to
Figure BDA0002076377710000157
A negative pseudo-aliasing signal is added. "generation of negative pseudo-aliasing signal,
Figure BDA0002076377710000158
The two parts of calculation of adding the negative pseudo aliasing signals are completed by using the multiplier-adder together, so that DSP resources can be effectively saved.
Therefore, the present embodiment realizes unification of calculation forms for correcting the TIADC mismatch error, and each calculation form can be realized by using a multiplier-adder with a function of "P ═ a × B + C", which provides possibility for time division multiplexing of the DSP by the calculation unit.
Specifically, when step S3 and step S4 are executed, the calculation formula using the calculation form of "P ═ a × B + C" is sequentially executed, so that all correction calculations can be completed by time division multiplexing using the same multiplier-adder having the function of "P ═ a × B + C", thereby reducing the consumption of DSP resources in the FPGA.
Fig. 3A schematically illustrates a filter structure used for the filtering process in step S4 in the TIADC mismatch error calibration method according to an embodiment of the disclosure.
FIG. 3B is a schematic diagram of another filter structure used for filtering in the digital calibration method for TIADC mismatch errors;
among them, fig. 3A and 3B focus on highlighting the structure of the filter, omitting the data buffering in the actual calculation process, which is a conventional representation method in the signal processing field.
In FIG. 3B, filter h [ n ]]Is divided into 2 polyphase filters, and the filtering results of the 2 polyphase filters need to be added to obtain the result
Figure BDA0002076377710000161
This 1 addition calculation means the consumption of 1 DSP in the FPGA. In fig. 3A, a filtering structure of a conventional tapped delay line filter is employed. Thus, the architecture of FIG. 3A consumes 1 less DSP than the architecture of FIG. 3B. FIG. 3B shows a digital calibration method for TIADC mismatch error, if filter h [ n [ ] is used]Dividing into a larger number of polyphase filters would consume a larger number of DSPs than the filtering architecture illustrated in fig. 3A. Therefore, the filtering structure shown in fig. 3A used in the embodiment of the present disclosure saves DSP resources in the FPGA even more.
The embodiment of the present disclosure adopts at least one technical scheme that can achieve the following beneficial effects:
the invention provides a TIADC mismatch error calibration method, a TIADC mismatch error calibration device, TIADC mismatch error calibration equipment and TIADC mismatch error calibration media, wherein the TIADC mismatch error, the TIADC mismatch error and the TIADC mismatch error are estimated, and signals input into the TIADC system are corrected according to the TIADC mismatch error, the TIADC mismatch error and the TIADC mismatch error. The calculation forms of the correction method are calculation sequences of performing multiplication calculation and then performing addition calculation, bit widths of a DSP adder and a multiplier in an FPGA in a TIADC system can be effectively utilized, and due to the unification of the calculation forms, the correction method can be realized by using a multiplier-adder in the calculation form of 'P ═ A × B + C', so that the consumption of DSP resources is reduced, and meanwhile, the requirement on the functional diversity of the DSP is reduced. In addition, because the direct-current bias mismatch error, the gain mismatch error and the clock phase mismatch error of each sub-ADC only need to be estimated once, the estimation of the mismatch error can be implemented in an off-line manner, and the consumption of DSP resources in the FPGA is further reduced.
Fig. 4 schematically illustrates a block diagram of a detection system for a terminal provided according to an embodiment of the present disclosure;
as shown in fig. 4, the system 400 includes: a first processing module 410, a second processing module 420, a third processing module 430, and a fourth processing module 440. The terminal 400 may perform the method as described in fig. 3.
Specifically, the first processing module 410 is configured to calculate a dc offset mismatch error, a gain mismatch error, and a clock phase mismatch error that are generated when a standard sinusoidal signal is transmitted in each sub-ADC channel of the TIADC system;
the second processing module 420 is configured to calculate a reconstructed gain parameter and a reconstructed direct current parameter of each sub-ADC channel based on the dc offset mismatch error and the gain mismatch error;
a third processing module 430, configured to acquire signal data of each sub-ADC channel when an analog signal is input to the TIADC system, where the product of the signal data of each sub-ADC channel and a corresponding reconstruction gain parameter is added with a corresponding reconstruction direct-current parameter to obtain correction data corresponding to the signal data of each sub-ADC channel;
the fourth processing module 440 is configured to combine the correction data corresponding to the signal data of each sub-ADC channel to obtain TIADC waveform data, perform filtering processing on the TIADC waveform data to obtain filtered waveform data, and obtain data of a final corrected analog signal by adding a product of the filtered waveform data and a corresponding reconstructed phase parameter to the TIADC waveform data.
It is understood that the first processing module 41(), the second processing module 420, the third processing module 430, and the fourth processing module 440 may be combined and implemented in one module, or any one of them may be split into a plurality of modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of the other modules and implemented in one module. According to an embodiment of the present invention, at least one of the first processing module 410, the second processing module 420, the third processing module 430, and the fourth processing module 440 may be implemented at least in part as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented in hardware or firmware in any other reasonable manner of integrating or packaging a circuit, or in a suitable combination of software, hardware, and firmware implementations. Alternatively, at least one of the first processing module 410, the second processing module 420, the third processing module 430 and the fourth processing module 440 may be at least partially implemented as a computer program module, which, when executed by a computer, may perform the functions of the respective modules.
Fig. 5 schematically shows a block diagram of a terminal according to another embodiment of the present disclosure.
As shown in fig. 5, the terminal 500 includes a processor 510, a computer-readable storage medium 520. The terminal 500 may perform the method described above with reference to fig. 1 to enable detection of a specific operation.
In particular, processor 510 may include, for example, a general purpose microprocessor, an instruction set processor and/or related chip set and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), and/or the like. The processor 510 may also include on-board memory for caching purposes. Processor 510 may be a single processing unit or a plurality of processing units for performing the different actions of the method flows described with reference to fig. 1 in accordance with embodiments of the present disclosure.
Computer-readable storage medium 520 may be, for example, any medium that can contain, store, communicate, propagate, or transport the instructions. For example, a readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of the readable storage medium include: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); a memory, such as a Random Access Memory (RAM) or a flash memory; and/or wired/wireless communication links.
The computer-readable storage medium 520 may include a computer program 521, which computer program 521 may include code/computer-executable instructions that, when executed by the processor 510, cause the processor 510 to perform a method flow such as that described above in connection with fig. 1 and any variations thereof.
The computer program 521 may be configured with, for example, computer program code comprising computer program modules. For example, in an example embodiment, code in computer program 521 may include one or more program modules, including for example 521A, modules 521B, … …. It should be noted that the division and number of modules are not fixed, and those skilled in the art may use suitable program modules or program module combinations according to actual situations, which when executed by the processor 510, enable the processor 510 to perform the method flow described above in connection with fig. 1 and any variations thereof, for example.
According to an embodiment of the present invention, at least one of the first processing module 410, the second processing module 420, the third processing module 430, and the fourth processing module 440 may be implemented as a computer program module described with reference to fig. 5, which, when executed by the processor 510, may implement the respective operations described above.
The present disclosure also provides a computer-readable medium, which may be embodied in the apparatus/device/system described in the above embodiments; or may exist separately and not be assembled into the device/apparatus/system. The computer readable medium carries one or more programs which, when executed, implement the method according to an embodiment of the disclosure.
According to embodiments of the present disclosure, a computer readable medium may be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer-readable signal medium may include a propagated data signal with computer-readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, optical fiber cable, radio frequency signals, etc., or any suitable combination of the foregoing.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.
While the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined not only by the appended claims, but also by equivalents thereof.

Claims (8)

1. A TIADC system mismatch error calibration method is characterized by comprising the following steps:
s1, calculating a direct current offset mismatch error, a gain mismatch error and a clock phase mismatch error generated when a standard sine signal is transmitted and sampled in each sub-ADC channel of the TIADC system;
s2, calculating the reconstruction gain parameter, the reconstruction direct current parameter and the reconstruction phase parameter of each sub ADC channel based on the direct current bias mismatch error, the gain mismatch error and the clock phase mismatch error;
s3, when analog signals are input into the TIADC system, acquiring signal data of each sub-ADC channel, wherein the correction data corresponding to the signal data of each sub-ADC channel is obtained by adding the corresponding reconstruction direct current parameter to the product of the signal data of each sub-ADC channel and the corresponding reconstruction gain parameter;
let the signal data of each sub ADC channel be am[k]The corresponding correction data of the signal data of each sub ADC channel is bm[k]The reconstructed gain parameter is g'mThe reconstructed direct current parameter is o'mWherein m represents each sub-ADC channel number, k represents a sampling data serial number, then:
bm[k]＝am[k]×g′m+o′m；
s4, splicing the corresponding correction data of the signal data of each sub-ADC channel to obtain TIADC waveform data, and filtering the TIADC waveform data to obtain filtered waveform data;
performing convolution calculation on the TIADC waveform data and a preset filter to obtain the filtering waveform data;
let the TIADC waveform data be
Figure FDA0002683945810000011
The preset filter is h [ n ]]The corresponding correction data of the signal data of each sub ADC channel is bm[k]The filter waveform data is
Figure FDA0002683945810000012
Then:
Figure FDA0002683945810000013
Figure FDA0002683945810000014
wherein n represents a serial number of TIADC waveform data obtained by combining correction data corresponding to the signal data of each sub-ADC channel, M represents the number of sub-ADCs constituting the TIADC in the TIADC system, M represents the number of each sub-ADC channel, M is 0, 1, M-1, k represents a sampling data serial number, n is Mk + M, i represents a data serial number of the preset filter, and L represents a positive integer;
and adding the product of the filtering waveform data and the corresponding reconstruction phase parameter to the TIADC waveform data to obtain the finally corrected data of the analog signal.
2. The method of claim 1, wherein the calculating the reconstructed gain parameter, the reconstructed dc parameter, and the reconstructed phase parameter for each sub-ADC channel based on the dc offset mismatch error and the gain mismatch error comprises:
respectively setting the DC bias mismatch error, the gain mismatch error and the clock phase mismatch error of each sub ADC channel as om、gmAnd tmThe reconstructed gain parameter, the reconstructed direct current parameter and the reconstructed phase parameter are g 'respectively'm、o′mAnd t'mWherein m represents the number of each sub-ADC channel, then:
Figure FDA0002683945810000021
Figure FDA0002683945810000022
t′m＝-tm。
3. the method of claim 1, wherein convolving the TIADC waveform data with a preset filter comprises:
the preset filter consists of a basic filter and a window function;
wherein the base filter is symmetrically truncated;
let the preset filter be h [ i ]]The basic filter is hb[i]The window function is w [ i ]]And then:
Figure FDA0002683945810000023
h[i]＝hb[i]×w[i]，-L≤i≤L；
where p denotes the p nyquist zone of the analog signal at the TIADC of the TIADC system, and L denotes the length of the truncation which symmetrizes the base filter.
4. The method of claim 1, wherein the TIADC waveform data plus the product of the filtered waveform data and the corresponding reconstructed phase parameter to obtain final modified analog signal data comprises:
let the TIADC waveform data be
Figure FDA0002683945810000031
The filter waveform data is
Figure FDA0002683945810000032
The reconstruction phase parameter is t'mThe finally corrected data of the analog signal is y [ n ]]Wherein n denotes a serial number of the TIADC waveform data, M denotes the number of sub-ADCs constituting the TIADC in the TIADC system, M denotes a channel number of each sub-ADC, M is 0, 1.
Figure FDA0002683945810000033
5. The method of claim 1, wherein calculating dc offset mismatch error, gain mismatch error, and clock phase mismatch error of a standard sinusoidal signal transmitted in each sub-ADC channel of the TIADC system comprises:
s11, inputting a standard sine signal into the TIADC system, and sampling the signal data of each sub-ADC channel;
s12, fitting the signals of the sub ADC channels respectively based on the signal data to obtain the amplitude, the phase and the direct current offset of the signals of the sub ADC channels;
s13, respectively carrying out direct current offset elimination and gain normalization processing on the signal data of each sub ADC channel;
s14, splicing the data processed in the step S13 to obtain TIADC waveform data;
s15, processing the TIADC waveform data to obtain the frequency of the standard sinusoidal signal shifted to the frequency of the first Nyquist zone of the TIADC system;
s16, calculating the actual frequency of the standard sinusoidal signal based on the frequency of the standard sinusoidal signal in the first Nyquist zone of the TIADC system;
s17, correspondingly adjusting the phase of the signal of each sub-ADC channel based on the actual frequency of the standard sinusoidal signal and the sampling rate of each sub-ADC channel to obtain the actual phase of the signal of each sub-ADC channel;
s18, respectively calculating gain mismatch errors and direct current offset mismatch errors of the sub ADC channels based on the amplitude and the direct current offset of the signal of each sub ADC channel; calculating the clock phase mismatch error of each sub-ADC channel based on the actual phase of the signal of each sub-ADC channel.
6. A TIADC system mismatch error calibration apparatus, comprising:
the first processing module is used for calculating a direct current offset mismatch error, a gain mismatch error and a clock phase mismatch error generated when a standard sinusoidal signal is transmitted in each sub-ADC channel of the TIADC system;
the second processing module is used for calculating a reconstruction gain parameter, a reconstruction direct current parameter and a reconstruction phase parameter of each sub ADC channel based on the direct current offset mismatch error and the gain mismatch error;
the third processing module is used for acquiring the signal data of each sub-ADC channel when an analog signal is input into the TIADC system, wherein the product of the signal data of each sub-ADC channel and the corresponding reconstruction gain parameter is added with the corresponding reconstruction direct current parameter to obtain the corresponding correction data of the signal data of each sub-ADC channel;
let the signal data of each sub ADC channel be am[k]The corresponding correction data of the signal data of each sub ADC channel is bm[k]The reconstructed gain parameter is g'mThe reconstructed direct current parameter is o'mWherein m represents each sub-ADC channel number, k represents a sampling data serial number, then:
bm[k]＝am[k]×g′m+o′m；
the fourth processing module is used for splicing the correction data corresponding to the signal data of each sub-ADC channel to obtain TIADC waveform data, and filtering the TIADC waveform data to obtain filtered waveform data;
performing convolution calculation on the TIADC waveform data and a preset filter to obtain the filtering waveform data;
let the TIADC waveform data be
Figure FDA0002683945810000041
The preset filter is h [ n ]]The corresponding correction data of the signal data of each sub ADC channel is bm[k]The filter waveform data is
Figure FDA0002683945810000042
Then:
Figure FDA0002683945810000051
Figure FDA0002683945810000052
wherein n represents a serial number of TIADC waveform data obtained by combining correction data corresponding to the signal data of each sub-ADC channel, M represents the number of sub-ADCs constituting the TIADC in the TIADC system, M represents the number of each sub-ADC channel, M is 0, 1, M-1, k represents a sampling data serial number, n is Mk + M, i represents a data serial number of the preset filter, and L represents a positive integer;
and adding the product of the filtering waveform data and the corresponding reconstruction phase parameter to the TIADC waveform data to obtain the finally corrected data of the analog signal.
7. An electronic device, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor, when executing the computer program, performs the steps of the TIADC system mismatch error calibration method of any of claims 1 to 5.
8. A computer-readable storage medium, having stored thereon a computer program, wherein the computer program, when executed by a processor, performs the steps of the TIADC system mismatch error calibration method of any of claims 1 to 5.
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