CN110265082A - The method for deleting and semiconductor storage unit of semiconductor storage unit - Google Patents
The method for deleting and semiconductor storage unit of semiconductor storage unit Download PDFInfo
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- CN110265082A CN110265082A CN201910412647.8A CN201910412647A CN110265082A CN 110265082 A CN110265082 A CN 110265082A CN 201910412647 A CN201910412647 A CN 201910412647A CN 110265082 A CN110265082 A CN 110265082A
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- storage unit
- semiconductor storage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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Abstract
The embodiment of the present application discloses the method for deleting and semiconductor storage unit of a kind of semiconductor storage unit, wherein the described method includes: carry out pre-programmed processing to the semiconductor storage unit, obtains pre-programmed treated semiconductor storage unit；Wherein, the non-programmed region of the accumulation layer of the pre-programmed treated semiconductor storage unit has a charge of the first concentration, and the program regions of the accumulation layer of the pre-programmed treated semiconductor storage unit have the charge of the second concentration；To the pre-programmed treated semiconductor storage unit carries out erasing processing, erasing is formed treated semiconductor storage unit；Wherein, the non-programmed region of the accumulation layer of erasing treated the semiconductor storage unit has the charge of first concentration；First concentration is less than or equal to second concentration.
Description
Technical field
The invention relates to semiconductor storage unit fields, relate to, but are not limited to a kind of wiping of semiconductor storage unit
Except method and semiconductor storage unit.
Background technique
3D NAND flash memory device since memory capacity is big, it is at low cost the features such as, thus obtained in memory area wide
General application.
In the related technology, it for the programming of the semiconductor storage units such as 3D NAND flash memory device, is usually deposited in semiconductor
Apply high program voltage in the wordline (Word Line, WL) of memory device, electronics is formed by forceful electric power field action in program voltage
Under, it is tunneling to the accumulation layer of semiconductor storage unit by channel, and captured by accumulation layer trap, makes the threshold of semiconductor storage unit
Threshold voltage increases, to realize the programming to semiconductor storage unit.
But the programmed method of the relevant technologies, it will usually after forming interlayer coupled interference and programming between adjacent WL
Charge laterally be lost, to cause the threshold voltage shift of semiconductor storage unit, influence the global storage performance of device.
Summary of the invention
In view of this, the embodiment of the present application provides the method for deleting and semiconductor memory of a kind of semiconductor storage unit
Part.
The technical solution of the embodiment of the present application is achieved in that
In a first aspect, the embodiment of the present application provides a kind of method for deleting of semiconductor storage unit, which comprises
Pre-programmed processing is carried out to the semiconductor storage unit, obtains pre-programmed treated semiconductor storage unit；
Wherein, the non-programmed region of the accumulation layer of the pre-programmed treated semiconductor storage unit has the charge of the first concentration,
And the program regions of the accumulation layer of the pre-programmed treated semiconductor storage unit have the charge of the second concentration；
To the pre-programmed treated semiconductor storage unit carries out erasing processing, erasing is formed treated semiconductor
Memory device；Wherein, the non-programmed region of the accumulation layer of erasing treated the semiconductor storage unit has described first
The charge of concentration；
First concentration is less than or equal to second concentration.
In other embodiments, described that pre-programmed processing is carried out to the semiconductor storage unit, obtain pre-programmed processing
Semiconductor storage unit afterwards, comprising:
Pre-programmed voltage is applied simultaneously at least two WL of the semiconductor storage unit, is carried out at the pre-programmed
Reason obtains the pre-programmed treated semiconductor storage unit.
It is in other embodiments, described that the pre-programmed, treated that semiconductor storage unit carries out erasing processing, shape
At erasing treated semiconductor storage unit, comprising:
First erasing voltage is applied to the pre-programmed treated semiconductor storage unit, to wipe second concentration
Charge, form erasing treated the semiconductor storage unit.
In other embodiments, it to the pre-programmed, treated that semiconductor storage unit carries out erasing processing, is formed
After erasing treated semiconductor storage unit, the method also includes:
Based on targets threshold, to the erasing, treated that semiconductor storage unit carries out erasing verifying；
If the erasing is verified, terminate the processing of the erasing to the semiconductor storage unit.
In other embodiments, the method also includes:
If the erasing verifying does not pass through, adjusting first erasing voltage is the second erasing voltage, by described
Second erasing voltage carries out the pre-programmed semiconductor storage unit to repeat erasing processing.
In other embodiments, at least two WL to the semiconductor storage unit apply pre-programmed electricity simultaneously
Pressure, carries out the pre-programmed processing, obtains the pre-programmed treated semiconductor storage unit, comprising:
The pre-programmed voltage is inputted simultaneously at least two WL of the semiconductor storage unit, described is partly led with realizing
Electronics in the polysilicon layer of body memory part is under the electric field action of the pre-programmed voltage, by tunnelling to the semiconductor
The program regions of the accumulation layer of memory device input the charge of the second concentration, act in the fringe field of the pre-programmed voltage
Under, the charge of the first concentration is inputted to the non-programmed region of the accumulation layer of the semiconductor storage unit by tunnelling.
In other embodiments, every WL is corresponding with a program regions of the accumulation layer of the semiconductor storage unit,
And the dimensional parameters of every WL are equal with the dimensional parameters of corresponding program regions.
Second aspect, the embodiment of the present application provide a kind of semiconductor storage unit, and the semiconductor storage unit includes:
Polysilicon layer；
Tunnel layer on the polysilicon layer；
Accumulation layer on the tunnel layer；Wherein, the accumulation layer includes at least two program regions and at least
Two non-programmed regions, and each non-programmed region has the charge of the first concentration；
Barrier layer on the accumulation layer；
At least two WL on the barrier layer.
In other embodiments, every WL is corresponding with a program regions of the accumulation layer of the semiconductor storage unit,
The dimensional parameters of every WL are equal with the dimensional parameters of corresponding program regions.
The method for deleting and semiconductor storage unit of semiconductor storage unit provided by the embodiments of the present application, due to right first
The semiconductor storage unit carries out pre-programmed processing, pre-programmed is obtained treated semiconductor storage unit, then to described
Pre-programmed treated semiconductor storage unit carries out erasing processing forms erasing treated semiconductor storage unit.In this way,
The electricity with the first concentration can be formed in the non-programmed region of the accumulation layer of erasing treated the semiconductor storage unit
Lotus reduces the layer coupling interference between adjacent WL and the charge after programming is horizontal to guarantee in subsequent programmed process
To loss, the threshold voltage shift of semiconductor storage unit is reduced, improves the global storage performance of semiconductor storage unit.
Detailed description of the invention
In attached drawing (it is not necessarily drawn to scale), similar appended drawing reference can describe phase in different views
As component.Similar reference numerals with different letter suffix can indicate the different examples of similar component.Attached drawing with example and
Unrestricted mode generally shows each embodiment discussed herein.
Figure 1A is the implementation process schematic diagram of programmed method in the related technology；
Figure 1B is formed by a kind of defect schematic diagram for programmed method in the related technology；
Fig. 1 C is formed by another defect schematic diagram for programmed method in the related technology；
Fig. 2 is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application one；
Fig. 3 A is the structural schematic diagram of semiconductor storage unit provided by the embodiment of the present application；
Fig. 3 B is the realization of pre-programmed processing in the method for deleting of semiconductor storage unit provided by the embodiment of the present application
Flow diagram；
Fig. 3 C wipes the realization stream of processing in the method for deleting for semiconductor storage unit provided by the embodiment of the present application
Journey schematic diagram；
Fig. 4 is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application two；
Fig. 5 is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application three；
Fig. 6 A is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application；
Fig. 6 B is the structural schematic diagram of semiconductor storage unit provided by the embodiment of the present application；
Fig. 6 C is the implementation process schematic diagram of the processing of pre-programmed provided by the embodiment of the present application；
Fig. 6 D is the implementation process schematic diagram of erasing processing provided by the embodiment of the present application；
Fig. 7 is the structural schematic diagram of semiconductor storage unit provided by the embodiment of the present application.
Specific embodiment
To keep the technical solution and advantage of the embodiment of the present application clearer, below in conjunction with attached in the embodiment of the present application
Figure, is described in further detail the specific technical solution of invention.Following embodiment is not limited to for illustrating the application
Scope of the present application.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.In general, term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or device
The step of may also including other or element.
When the embodiment of the present application is described in detail, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the range of the application protection herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Feature and second feature are formed as the embodiment directly contacted, also may include that other feature is formed in fisrt feature and second
Embodiment between feature, such fisrt feature and second feature may not be direct contact.
In the related technology, for the programming of semiconductor storage unit, usually apply on the WL of semiconductor storage unit
High program voltage, electronics are tunneling to the accumulation layer of device by channel in the case where program voltage is formed by forceful electric power field action, and by
The capture of accumulation layer trap, so that the threshold voltage of program regions increases, programming terminates.It as shown in Figure 1A, is in the related technology
The implementation process schematic diagram of programmed method, program voltage V is applied on the WL 10 of semiconductor storage unit, and charge 130 is in V
It is formed by under forceful electric power field action, tunnel layer 12 is passed through by polysilicon layer 11, then tunnelling, to the storage of semiconductor storage unit
Layer 13 is captured by the trap in accumulation layer 13, wherein has barrier layer 14 between accumulation layer 13 and WL 10.
But there is following both sides in the programmed method of the relevant technologies:
In a first aspect, as shown in Figure 1B, when carrying out normal program to semiconductor storage unit, being applied when to corresponding WL 10
When making alive, WLnAfter the completion of (n-th of WL) programming, start WLn+1Programming.And WLn+1It can be because of the program voltage applied when programming
Fringe field, make WLnWith WLn+1Between the non-programmed region of the corresponding accumulation layer in region be programmed out a small amount of edge charges
101, this part edge charge 101 will cause WL againnThreshold voltage shift, i.e. WLn+1To WL when programmingnLayer coupling it is dry
It disturbs.
Second aspect, as shown in Figure 1 C, the accumulation layer when carrying out normal program to semiconductor storage unit, immediately below WL
Area charge concentration highest, WLnWith WLn+1Between accumulation layer non-programmed area charge concentration it is minimum, then immediately below WL
The charges of the program regions of accumulation layer can be because of concentration gradient, and to the non-programmed regional diffusion on the both sides (arrow 131 in such as figure
Direction, be charge dispersal direction), cause WLnThreshold voltage shift.
In the related technology, since charge when forming interlayer coupled interference and programming between adjacent WL is laterally lost,
To will cause the threshold voltage shift of program regions, the global storage performance of device is influenced.
Based on the above problem present in programmed method in the related technology, the embodiment of the present application provides a kind of semiconductor and deposits
The method for deleting of memory device has the non-programmed region of accumulation layer by adding pre-programmed treatment process before erasing operation
There is a certain amount of charge, in this way, can reduce formation interlayer coupled interference between adjacent WL during subsequent normal program
And the charge after programming is laterally lost, to reduce the threshold voltage shift of semiconductor storage unit, improves semiconductor storage
The global storage performance of device.
Fig. 2 is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application one,
As shown in Fig. 2, the described method comprises the following steps:
Step S201 carries out pre-programmed processing to semiconductor storage unit, obtains pre-programmed treated semiconductor storage
Device.
Here, the semiconductor storage unit can be any one nonvolatile semiconductor memory member, for example, the semiconductor
Memory device can be 3D NAND flash memory device.The semiconductor storage unit can will program number by applying program voltage
According to the accumulation layer for being programmed into the semiconductor storage unit, the storage of data is realized.Fig. 3 A is provided by the embodiment of the present application
The structural schematic diagram of semiconductor storage unit, as shown in Figure 3A, the semiconductor storage unit include polysilicon layer 31, positioned at more
Tunnel layer 32 on crystal silicon layer 31, the accumulation layer 33 on tunnel layer 32, the barrier layer 34 on accumulation layer 33
With at least two WL 35 being located on barrier layer 34.
In the present embodiment, the non-programmed region of the accumulation layer of the pre-programmed treated semiconductor storage unit has the
The charge of one concentration, and the program regions of the accumulation layer of the pre-programmed treated semiconductor storage unit have the second concentration
Charge.Wherein, the program regions refer to immediately below every WL, and the region being located in the accumulation layer；It is described non-
Program regions refer to the underface in the region between every two adjacent WL, and the region being located in the accumulation layer.
In the present embodiment, first concentration is less than or equal to second concentration, also, multiple volumes in the accumulation layer
The concentration difference of the charge between any two program regions in journey region is less than or equal to preset threshold, more in the accumulation layer
The concentration difference of the charge between any two non-programmed region in a non-programmed region is again smaller than equal to the preset threshold.
In one embodiment of the application, the pre-programmed treatment process can be realized by following steps:
Step S2011 applies pre-programmed voltage at least two WL of the semiconductor storage unit, described in progress simultaneously
Pre-programmed processing obtains the pre-programmed treated semiconductor storage unit.
It as shown in Figure 3B, is pre-programmed processing in the method for deleting of semiconductor storage unit provided by the embodiment of the present application
Implementation process schematic diagram.Pre-programmed voltage V is applied simultaneously at least two WL 35 of the semiconductor storage unitpgmIt
Afterwards.
Here, the pre-programmed voltage can be Vpgm, the pre-programmed voltage can be identical as the voltage of programmed process,
It can also be different.The pre-programmed voltage usually can be set higher than program voltage.By to semiconductor storage unit at least
Two WL apply pre-programmed voltage simultaneously, in this way, the program regions 331 of the accumulation layer 33 below WL can generate a large amount of electricity
Lotus, also, the effect of the fringe field 301 due to being respectively formed between n-th of WL and (n+1)th WL, can fringe field it
Under the non-programmed region 332 of accumulation layer 33 also generate a large amount of charge, wherein the charge in the non-programmed region 332 it is dense
Degree is the first concentration.
It should be noted that the present embodiment is formed by the charge of the first concentration in non-programmed region, relative to related skill
It is higher in the concentration that non-programmed region is formed by charge in art in normal program, it is because being pair in pre-programmed processing
At least two WL apply pre-programmed voltage V simultaneouslypgm.In this way, since n-th of WL forms fringe field, and (n+1)th WL simultaneously
Also it will form fringe field, therefore, the preprogramming process of the present embodiment, the electric-field strength of the fringe field on non-programmed region
Degree, can be in the related technology normal program when be formed by twice of fringe field.So pre- provided by the embodiment of the present application
Programmed process process can form the charge of higher first concentration of concentration in non-programmed region, and the value of first concentration can be with
Twice of the concentration of the charge formed when being equivalent to normal program in the related technology in non-programmed region.
Step S202 forms erasing processing to the pre-programmed treated semiconductor storage unit carries out erasing processing
Semiconductor storage unit afterwards.
Here, it is handled by the erasing, by the program regions of the accumulation layer of the pre-programmed semiconductor storage unit
The charge erasure of second concentration is fallen, so that the non-programmed region of the accumulation layer of erasing treated the semiconductor storage unit
Charge with first concentration.
In one embodiment of the application, the erasing treatment process can be realized by following steps:
Step S2021 applies the first erasing voltage to the pre-programmed treated semiconductor storage unit, to wipe
It states the charge of the second concentration, forms the erasing treated semiconductor storage unit.
It as shown in Figure 3 C, is erasing processing in the method for deleting of semiconductor storage unit provided by the embodiment of the present application
Implementation process schematic diagram.After at least two WL to the semiconductor storage unit apply pre-programmed voltage simultaneously, to institute
It states pre-programmed treated that semiconductor storage unit applies the first erasing voltage, to wipe the charge of second concentration, formed
Erasing treated the semiconductor storage unit.
Here, by applying the first erasing voltage to pre-programmed treated semiconductor storage unit, in this way, can be more
Crystal silicon layer 31 forms a large amount of hole, and hole enters accumulation layer 33 by tunnel layer 32, with stored electricity in accumulation layer 33
Lotus combines, to reduce the charge of the program regions 331 of accumulation layer 33, retains the charge in non-programmed region 332, formation only exists
Retain erasing treated the semiconductor storage unit 300 of the charge of the first concentration in non-programmed region 332.
In the present embodiment, when to the pre-programmed treated semiconductor storage unit carries out erasing processing, it can adopt
Erasing processing is carried out with any one erasing mode.
The method for deleting of semiconductor storage unit provided by the embodiments of the present application, it is pre- due to being carried out to semiconductor storage unit
Programmed process forms pre-programmed treated semiconductor storage unit, to the pre-programmed treated semiconductor memory
Part carries out erasing processing.In this way, can make the non-programmed region of erasing treated the semiconductor storage unit has first
The charge of concentration, to guarantee in subsequent programmed process, after reducing layer coupling interference and the programming between adjacent WL
Charge laterally be lost, reduce the threshold voltage shift of semiconductor storage unit, improve the global storage of semiconductor storage unit
Performance.
Fig. 4 is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application two,
As shown in figure 4, the described method comprises the following steps:
Step S401 applies pre-programmed voltage simultaneously at least two WL of semiconductor storage unit, prelists described in progress
Journey processing obtains the pre-programmed treated semiconductor storage unit.
Here, the non-programmed region of the accumulation layer of the pre-programmed treated semiconductor storage unit has the first concentration
Charge, and the program regions of the accumulation layer of the pre-programmed treated semiconductor storage unit have the electricity of the second concentration
Lotus.Also, the difference of first concentration and second concentration is less than or equal to preset threshold, in this manner it is ensured that described
The non-programmed region of the accumulation layer of semiconductor storage unit forms the charge of higher concentration, is formed by pre-programmed to realize
The concentration of the charge in the non-programmed region of the semiconductor storage unit after reason is higher.
Since the charge of first concentration is the charge to be retained, the charge of second concentration is the electricity to be wiped out
Lotus, therefore, it is necessary to the value of the first concentration, the higher the better.In the present embodiment, the value of the first concentration can be improved by two ways:
Mode one: adjusting the voltage value of pre-programmed voltage, when the voltage value of pre-programmed voltage is higher, in the non-programmed
Region can form the charge of higher concentration.
Mode two: first voltage is applied simultaneously to whole WL.In this way, since each WL has been applied pre-programmed electricity simultaneously
Pressure, thus between two adjacent WL, it will form higher fringe field, it, can be described under the action of high rim electric field
The charge of non-programmed region storage higher concentration.
Step S402 applies the first erasing voltage to the pre-programmed treated semiconductor storage unit, to wipe
It states the charge of the second concentration, forms the erasing treated semiconductor storage unit.
Here, when first erasing voltage is applied in the pre-programmed treated on semiconductor storage unit,
A large amount of hole can be formed in the polysilicon layer of the pre-programmed treated semiconductor storage unit, hole is through tunnel layer tunnelling
Into the charge bonded of program regions in accumulation layer, with accumulation layer, to wipe the charge of the program regions, and is formed and only existed
Retain erasing treated the semiconductor storage unit of the charge of the first concentration in non-programmed region.
Step S403 is based on targets threshold, and to erasing, treated that semiconductor storage unit carries out erasing verifying.
Here, to pre-programmed, treated after semiconductor storage unit carries out erasing processing, this erasing is handled
Process is verified, and can be verified in the following manner: judgement erasing treated semiconductor storage unit it is each non-
Whether the concentration of the charge of program regions reaches the targets threshold, alternatively, judgement erasing treated semiconductor storage unit
The concentration of charge in whole non-programmed regions whether reach the targets threshold.
In the present embodiment, the targets threshold can be set according to the performance requirement of actual process situation and device,
The present embodiment does not limit.
Step S404 terminates the processing of the erasing to the semiconductor storage unit if erasing is verified.
Here, if the concentration of the charge in each non-programmed region of erasing treated semiconductor storage unit reaches institute
Targets threshold is stated, alternatively, the concentration of the charge in whole non-programmed regions of erasing treated semiconductor storage unit reaches institute
Targets threshold is stated, then erasing is verified.
When the erasing is verified, shows that this erasing treatment process is met the requirements, then terminate to the semiconductor
The erasing of memory device is handled.
Step S405, if erasing verifying does not pass through, adjusting first erasing voltage is the second erasing voltage, is passed through
Second erasing voltage carries out the pre-programmed semiconductor storage unit to repeat erasing processing.
Here, if the concentration of the charge in each non-programmed region of erasing treated semiconductor storage unit is not up to
The targets threshold, alternatively, the concentration of the charge in whole non-programmed regions of erasing treated semiconductor storage unit does not reach
To the targets threshold, then wipes verifying and do not pass through.
When erasing verifying does not pass through, then carry out repeating erasing processing.
In the present embodiment, when carrying out repeating to wipe processing, the first erasing voltage is adjusted to the second erasing voltage first,
, can be according to erasing verifying as a result, determining the value of second erasing voltage during realization, second erasing is electric
The value of pressure is greater than the value of first erasing voltage.
When repeating erasing processing, apply second erasing to by erasing treated the semiconductor storage unit
Voltage forms to continue to wipe the charge of second concentration and repeats erasing treated semiconductor storage unit.
It should be noted that the method for deleting of semiconductor storage unit provided in this embodiment, in the primary erasing of every completion
It after process, is required to that treated that semiconductor storage unit carries out erasing verifying to erasing, if be not verified, needs
Erasing processing is repeated, until until wiping that treated semiconductor storage unit being verified.
The method for deleting of semiconductor storage unit provided by the embodiments of the present application, it is right first due to before erasing is handled
At least two WL of the semiconductor storage unit apply pre-programmed voltage simultaneously, carry out the pre-programmed processing, obtain described
Pre-programmed treated semiconductor storage unit, in this way, can be in the non-of the pre-programmed treated semiconductor storage unit
Program regions form the charge with the first concentration, to guarantee after erasing is handled, non-programmed region still has first dense
The charge of degree, so that in subsequent programmed process, after reducing layer coupling interference and the programming between adjacent WL
Charge is laterally lost, and is reduced the threshold voltage shift of semiconductor storage unit, is improved the global storage of semiconductor storage unit
Energy.In addition, due to carrying out erasing verifying to erasing processing, pre-programmed can be guaranteed in this way treated semiconductor memory
Part is effectively wiped, the erasing met the requirements treated semiconductor storage unit.
Fig. 5 is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application three,
As shown in figure 5, the described method comprises the following steps:
Step S501 inputs pre-programmed voltage simultaneously at least two WL of semiconductor storage unit, to realize semiconductor
Electronics in the polysilicon layer of memory device is under the electric field action of pre-programmed voltage, by tunnelling to semiconductor storage unit
The program regions of accumulation layer input the charge of the second concentration, under the fringe field effect of pre-programmed voltage, by tunnelling to partly
The non-programmed region of the accumulation layer of conductor memory inputs the charge of the first concentration, obtains pre-programmed treated that semiconductor is deposited
Memory device.
Here, every WL is corresponding with a program regions of the accumulation layer of the semiconductor storage unit, and every WL
Dimensional parameters are equal with the dimensional parameters of corresponding program regions.Wherein, the dimensional parameters can for cross-sectional area, diameter,
Any one parameter such as side length.
In one embodiment of the application, the cross-sectional area of every WL and the area equation of corresponding program regions, in this way, can
When guaranteeing through WL to program regions input charge, the charge of preset concentration is obtained in corresponding program regions.
Step S502 applies the first erasing voltage to pre-programmed treated semiconductor storage unit, dense with erasing second
The charge of degree forms erasing treated semiconductor storage unit.
It here, can be to described pre- by applying the first erasing voltage to pre-programmed treated semiconductor storage unit
The charge of second concentration of the program regions of the accumulation layer of the semiconductor storage unit after programmed process is wiped.
The method for deleting of semiconductor storage unit provided by the embodiments of the present application, at least to the semiconductor storage unit
Two WL input the pre-programmed voltage simultaneously, and the electronics in polysilicon layer to realize the semiconductor storage unit is described
Under the electric field action of pre-programmed voltage, second is inputted to the program regions of the accumulation layer of the semiconductor storage unit by tunnelling
The charge of concentration passes through tunnelling depositing to the semiconductor storage unit under the fringe field effect of the pre-programmed voltage
The non-programmed region of reservoir inputs the charge of the first concentration, obtains the pre-programmed treated semiconductor storage unit, in this way,
The charge with the first concentration can be formed in the non-programmed region of the pre-programmed treated semiconductor storage unit, thus
Guaranteeing after erasing is handled, non-programmed region still has the charge of the first concentration, so that in subsequent programmed process,
It reduces the layer coupling interference between adjacent WL and the charge after programming is laterally lost, reduce the threshold value of semiconductor storage unit
Voltage drift improves the global storage performance of semiconductor storage unit.
The embodiment of the present application provides a kind of method for deleting of semiconductor storage unit, before normal erasing, to entire half
All WL in conductor memory apply high pre-programmed voltage Vpgm, carry out whole pre-programmed.The then storage between WL and WL
Layer region (non-programmed region) can be programmed out a large amount of charges because of the high rim electric field on both sides.Then it is normally wiped,
Storage layer region after then wiping between WL and WL can then remain a part of charge.At this time if carrying out normal program again, deposit
In following advantages:
(1) reduce layer coupling interference；Because the storage layer region after erasing between WL and WL has remained quite
More charges, then WLn+1To WL when programmingnLayer coupling interference can die down.
(2) reduce charge to be laterally lost；The same storage layer region because of after erasing between WL and WL has remained phase
When more charges, then immediately below WL between the charge and WL and WL of accumulation layer (program regions) concentration of the charge of accumulation layer difference
It is different to become smaller, thus the charge of accumulation layer can also die down to both sides transverse direction loss immediately below WL.
Fig. 6 A is the implementation process schematic diagram of the method for deleting of semiconductor storage unit provided by the embodiment of the present application, such as
Shown in Fig. 6 A, it the described method comprises the following steps:
Step S601 carries out pre-programmed processing to semiconductor storage unit, obtains pre-programmed treated semiconductor storage
Device.
Here, before the pre-programmed processing for introducing the embodiment of the present application, a kind of semiconductor storage unit is provided first.Such as
It is the structural schematic diagram of semiconductor storage unit provided by the embodiment of the present application, the semiconductor storage unit shown in Fig. 6 B
Include:
Substrate 60, polysilicon layer 61, tunnel layer 62, accumulation layer 63, barrier layer 64, p-type trap 65, bit line 66 and grid,
In, the grid includes upper selecting pipe 671, the lower selecting pipe 672, upper redundancy for carrying out pre-programmed processing and erasing processing
Layer 673, lower redundant layer 674 and at least one WL 675 for storage.
Fig. 6 C is the implementation process schematic diagram of the processing of pre-programmed provided by the embodiment of the present application, as shown in Figure 6 C, pre-
When programmed process, all WL 675 in entire semiconductor storage unit are applied with high pre-programmed voltage V1, bit line 66 applies
0V voltage, upper selecting pipe 671 and lower selecting pipe 672 apply voltage V2 and V3 respectively, so that upper selecting pipe 671 and lower selecting pipe
672 open, and upper redundant layer 673 and lower redundant layer 674 apply voltage V4 and V5 respectively, and p-type trap 65 applies 0V voltage, to carry out
The pre-programmed treatment process of entire semiconductor storage unit obtains pre-programmed treated semiconductor storage unit.
After pre-programmed processing, storage layer region between WL and WL can because of adjacent both sides high rim electric field and by
Program out a large amount of charges.
Step S602, by applying erasing voltage to the pre-programmed treated semiconductor storage unit, (i.e. first is wiped
Except voltage), erasing processing is carried out, erasing treated semiconductor storage unit is obtained.
After completing pre-programmed processing, normal erasing processing is carried out, Fig. 6 D is erasing provided by the embodiment of the present application
The implementation process schematic diagram of processing, as shown in Figure 6 D, to the institute for needing to wipe in pre-programmed treated semiconductor storage unit
There is WL to apply 0V voltage, 66 floating of bit line, upper selecting pipe 671 and lower selecting pipe 672 apply voltage V6 and V7, upper redundant layer respectively
673 and lower redundant layer 674 apply voltage V8 and V9 respectively, p-type trap 65 applies erasing voltage V10, so that hole is entered accumulation layer, into
The erasing of the entire memory module of row.
After erasing processing, the storage layer region between WL and WL can then remain a part of charge, and remaining charge
The quantity of electric charge after amount is directly wiped than handling without pre-programmed is more.
Step S603, to the erasing, treated that semiconductor storage unit carries out erasing verifying.
Step S604, judges whether the charge in erasing treated the semiconductor storage unit reaches targets threshold.
Here, if it is judged that be it is yes, then terminate process；If it is judged that be it is no, then follow the steps S605.
Step S605 increases the erasing pulse voltage, and continues to execute step S602.
Here, increase the erasing pulse voltage to the second erasing voltage, continue to wipe by the second erasing voltage
Processing.
Based on above embodiments, the embodiment of the present application provides a kind of semiconductor storage unit, as shown in fig. 7, being the application
Structural schematic diagram (the knot in the region that wherein, Fig. 7 is drawn a circle to approve by dotted line in Fig. 6 B of semiconductor storage unit provided by embodiment
Structure schematic diagram), it should be noted that semiconductor storage unit provided by the embodiment of the present application is by any of the above-described embodiment
Method for deleting processing after obtained semiconductor storage unit, wherein the semiconductor storage unit 70 includes:
Polysilicon layer 71；
Tunnel layer 72 on the polysilicon layer 71；
Accumulation layer 73 on the tunnel layer 72；Wherein, wherein the accumulation layer 73 includes at least two programmings
Region 732 and at least two non-programmed regions 731, and each non-programmed region 731 has the charge 733 of the first concentration；
Barrier layer 74 on the accumulation layer 73；
WL 75 on the barrier layer 74.
In other embodiments, every WL is corresponding with a program regions of the accumulation layer of the semiconductor storage unit,
The dimensional parameters of every WL are equal with the dimensional parameters of corresponding program regions.
It should be noted that semiconductor storage unit provided by the embodiment of the present application corresponds to above-mentioned any one method reality
The erasing for applying in example treated semiconductor storage unit, that is to say, that the embodiment of the present invention semiconductor storage unit be through
Cross obtained semiconductor storage unit after the erasing in any one above-mentioned embodiment is handled.
Semiconductor storage unit provided by the embodiment of the present application, the non-programmed region of accumulation layer have the electricity of the first concentration
Lotus, in this way, it is subsequent the semiconductor storage unit is programmed when, due to accumulation layer non-programmed region have the first concentration
Charge, so as to reduce the layer coupling between adjacent WL interference and programming after charge laterally be lost, reduction partly lead
The threshold voltage shift of body memory part improves the global storage performance of semiconductor storage unit.
It should be understood by those skilled in the art that, the method for deleting of the semiconductor storage unit of the embodiment of the present application and partly leading
Body memory part other constitute and effect, be all for a person skilled in the art it is known, in order to reduce redundancy,
The embodiment of the present application does not repeat them here.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example " " specific example "
Or the description of " some examples " etc. means particular features, structures, materials, or characteristics packet described in conjunction with this embodiment or example
In at least one embodiment or example contained in the application.In the present specification, schematic expression of the above terms are not necessarily
Refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any one
It can be combined in any suitable manner in a or multiple embodiment or examples.
While there has been shown and described that embodiments herein, it will be understood by those skilled in the art that: not
A variety of change, modification, replacement and modification can be carried out to these embodiments in the case where being detached from the principle and objective of the application, this
The range of application is by claim and its equivalent limits.
Claims (9)
1. a kind of method for deleting of semiconductor storage unit, which is characterized in that the described method includes:
Pre-programmed processing is carried out to the semiconductor storage unit, obtains pre-programmed treated semiconductor storage unit；Wherein,
The non-programmed region of the accumulation layer of the pre-programmed treated semiconductor storage unit has the charge of the first concentration, and described
The program regions of the accumulation layer of pre-programmed treated semiconductor storage unit have the charge of the second concentration；
To the pre-programmed treated semiconductor storage unit carries out erasing processing, erasing is formed treated semiconductor storage
Device；Wherein, the non-programmed region of the accumulation layer of erasing treated the semiconductor storage unit has first concentration
Charge；
First concentration is less than or equal to second concentration.
2. method for deleting according to claim 1, which is characterized in that described to prelist to the semiconductor storage unit
Journey processing obtains pre-programmed treated semiconductor storage unit, comprising:
Pre-programmed voltage is applied simultaneously at least two wordline WL of the semiconductor storage unit, is carried out at the pre-programmed
Reason obtains the pre-programmed treated semiconductor storage unit.
3. method for deleting according to claim 2, which is characterized in that described to the pre-programmed, treated that semiconductor is deposited
Memory device carries out erasing processing, forms erasing treated semiconductor storage unit, comprising:
First erasing voltage is applied to the pre-programmed treated semiconductor storage unit, to wipe the electricity of second concentration
Lotus forms erasing treated the semiconductor storage unit.
4. method for deleting according to claim 3, which is characterized in that the pre-programmed treated semiconductor storage
Device carries out erasing processing, forms erasing treated after semiconductor storage unit, the method also includes:
Based on targets threshold, to the erasing, treated that semiconductor storage unit carries out erasing verifying；
If the erasing is verified, terminate the processing of the erasing to the semiconductor storage unit.
5. method for deleting according to claim 4, which is characterized in that the method also includes:
If the erasing verifying does not pass through, adjusting first erasing voltage is the second erasing voltage, passes through described second
Erasing voltage carries out the pre-programmed semiconductor storage unit to repeat erasing processing.
6. method for deleting according to claim 2, which is characterized in that described at least the two of the semiconductor storage unit
A WL applies pre-programmed voltage simultaneously, carries out the pre-programmed processing, obtains the pre-programmed treated semiconductor memory
Part, comprising:
The pre-programmed voltage is inputted simultaneously at least two WL of the semiconductor storage unit, to realize that the semiconductor is deposited
Electronics in the polysilicon layer of memory device is under the electric field action of the pre-programmed voltage, by tunnelling to the semiconductor storage
The program regions of the accumulation layer of device input the charge of the second concentration, under the fringe field effect of the pre-programmed voltage, lead to
Cross the charge that tunnelling inputs the first concentration to the non-programmed region of the accumulation layer of the semiconductor storage unit.
7. method for deleting according to claim 2, which is characterized in that the storage of every a WL and the semiconductor storage unit
One program regions of layer are corresponding, and the dimensional parameters of every WL are equal with the dimensional parameters of corresponding program regions.
8. a kind of semiconductor storage unit, which is characterized in that the semiconductor storage unit includes:
Polysilicon layer；
Tunnel layer on the polysilicon layer；
Accumulation layer on the tunnel layer；Wherein, the accumulation layer includes at least two program regions and at least two
Non-programmed region, and each non-programmed region has the charge of the first concentration；
Barrier layer on the accumulation layer；
At least two WL on the barrier layer.
9. semiconductor storage unit according to claim 8, which is characterized in that every WL and the semiconductor storage unit
Accumulation layer a program regions it is corresponding, the dimensional parameters of every WL are equal with the dimensional parameters of corresponding program regions.
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| CN105938725A (en) * | 2015-03-07 | 2016-09-14 | 爱思开海力士有限公司 | Data storage device and method of driving the same |
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| US7319615B1 (en) * | 2006-08-02 | 2008-01-15 | Spansion Llc | Ramp gate erase for dual bit flash memory |
| CN105938725A (en) * | 2015-03-07 | 2016-09-14 | 爱思开海力士有限公司 | Data storage device and method of driving the same |
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