CN110249425A - 用于跨电容耦合通道进行通信的设备 - Google Patents
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Abstract
示例电路包括基本上平行于基板(117)的第一板(610),从而在第一板(610)和基板(117)中间形成第一电容。第二板(620)基本上平行于基板(117)和第一板(610)。第一板(610)位于基板(117)和第二板(620)中间。第三板(615)基本上平行于基板(117),从而在第三板(615)和基板(117)中间形成第二电容。第四板(625)基本上平行于基板(117)和第三板(615)。第三板(615)位于基板(117)和第四板(625)中间。电感器(509)连接到第一板(610)和第三板(615),以与第一电容和第二电容组合形成LC放大器。
Description
技术领域
本申请总体涉及电子通信,并且更具体地涉及用于跨电容耦合通道进行通信的设备。
背景技术
电子通信系统通常需要将数据从在第一电压域中操作的第一电路传送到在第二电压域中操作的第二电路。在一些示例中,第一电压域可以是一百伏的量级,而第二电压域可以是一千伏的量级。可替代地,第一电压域可以比第二电压域高数千伏(或反之亦然)。电耦合两个电路可能导致信号和/或数据完整性的损失,并且在一些示例中,可能导致电路中的一个或多个的损坏。为了实现通信,可以使用例如光隔离、磁隔离、电容隔离等以隔离方式连接电路。
发明内容
示例电路包括基本上平行于基板的第一板,从而在第一板和基板中间形成第一电容。第二板基本上平行于基板和第一板。第一板位于基板和第二板中间。第三板基本上平行于基板,从而在第三板和基板中间形成第二电容。第四板基本上平行于基板和第三板。第三板位于基板和第四板中间。电感器连接到第一板和第三板以与第一电容和第二电容组合形成LC放大器。
附图说明
图1是经由两个键合线连接的第一管芯和第二管芯的等距视图。
图2是图1的第一叠堆的侧视图。
图3是图1和/或图2的第一叠堆的俯视图。
图4是图1的示例第一管芯、示例第二管芯和示例键合线的电路图。
图5是根据本说明书构造的图1和/或图4的示例第一管芯、示例第二管芯和示例键合线的电路图。
图6是图5的示例第一管芯、示例第二管芯、键合线和电感器的图示。
图7是示出用于跨图5和/或图6的电容耦合通道传输和/或驱动信号的实例方法的电路图。
图8是示出跨频谱的示例接收信号的幅度的幅度点图。
具体实施方式
附图并未按比例绘制。相反,为了阐明多个层和区域,可以在附图中扩大层的厚度。只要有可能,在整个附图和随附的书面描述中将使用相同的附图标记来表示相同或相似的部分。如在该专利中所使用的,任何部分(例如,层、膜、区或板)以任何方式定位在另一部分上(例如,定位在其上、位于其上、设置在其上或形成在其上等)的陈述是指参考部分与另一部分接触,或者参考部分在另一部分之上,其中一个或多个中间部分位于其间。任何部分与另一部分接触的陈述意味着两个部分之间没有中间部分。
信号的数字隔离是一种新兴技术。数字隔离的两个主要技术是变压器和隔离电容器。目前,隔离电容器方法需要大功率抽取来操作增强信号质量的放大器。本文公开的示例方法利用隔离电容器电路内的电感器来实现无源增益,其具有比现有有源放大方法低得多的功率要求。
在本文公开的示例中,隔离电路的初级侧和隔离电路的次级侧两者被调谐用于无源增益。在一些示例中,取决于电感器的所选择的(一个或多个)值,期望频率下的增益可以是衰减信号的三到四倍(或任何其他增益值),而不需要任何电流用于有源放大。将初级侧(例如,传输侧)和次级侧(例如,接收侧)两者调谐到同一频率提高了隔离系统的共模瞬态免疫(CMTI)和接地噪声瞬态免疫(GNTI)性能。在一些示例中,使用与传输侧和接收侧的调谐频率匹配的输入信号频率(例如,调制频率)进一步提高了隔离系统的共模瞬态免疫(CMTI)和接地噪声瞬态免疫(GNTI)性能。
图1是通信系统100的等距视图,该通信系统100包括经由两个键合线106、108连接的第一管芯102和第二管芯104。图1的示例等距视图使用1毫米(mm)的标度109。然而,可以附加地或替代的使用任何其他标度。在图1的示例中,第一示例管芯102包括第一叠堆110和第二叠堆115。第一示例管芯102包括第一基板117。在图1的示例中,第二示例管芯104包括第三叠堆120和第四叠堆125。第二示例管芯104包括第二基板127。
在图1的示例中,第一示例键合线106耦合第一叠堆110和第三叠堆120。在图1的示例中,第二示例键合线108耦合第二叠堆115和第四叠堆125。
在图1的示例中,第一示例管芯102表示图1的示例通信系统100的传输侧。第二示例管芯104表示图1的示例通信系统100的接收侧。在图1的示例中,通信系统100表示为经由键合线106、108从第一管芯102向第二管芯104通信的单向通信系统。然而,在一些示例中,可以实现双向通信系统。在此类示例中,可以使用附加键合线和/或叠堆来促进两个方向上的通信。
图2是图1的第一叠堆110的侧视图。结合图1的第一叠堆110描述图2的示例,但是图2的示例也适用于图1的第二叠堆115、第三叠堆120和第四叠堆125。在图2的示例中,叠堆110包括顶板205和底板210。底板210定位在顶板205和第一基板117(或第二基板127)中间。在图2的示例中,顶板205和底板210布置成基本上彼此平行。在图2的示例中,顶板205和底板210布置成基本上平行于基板117。如本文所使用的,当顶板205和底板210之间、顶板205和基板117之间,和/或底板210和基板之间的距离偏离平均距离不超过百分之二十时,板和基板基本上平行。
在顶板205和底板210之间产生第一电容215。在底板210和基板之间产生第二电容220。在图2的示例中,顶板105连接到键合线225(例如,第一键合线106、第二键合线108)。在本文公开的示例中,底板210接收输入电信号。
在图2的示例中,顶板205和底板210被封闭在电介质230中。也就是说,电介质230围绕顶板205和底板210两者并且与基板117接触。在一些示例中,电介质230围绕基板117。在一些示例中,相同的电介质用于整个管芯。也就是说,图2的第一管芯102的电介质可以封闭第一叠堆110的顶板和底板,以及第二叠堆115的顶板和底板。在本文公开的示例中,电介质230是二氧化硅。然而,可以附加地或替代地使用任何其他电介质材料。
图3是图1的第一叠堆110的俯视图。结合图1的第一叠堆110描述图3的示例,但是图3的示例也适用于图1的第二叠堆115、第三叠堆120和第四叠堆125。在图3的示例中,顶板205的表面积小于底板210的表面积。底板210的表面积小于基板117的表面积。由于顶板205和底板210之间的表面积和/或间距的差异,电容215、220是不同的。图3的示例视图300表示图1的第一叠堆110。然而,第二叠堆115、第三叠堆120和第四叠堆125可以以类似的方式布置。
在实施方式中,期望使顶板的尺寸在第一叠堆110、第二叠堆115、第三叠堆120和第四叠堆125之间匹配。同样,期望使底板的尺寸在第一叠堆110、第二叠堆115、第三叠堆120和第四叠堆125之间匹配。使用匹配的板尺寸确保在基板和板之间形成的电容在第一叠堆110、第二叠堆115、第三叠堆120和第四叠堆125中的每个之间匹配。
图4是图1的示例第一管芯102、示例第二管芯104和示例键合线106、108的电路图400。在图4的示例中,示例第一管芯102包括第一电容402、第二电容406、第一电阻408、第二电阻410、第三电容412和第四电容416。在图4的示例中,在第一示例管芯102内表示了四个节点401、404、414、419。在图4的示例中,第一节点401表示第一管芯102的第一顶板(例如,图1的第一叠堆110的顶板)。第二示例节点404表示第一管芯102的第一底板(例如,图1的第一叠堆110的底板)。第三示例节点414表示第一管芯102的第二底板(例如,图1的第二叠堆115的底板)。第四示例节点419表示第一管芯102的第二顶板(例如,图1的第二叠堆115的顶板)。
在图4的示例中,第一电容402表示在第一节点401和第二节点404之间(例如,在图1的第一叠堆110的顶板和底板之间)形成的电容。第二电容406表示在第二节点404与第一管芯102的基板之间形成的电容(例如,在图1的第一叠堆110的底板与图1的基板117之间形成的电容)。第一电阻408表示基板的电阻。因此,第一电阻408模拟在基板处经历的损耗。
在图1的示例中,第二电阻410表示基板的电阻(例如,第二电阻410模拟基板处经历的损耗)。第三电容412表示在第一管芯102的基板和第三节点414之间(例如,在图1的基板117和第二叠堆115的底板之间)形成的电容。第四示例电容416表示在第三节点414和第四节点419之间(例如,在图1的第二叠堆115的底板和第二叠堆115的顶板之间)形成的电容。
在图4的示例中,示例第二管芯104包括第五电容422、第六电容426、第三电阻428、第四电阻430、第七电容432和第八电容436。在图4的示例中,在第二示例管芯104内表示了四个节点421、424、434、439。在图4的示例中,第五节点422表示第二管芯104的第一顶板(例如,图1的第三叠堆120的顶板)。第六示例节点424表示第二管芯104的第一底板(例如,图1的第三叠堆120的底板)。第七示例节点434表示第二管芯104的第二底板(例如,图1的第四叠堆125的底板)。第八示例节点439表示第二管芯104的第二顶板(例如,图1的第四叠堆120的顶板)。
在图4的示例中,第五电容422表示在第五节点421和第六节点424之间(例如,在图1的第三叠堆120的顶板和底板之间)形成的电容。第六电容426表示在第六节点424和第二管芯104的基板之间形成的电容(例如,在图1的第三叠堆120的底板和图1的基板127之间形成的电容)。第三电阻428表示基板的电阻(例如,第三电阻428模拟在基板处经历的损耗)。
在图1的示例中,第四电阻430表示基板的电阻(例如,第四电阻430模拟在基板处经历的损耗)。第七电容432表示在第一管芯102的基板和第七节点434之间(例如,在图1的基板127和第四叠堆125的底板之间)形成的电容。第八示例电容436表示在第七节点434和第八节点439之间(例如,在图1的第四叠堆125的底板和第四叠堆125的顶板之间)形成的电容。
在本文公开的示例中,第一管芯102和第二管芯104的电容和电阻的值基于叠堆的基板和部件(例如,顶板和底板)的物理布置。本文公开的示例假设第一叠堆110、第二叠堆115、第三叠堆120和第四叠堆125的结构是一致的。因此,第一电容402、第四电容416、第五电容422和第八电容436的值匹配(并且在图5中表示为Ciso)。同样,第二电容406、第三电容412、第六电容426和第七电容432的值匹配(并且在图5中表示为Cbot)。然而,在一些示例中,结构可能不匹配(有意或无意地),导致电容的不同值。
在图4的示例中,第一键合线106的第一端连接到第一节点401(例如,连接到第一叠堆110的顶板)。第一键合线106的第二端连接到第五节点421(例如,图1的第三叠堆120的顶板)。示例第一键合线106由第一电感442和第五电阻444表示。
在图4的示例中,第二键合线108的第一端连接到第四节点419(例如,图1的第二叠堆115的顶板)。第二键合线108的第二端连接到第八节点439(例如,图1的第四叠堆125的顶板)。示例第二键合线108由第二电感452和第六电阻454表示。
在图4的示例中,跨第二节点404和第三节点414施加电压信号,并且在第六节点424和第七节点434处接收该电压信号。在本文公开的示例中,第六节点424和第七节点434之间的电压差相对于第二节点404和第三节点414之间的电压差被衰减。在一些示例中,电压的衰减是跨隔离电容(例如,第一电容402、第四电容416、第五电容422和/或第八电容436)经历的损耗的结果。在一些示例中,衰减是在(一个或多个)基板和(一个或多个)底板之间形成的电容相比于(一个或多个底板)和(一个或多个顶板)之间形成的电容的差异的结果。在一些示例中,衰减也是键合线106、108之间的寄生电容的结果。
为了促进更可靠的信号传输(例如,具有较低衰减的传输),一些示例方法利用在接收侧处(例如,在第二管芯104处)的放大。然而,使用这种方法也放大噪声。因为噪声也被放大,所以传输的信噪比没有提高。替代方法利用传输侧处(例如,在第一管芯102处)的增加的电压差。然而,提供增加的电压差并不总是可行的,因为对用于跨第二节点404和第三节点414施加电压差的晶体管可能存在电压限制。
为了解决现有方法的缺陷,将电感器连接在管芯的底板中的每个之间。与底板和基板之间的电容并联的电感器形成LC储能回路(tank),该LC储能回路在一频率下产生高阻抗。图5中示出了使用与底板和(一个或多个)基板之间形成的电容并联的电感器的示例方法。图5是根据本说明书构造的图1和/或图4的示例第一管芯102、示例第二管芯104和示例键合线106、108的电路图。在图5的示例中,第三电感器509和第四电感器529添加到图4的电路400。在图5的示例中,第三电感器509被包括在第二节点404和第三节点414中间。第四电感器529被包括在第六节点424和第七节点434中间。
在图5的示例中,第三电感器509与第二电容406和第三电容412并联。第四电感器529与第六电容426和第七电容432并联。由于并联关系,在谐振频率下在第六示例节点424和第七示例节点434之间产生高阻抗。谐振频率由以下等式1定义:
在该示例等式1中,Cbot表示在叠堆(例如,图1的第一叠堆110)的底板与对应的基板之间形成的电容。L表示电感器(例如,第三电感器509或第四电感器529)的值。当传输侧(例如,第一管芯102)和接收侧(例如,第二管芯104)中的每个被调谐使得它们的频率匹配时,噪声被滤除,从而提高接收信号的信噪比。在一些示例中,附加电容器被添加以与电感器509、529中的一个或多个并联以便于频率的精细调谐。此种方法不需要有源放大,并且因此不消耗大量功率。
图6是图5的示例第一管芯102、示例第二管芯104、键合线106、108和电感器509、529的图示。在图6的示例中,第一电感器509连接到第一底板610和第二底板615。第二电感器529连接到第三底板630和第四底板635。第一键合线106连接到第一顶板620和第三顶板640。第二键合线108连接到第二顶板625和第四顶板645。
在图6的示例中,电感器509、529是平面电感器。在图6的示例中,电感器509、529布置在与对应基板117、127的表面基本上平行的(一个或多个)平面中。如本文所用,当电感器和对应基板之间的距离偏离电感器和对应基板之间的平均距离不超过百分之二十时,电感器基本上平行于对应基板的(一个或多个)表面。在一些示例中,电感器被封闭在图2的电介质230中。然而,可以附加地或替代地使用任何其他类型的电感器。例如,电感器中的一个或多个可以实现为外部部件(例如,与管芯102、104分开的分立部件)。
图7是示出用于跨图5和/或图6的电容耦合通道传输和/或驱动信号的示例方法的电路图。在图7的示例中,第一晶体管705和第二晶体管710添加到图5的电路500。在图7的示例中,第一晶体管705是n型金属氧化物半导体场效应晶体管(MOSFET)。在一些示例中,第一晶体管705和第二晶体管710的接地节点可以连接在一起和/或连接到电流源。在图7的示例中,第二晶体管710是n型MOSFET。
第一晶体管705的第一端子连接到接地。第一晶体管705的第二端子连接到第二节点404(例如,第一叠堆110的底板)。第一晶体管705的第三端子连接到第三节点414(例如,第二叠堆115的底板)。第二晶体管710的第一端子连接到接地。第二晶体管710的第二端子连接到第三节点414(例如,第二叠堆115的底板)。第二晶体管710的第三端子连接到第二节点404(例如,第一叠堆110的底板)。
在图7的示例中,第一晶体管705的第一端子是源极端子,第一晶体管705的第二端子是漏极端子,并且第一晶体管705的第三端子是栅极端子。在图7的示例中,第二晶体管710的第一端子是源极端子,第二晶体管710的第二端子是漏极端子,并且第二晶体管710的第三端子是栅极端子。当以这种方式布置时,第一晶体管705和第二晶体管710形成振荡器,该振荡器以由上文中的等式1定义的频率振荡。也就是说,振荡器的频率与LC储能回路的调谐频率匹配。作为结果,振荡频率和LC储能回路的谐振频率可以一起调谐。在一些示例中,频率可以被调谐到非常高的值,从而能够设计高数据速率传输系统。在实施方式中,通常基于其与在要传输的信号中使用的调制方案的兼容性来选择频率。
图8是示出跨频谱的示例接收信号的幅度的幅度点图800。图8的示例点图800的水平轴线810表示以吉赫兹(GHz)为单位的频率。图8的示例点图800的竖直轴线820表示以毫伏(mV)为单位的接收信号的幅度。在图8的示例中,示出了接收信号。第一接收信号830表示使用图4的电路400(例如,在相应的管芯的底板中间没有电感器)接收的信号。第二接收信号840表示使用图5的电路500(例如,在相应的管芯的底板中间具有电感器)接收的信号。在图5的示例中,对应于第二接收信号840的电路被调谐到大约2.26875GHz的谐振频率。在2.26872GHz下,第一接收信号830具有大约51mV的幅度,而第二接收信号840具有大约134mV的幅度。实际上,结果值可以不同,这取决于许多因素,诸如,例如调谐频率、输入信号的幅值、(一个或多个)无源放大器的(一个或多个)增益(Q)等。因此,由于通过添加电感器509、529进行调谐,调谐频率下的接收信号的幅度大于其本来将具有的幅度。作为结果,通过电容隔离连接的信号传输变得更可靠。
根据前述内容,上述设备和制品使得能够使用电容耦合来传输电压差信号。在本文描述的示例中,在堆叠电容耦合系统的底板中间包括电感器产生了作为无源放大器操作的LC储能回路。可以将该无源放大调谐到期望的频率,并且当以该频率传输数据时,增加了所得数据传递的信噪比。
在权利要求的范围内,所描述的实施例中的修改是可能的,并且其他实施例是可能的。
Claims (20)
1.一种电路,其包括:
基板;
第一板,其基本上平行于所述基板从而在所述第一板和所述基板中间形成第一电容;
第二板,其基本上平行于所述基板和所述第一板,所述第一板位于所述基板和所述第二板中间;
第三板,其基本上平行于所述基板从而在所述第三板和所述基板中间形成第二电容;
第四板,其基本上平行于所述基板和所述第三板,所述第三板位于所述基板和所述第四板中间;以及
电感器,其连接到所述第一板和所述第三板,所述电感器与所述第一电容和所述第二电容组合形成LC放大器。
2.根据权利要求1所述的电路,其中所述电感器是平面电感器。
3.根据权利要求2所述的电路,其中所述平面电感器基本上平行于所述基板。
4.根据权利要求1所述的电路,其中所述第一板的第一表面积小于所述基板的第二表面积。
5.根据权利要求4所述的电路,其中所述第二板的第三表面积小于所述第一板的所述第一表面积。
6.根据权利要求1所述的电路,其中所述第一板与所述基板分开第一距离,并且所述第三板与所述基板分开所述第一距离。
7.根据权利要求6所述的电路,其中所述第二板与所述第一板分开第二距离,并且所述第四板与所述第三板分开所述第二距离。
8.根据权利要求1所述的电路,其中所述第一板、所述第二板、所述第三板和所述第四板被封闭在电介质中。
9.根据权利要求1所述的电路,进一步包括:
第一晶体管,其具有连接到所述第一板的第一端子和连接到所述第三板的第二端子;以及
第二晶体管,其具有连接到所述第三板的第三端子和连接到所述第一板的第四端子,所述第一晶体管和所述第二晶体管形成振荡器。
10.根据权利要求9所述的电路,其中所述LC放大器具有在第一频率下的峰值幅值,所述振荡器在所述第一频率下振荡。
11.根据权利要求1所述的电路,进一步包括:
第一键合线,其连接到所述第二板;以及
第二键合线,其连接到所述第四板,所述第一板和所述第三板接收差分电压信号以用于经由所述第一键合线和所述第二键合线传输。
12.一种用于跨电容耦合通道进行通信的系统,所述系统包括:
第一管芯,其包括第一基板、第一板、第二板、第三板和第四板,其中所述第一板、所述第二板、所述第三板和所述第四板基本上平行于所述第一基板,所述第一板位于所述第二板和所述第一基板中间,所述第三板位于所述第四板和所述第一基板中间;
第一电感器,其连接所述第一板和所述第三板;
第二管芯,其包括第二基板、第五板、第六板、第七板和第八板,其中所述第五板、所述第六板、所述第七板和所述第八板基本上平行于所述第二基板,所述第五板位于所述第六板和所述第二基板中间,所述第七板位于所述第八板和所述第二基板中间;
第二电感器,其连接所述第五板和所述第七板;
第一键合线,其连接所述第二板和所述第六板;以及
第二键合线,其连接所述第四板和所述第八板。
13.根据权利要求12所述的系统,其中所述第一电感器是平面电感器。
14.根据权利要求13所述的系统,其中所述平面电感器基本上平行于所述第一基板。
15.根据权利要求12所述的系统,其中所述第一板与所述第一基板分开第一距离,并且所述第三板与所述第一基板分开所述第一距离。
16.根据权利要求15所述的系统,其中所述第五板与所述第二基板分开所述第一距离,并且所述第七板与所述第二基板分开所述第一距离。
17.根据权利要求12所述的系统,其中所述第一板、所述第二板、所述第三板和所述第四板被封闭在第一电介质中。
18.根据权利要求12所述的系统,其中所述第一管芯在第一电压域中操作,并且所述第二管芯在与所述第一电压域不同的第二电压域中操作。
19.根据权利要求12所述的系统,其中跨所述第一板和所述第三板施加差分电压信号,并且跨所述第五板和所述第七板接收所述差分电压信号。
20.一种电路,其包括:
基板;
第一板,其基本上平行于所述基板从而在所述第一板和所述基板中间形成第一电容;
第二板,其基本上平行于所述基板和所述第一板,所述第一板位于所述基板和所述第二板中间;
电感器,其连接到所述第一板,所述电感器与所述第一电容组合形成LC放大器;以及
键合线,其连接到所述第二板。
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US20070148895A1 (en) * | 2005-12-28 | 2007-06-28 | Palo Alto Research Center Incorporated | Integrateable capacitors and microcoils and methods of making thereof |
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