CN110247652A - Based on print address book stored array and use two-sided integrated programmable computing array - Google Patents
Based on print address book stored array and use two-sided integrated programmable computing array Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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Abstract
The present invention proposes a kind of novel programmable gate array --- programmable computing array chip.It is a single (monolithic) chip and contains multiple programmable computing units, multiple programmable logic chips and multiple reconfigurable interconnections.Each programmable computing unit contains multiple print address book stored arrays, and each print address book stored array stores the look-up table (LUT) in a basic function library.Programmable computing unit and programmable logic cells are respectively formed at the different surfaces (front and back) of same semi-conductive substrate, and are electrically coupled by penetrating substrate connection.
Description
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to programmable gate array.
Background technique
Programmable gate array belongs to semicustom integrated circuit, i.e., by backend process or field programming, realizes to logic electricity
The customization on road.United States Patent (USP) 4,870,302 discloses a kind of programmable gate array.It contains multiple programmable logic cells
(configurable logic element or configurable logic block) and reconfigurable interconnection
(configurable interconnect or programmable interconnect).Wherein, programmable logic cells exist
Realize displacement, logic NOT, AND(logical AND to the property of can choose under setting signal control), OR(logic sum), NOR(and non-),
NAND(and non-), XOR(exclusive or) ,+(arithmetic adds) ,-functions such as (arithmetic subtracts)；Reconfigurable interconnection can be under setting signal control
Selectively realize the functions such as connection, the disconnection between two interconnection lines.
Currently, many applications all refer to the calculating of complex mathematical function.The example of complex mathematical function includes surmounting function,
Such as index (exp), logarithm (log), trigonometric function (sina, cos) and their combination.It is high in order to guarantee to execute speed
Complex mathematical function is realized in performance applications requirement with hardware.In existing programmable gate array, complex mathematical function is logical
Come over to solidify computing unit to realize.These solidify a part that computing unit is stone (hard block), and circuit is
Solidification cannot reconfigure it.It is obvious that further applying for programmable gate array will be limited by solidifying computing unit.For
Overcome this difficulty, the present invention makes the concept of programmable gate circuit solidify computing unit programmable.Specifically
Come, programmable gate circuit is other than containing programmable logic cells, also containing programmable computing unit.The programmable calculating is single
Realize one of a variety of basic functions to the member property of can choose.
Summary of the invention
The main object of the present invention is to promote programmable gate circuit in the application in complex mathematical computations field.
It is a further object of the present invention to provide a kind of programmable counting circuits, and not only its logic function can be customized,
Computing function can also be customized.
A kind of it is a further object of the present invention to provide computing capabilitys more flexible, more powerful programmable gate array.
In order to realize that these and other purpose, the present invention propose a kind of novel programmable gate array --- it is programmable to calculate
Array chip.It is a single (monolithic) chip and contains multiple programmable computing units, multiple programmable logic cores
Piece and multiple reconfigurable interconnections.Each programmable computing unit contains multiple print address book stored arrays, and each print address book stored array is deposited
Store up the look-up table (LUT) in a basic function library.Programmable computing unit and programmable logic cells are respectively formed at same half and lead
The different surfaces (front and back) of body substrate, and be electrically coupled by penetrating substrate connection.
For high performance programmable computing unit, three-dimensional print records reservoir (three-dimensional printed
Memory, referred to as 3D-P, referring to Chinese patent 201280042212.5) it is especially suitable for storage LUT.3D-P is three-dimensional storage
The one kind of (three-dimensional memory, referred to as 3D-M, referring to Chinese patent 98119572.5), the letter of storage
Breath is in process of factory production using using mode of printing typing (Yin Lufa, such as photoetching, nano impression means) typing
's.These information are permanently fixed, and cannot be changed after factory.Since 3D-P storage member does not need to realize electrical programming, it can be than three
Tie up writable memory (three-dimensional writable memory, referred to as 3D-W) bear bigger read voltage and
Read current.Therefore, the reading rate of 3D-P is far faster than 3D-W.
In addition to may be programmed computing unit, programmable computing array chip also contains multiple programmable logic cells and may be programmed
Connection.Complex mathematical function is a kind of group of basic function (including log, exp, sin, cos, sqrt, cbrt, tan, atan etc.)
It closes.During its realization, complex mathematical function is first broken down into multiple basic functions.Then it is set for each basic function
Corresponding programmable computing unit is set, corresponding basic function is achieved.Finally, passing through setting programmable logic cells and can
Programming connection, realizes required complex mathematical function.
Realize that programmable computing unit there are many advantages using 3D-P: firstly, the reading rate of 3D-P ratio 3D-W is fast, it can be real
Existing high-performance calculation unit；Secondly, 3D-P array size needed for different basic functions is all the same or differs integral multiple.It represents not
3D-P array with basic function can be placed in different accumulation layers, and is integrated into same 3D-M module by three-dimensional stacked.
This can greatly reduce Substrate Area shared by programmable computing unit.Finally, due to 3D-P array does not account for Substrate Area substantially,
Reconfigurable interconnection can integrate below 3D-P array in computing unit, can be further reduced programmable computing unit institute in this way
The Substrate Area accounted for.
Correspondingly, the present invention proposes a kind of programmable computing array (400) chip, it is characterised in that contain: one contains two
The semiconductor substrate (0) on a surface, two surfaces include one positive (0F) and a reverse side (0B)；At least one programmable calculating is single
First (100,100AA-100AD), programmable computing unit (100) are contained: the first and second three-dimensional prints record reservoir (3D-P)
Array (110,120), the first 3D-P array (110) store at least partly look-up table (LUT A) of one first basic function,
2nd 3D-P array (120) stores at least partly look-up table (LUT B) of one second basic function；At least one with this first and
Reconfigurable interconnection (150 or 160) in the computing unit of 2nd 3D-P array coupling, based on reconfigurable interconnection in the computing unit
The first or second basic function is selectively realized in setting signal (125), programmable computing unit (100)；It is multiple to compile
Journey logic unit (200,200AA-200AD), the programmable logic cells (200) are selectively real from a logical operation library
A kind of existing logical operation；The programmable computing unit (100,100AA-100AD) and the programmable logic cells (200,
The different surfaces of the semiconductor substrate (0) 200AA-200AD) are respectively formed at, and penetrate substrate connection (180) electricity by multiple
Coupling.
Detailed description of the invention
Fig. 1 is a kind of symbol of programmable computing unit.
Fig. 2 is a kind of circuit block diagram of programmable computing unit, which discloses the programmable computing unit simultaneously and realize
Basic function library.
Fig. 3 is the first implementation of the programmable computing unit, which is its circuit diagram.
Fig. 4 A- Fig. 4 B is second of implementation of the programmable computing unit, and Fig. 4 A is its sectional view；Fig. 4 B serves as a contrast for it
Bottom circuit arrangement map.
Fig. 5 is a kind of circuit diagram of programmable computing array chip.
Fig. 6 A discloses a kind of link library that reconfigurable interconnection is realized；Fig. 6 B discloses a kind of patrolling for programmable logic cells realization
Collect operation library.
Fig. 7 is a kind of circuit diagram of programmable computing array chip specific implementation.
Fig. 8 A is a kind of front perspective view of programmable computing array chip；Fig. 8 B is the programmable computing array chip
Back perspective view；Fig. 8 C is the sectional view of the programmable computing array chip.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Specific embodiment
Fig. 1 is a kind of symbol of programmable computing unit 100.Its input terminal IN includes input data 115, output end OUT
Including output data 135, it includes setting signal 125 that end CFG, which is arranged,.Under the control of setting signal 125, the programmable calculating is single
Member 100 selects required basic function from a basic function library.
Fig. 2 is a kind of circuit block diagram of programmable computing unit 100, which discloses the programmable computing unit simultaneously
The 100 basic function libraries being able to achieve.It contains reconfigurable interconnection 150,160 and storage one in the first and second computing units
The LUT A-D in basic function library.In the present embodiment, in the first computing unit reconfigurable interconnection 150 be one 1 to 4 demux,
Reconfigurable interconnection 160 is one 4 to 1 mux in second computing unit, which includes logarithm log (), exponent e xp
(), logarithmic sine log [sin ()] and logarithmic cosine log [cos ()].LUT A storage logarithmic table log (), LUT B storage refer to
Number table exp (), LUT C storage logarithmic sine table log [sin ()], LUT D storage logarithmic cosine table log [cos ()].Such as
It says, in order to realize function exp (), input data 115 is sent to corresponding LUT B by reconfigurable interconnection 150 in the first computing unit
As address.It is tabled look-up based on this address, i.e. value (exp ()) in reading LUT B.It then can in the second computing unit
Programming connection 160 will be sent to output as output data 135 from the value.For the professional person for being familiar with this field, substantially
Function library can contain more basic functions.Compare, it can contain eight kinds of basic functions, including log (), exp (),
sin(),cos(),sqrt(),cbrt(),tan(),atan().Certainly, other multiple combinations are also feasible.
Fig. 3 indicates the first implementation of programmable computing unit 100, this is its circuit diagram.In this embodiment, often
A LUT is stored in a print address book stored array: LUT A is stored in print address book stored array 110, and LUT B is stored in print address book stored
In array 120, LUT C is stored in print address book stored array 130, and LUT D is stored in print address book stored array 140.These print records
Storage array 110-140 side by side arrangement.The circuit further include in computing unit reconfigurable interconnection 150,160 and it is each print record
Store up the peripheral circuit of array 110-140: X-decoder 15A and Y-decoder (including reading circuit) as printed address book stored array 110
17A etc..
In order to reduce Substrate Area shared by programmable computing unit 100, the abundant three-dimensional storage of the present invention (3D-M, ginseng
See Chinese patent 98119572.5) three-dimensional stacked characteristic, by the three-dimensional print for storing different basic functions record reservoir (3D-P,
Referring to Chinese patent 201280042212.5) array is stacked.Fig. 4 A- Fig. 4 B indicates the of programmable computing unit 100
Two kinds of implementations.In the sectional view of Fig. 4 A, the 3D-P array 110 of the LUT A of storage function log () is stacked on substrate electricity
Above the 0K of road (direction+z), the 3D-P array 120 of the LUT B of storage function exp () is stacked on the 110 top (side+z of 3D-P array
To), the 3D-P array 130 of the LUT C of storage function log [sin ()] is stacked on 120 top (direction+z) of 3D-P array, deposits
The 3D-P array 140 for storing up the LUT D of function log [cos ()] is stacked on 130 top (direction+z) of 3D-P array.From Fig. 4 B's
Substrate circuitry layout can be seen more clearly, and the 3D-P array 110 of the storage LUT A in the embodiment stores LUT B's
3D-P array 120, the 3D-P array 130 for storing LUT C, projection of the 3D-P array 140 on substrate 0 for storing LUT D are
Overlapping, the substrate gross area shared by them is 1/4 of embodiment in Fig. 3.Meanwhile rise can in computing unit for Z decoder 19
The effect of programming connection 150,160.
For 3D-P, due to data typing in technical process of storage, and it cannot change later, 3D-P is not required to
Support electrical programming.Compare therewith, three-dimensional writable memory (3D-W) needs support electrical programming.Not due to read voltage/read current
It can exceed that program voltage/program current, read voltage/read current that 3D-W can bear are respectively less than 3D-P.Due to the reading of 3D-W
Speed is far below 3D-P, and 3D-P is more suitable for high-performance calculation.
Fig. 5 indicates a kind of programmable computing array chip 400.It contains regularly arranged programmable module 400A and can compile
Journey module 400B etc..Each programmable module (such as 400A) contains multiple programmable computing units (such as 100AA-100AD) and can
Programmed logic unit (such as 200AA-200AD).In programmable computing unit (such as 100AA-100AD) and programmable logic cells
Contain programmable channel 320,340 between (such as 200AA-200AD)；Programmable module 400A and programmable module 400B it
Between, also contain programmable channel 310,330,350.Programmable channel 310-350 contains multiple reconfigurable interconnections 300.For ripe
It knows for the professional person of this field, other than programmable channel, programmable computing array chip 400 can also use sea of gates
(sea-of-gates) design such as.
Fig. 6 A discloses a kind of link library that reconfigurable interconnection 300 is able to achieve.The reconfigurable interconnection 300 and United States Patent (USP) 4,
The reconfigurable interconnection disclosed in 870,302 is similar.It uses a kind of connection type of following link libraries: a) interconnection line 302/304
It is connected, interconnection line 306/308 is connected, but 302/304 is not attached to 306/308；B) interconnection line 302/304/306/308 is homogeneous
Even；C) interconnection line 306/308 is connected, and interconnection line 302,304 is not attached to, and is not also connected with 306/308；D) interconnection line 302/304
It is connected, interconnection line 306,306 is not attached to, and is not also connected with 302/304；E) interconnection line 302,304,306,306 is not attached to.?
In this specification, the symbol "/" between two interconnection lines indicates that two interconnection lines are connected, the symbol between two interconnection lines
", " indicate that two interconnection lines are not attached to.
Fig. 6 B discloses a kind of logical operation library that programmable logic cells 200 are able to achieve.It is input data that it, which inputs A and B,
210,220, output C are output data 230.What is disclosed in the programmable logic cells 200 and United States Patent (USP) 4,870,302 compiles
Journey logic unit is similar.It may be implemented at least one of following logical operation libraries: C=A, A logic NOT, A displacement, AND (A,
B), OR (A, B), NAND (A, B), NOR (A, B), XOR (A, B), arithmetic add A+B, arithmetic to subtract A-B etc..Programmable logic cells
200 can also be containing sequential circuit elements such as register, triggers, with the operation such as assembly line of practising (pipeline).
Fig. 7 is a kind of specific implementation of programmable computing array chip 400, it is for realizing a complex mathematical function: e=
a.sin(b)+c.cos(d).Reconfigurable interconnection 300 is using the representation in Fig. 6 A in programmable channel 310-350: intersecting
Point has the reconfigurable interconnection of dot to indicate that cross spider is connected, and crosspoint indicates that cross spider is not attached to without the reconfigurable interconnection of dot,
The reconfigurable interconnection of disconnection indicates that the interconnection line disconnected is divided into two mutual disjunct interconnection line segments.In this embodiment, may be used
Program calculation unit 100AA is arranged to log (), and calculated result log (a) is sent to the of programmable logic cells 200AA
One input.Programmable computing unit 100AB is arranged to log [sin ()], and calculated result log [sin (b)] is sent to and can compile
The second input of journey logic unit 200AA.Programmable logic cells 200AA is arranged to " arithmetic adds ", calculated result log
(a)+log [sin (b)] is sent to programmable computing unit 100BA.Programmable computing unit 100BA is arranged to exp (),
Calculated result exp { log (a)+log [sin (b)] }=a.Sin (b) is sent to the first input of programmable logic cells 200BA.
Similarly, by setting appropriate, computing unit 100AC, 100AD, programmable logic cells 200AC, programmable meter be may be programmed
Calculate the result c of unit 100BC.Cos (d) is sent to the second input of programmable logic cells 200BA.Programmable logic cells
200BA is arranged to " arithmetic adds ", a.Sin (b) and c.Cos (d) is added herein, and final result is sent to output e.It is obvious that passing through
Change setting, programmable computing array chip 400 can also realize other complex mathematical functions.
Fig. 8 A is a kind of front perspective view of programmable computing array chip 400；Fig. 8 B is the programmable computing array core
The back perspective view of piece 400；Fig. 8 C is the sectional view of the programmable computing array chip 400.The programmable computing array chip
400 are a single (monolithic) chips and contain semi-conductive substrate 0.The substrate 0 contains the front direction 0F(+z) and back
The face direction 0B(-z).In this embodiment, programmable logic cells 200AA-200BB is formed in the positive 0F of substrate 0；It is programmable
Computing unit 100AA-100BB is formed in the back side 0B of substrate 0, between them by it is multiple penetrate substrate connection (180, including
180a-180c) it is electrically coupled.The example for penetrating substrate connection (180, including 180a-180c) includes penetrating silicon wafer channel
(TSV).In other embodiments, it may be programmed the positive 0F that computing unit 100AA-100BB is formed in substrate 0；Programmable logic
Unit 200AA-200BB is formed in the back side 0B of substrate 0.
It is this that programmable logic cells 200AA-200BB and programmable computing unit 100AA-100BB is being formed into substrate just
The integration mode on anti-two sides is referred to as two-sided integrated.Two-sided integrated can improve calculates density and computation complexity.Using traditional
Two dimension is integrated, and the area that may be programmed computing array is the sum of programmable logic cells and programmable computing unit.Using two-sided collection
Cheng Hou, LUT move on to other one side of substrate from side, and programmable computing array becomes smaller, and calculate density and reinforce.Further, since structure
At the storage of the programmable computing unit 100AA-100BB of logic transistor and composition of programmable logic cells 200AA-200BB
Transistor is respectively formed on the different surfaces of substrate, their manufacturing process can be separately optimized.
This specification is by taking field programmable gate array (FPGA) as an example.In FPGA, wafer will complete all process steps (including
All programmable computing unit, programmable logic cells and reconfigurable interconnection).It, can be by the way that programmable connect be arranged at programming scene
Fetch the function of defining FPGA.The example of above-mentioned FPGA can easily be generalized to traditional programmable gate array.In tradition
In programmable gate array, wafer is only semi-finished, i.e., wafer production is only completed programmable computing unit and programmable logic cells, but
Reconfigurable interconnection is not completed.After the function of chip determines, programmable channel 310-350 is customized by backend process.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention
It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims,
The present invention should not be any way limited.
Claims (10)
1. a kind of programmable computing array (400), it is characterised in that contain:
One containing there are two the semiconductor substrate (0) on surface, which includes one positive (0F) and a reverse side (0B)；
At least one programmable computing unit (100,100AA-100AD), programmable computing unit (100) are contained: first and the
Two three-dimensional prints record reservoir (3D-P) array (110,120), and the first 3D-P array (110) stores one first basic function
At least partly look-up table (LUT A), the 2nd 3D-P array (120) store at least partly look-up table of one second basic function
(LUT B)；Reconfigurable interconnection (150 or 160) at least one computing unit coupled with the first and second 3D-P array, is based on
The setting signal (125) of reconfigurable interconnection in the computing unit, programmable computing unit (100) selectively realize this first
Or second basic function；
Multiple programmable logic cells (200,200AA-200AD), the programmable logic cells (200) are from a logical operation library
In selectively realize a kind of logical operation；
The programmable computing unit (100,100AA-100AD) and the programmable logic cells (200,200AA-
It 200AD) is respectively formed at the different surfaces of the semiconductor substrate (0), and penetrates substrate connection (180) by multiple and be electrically coupled.
2. programmable computing array (400) according to claim 1, it is further characterized in that containing: multiple to may be programmed this
Computing unit (100AA-100AD) and the selectively coupled reconfigurable interconnection of the programmable logic cells (200AA-200AD)
(300)。
3. programmable computing array (400) according to claim 1, it is further characterized in that: by the programmable calculating
Unit (100AA-100AD), the programmable logic cells (200AA-200AD) and the reconfigurable interconnection (300) be programmed with
Realize a function, which is a kind of combination of first and second basic function.
4. programmable computing array (400) according to claim 1, it is further characterized in that: this first and second 3D-P gusts
Column (110,120) are arranged side by side.
5. programmable computing array (400) according to claim 1, it is further characterized in that: the 2nd 3D-P array stacks
(120) on the first 3D-P array (110).
6. programmable computing array (400) according to claim 1, it is further characterized in that: the number being stored in the 3D-P
According to being in process of production by a printing process typing.
7. programmable computing array (400) according to claim 6, it is further characterized in that: the printing process includes photoetching
(photo-lithography), nano-imprint method (nano-imprint), electron beam scanning exposure (e-beam
Lithography), at least one of DUV scan exposure and laser scanning exposure (laser programming).
8. programmable computing array (400) according to claim 1, it is further characterized in that: the programmable computing unit
(100,100AA-100AD) it is located at the back side (0B) of the semiconductor substrate (0), the programmable logic cells (200,200AA-
200AD) it is located at the front (0F) of the semiconductor substrate (0).
9. programmable computing array (400) according to claim 1, it is further characterized in that: the programmable computing unit
(100,100AA-100AD) it is located at the front (0F) of the semiconductor substrate (0), the programmable logic cells (200,200AA-
200AD) it is located at the back side (0B) of the semiconductor substrate (0).
10. programmable computing array (400) according to claim 1, it is further characterized in that: 3D-P gusts of the first or second
Column (110 or 120) are stacked on above reconfigurable interconnection in the computing unit (150 or 160).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810187766.3A CN110247652A (en) | 2018-03-07 | 2018-03-07 | Based on print address book stored array and use two-sided integrated programmable computing array |
| US15/917,520 US10148271B2 (en) | 2016-03-05 | 2018-03-09 | Configurable computing array die based on printed memory and two-sided integration |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810187766.3A CN110247652A (en) | 2018-03-07 | 2018-03-07 | Based on print address book stored array and use two-sided integrated programmable computing array |
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| CN107154797A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | Programmable gate array based on three-dimensional printed memory |
| US20180048316A1 (en) * | 2016-03-05 | 2018-02-15 | Chengdu Haicun Ip Technology Llc | Configurable Computing Array Using Two-Sided Integration |
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2018
- 2018-03-07 CN CN201810187766.3A patent/CN110247652A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154797A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | Programmable gate array based on three-dimensional printed memory |
| US20180048316A1 (en) * | 2016-03-05 | 2018-02-15 | Chengdu Haicun Ip Technology Llc | Configurable Computing Array Using Two-Sided Integration |
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Application publication date: 20190917 |