CN110235394B - Method for realizing high-frequency carrier synchronization and related device - Google Patents
Method for realizing high-frequency carrier synchronization and related device Download PDFInfo
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- CN110235394B CN110235394B CN201780084715.1A CN201780084715A CN110235394B CN 110235394 B CN110235394 B CN 110235394B CN 201780084715 A CN201780084715 A CN 201780084715A CN 110235394 B CN110235394 B CN 110235394B
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Abstract
The embodiment of the invention provides a method for realizing high-frequency carrier synchronization and a related device. A method for realizing high-frequency carrier synchronization comprises the following steps: a CPLD operation chip of the slave equipment acquires a master high-frequency synchronous square wave signal sent by the master equipment from a bus; the CPLD operation chip of the slave equipment acquires a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment; the CPLD operation chip of the slave equipment determines the phase adjustment information of the carrier of the slave equipment according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; the CPLD operation chip of the slave equipment transmits the direction adjusting signal carrying the phase adjusting information to the MCU main control chip of the slave equipment; and the MCU main control chip of the slave equipment adjusts the carrier of the slave equipment according to the direction adjusting signal. The technical scheme of the invention can realize master-slave synchronization under the condition that the MCU master control chip does not have a capture port.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and a related apparatus for implementing high frequency carrier synchronization.
Background
In inverter or dc source application, N devices are usually connected in parallel to expand capacity, and the parallel connection can increase the capacity of the system, but may cause circulation problems, and the circulation may reduce the efficiency of the system and increase the system loss. The high-frequency carrier synchronization can effectively reduce circulation current, and the high-frequency carrier synchronization is realized by a plurality of methods, wherein the conventional method is that a host generates a square wave signal with the same frequency as a carrier, and a slave captures an edge signal of the square wave by using a capture port, so that the phase difference between the slave and the host is judged, the carrier period of the slave is adjusted to realize that the slave follows the host, and the master-slave synchronization is realized.
In the method, a Micro Controller Unit (MCU) is required to have a capture function, and sometimes, an MCU master control chip with relatively few chip resources, i.e., an MCU master control chip without a capture port, is used based on cost considerations.
Disclosure of Invention
The embodiment of the invention provides a method and a related device for realizing high-frequency carrier synchronization, which can realize master-slave synchronization under the condition that an MCU (microprogrammed control Unit) master control chip does not have a capture port.
A first aspect of an embodiment of the present invention provides a method for implementing high frequency carrier synchronization, where the method includes:
a CPLD operation chip of the slave equipment acquires a master high-frequency synchronous square wave signal sent by the master equipment from a bus;
the CPLD operation chip of the slave equipment acquires a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment;
the CPLD operation chip of the slave equipment determines the phase adjustment information of the carrier of the slave equipment according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal;
the CPLD operation chip of the slave equipment transmits the direction adjusting signal carrying the phase adjusting information to the MCU main control chip of the slave equipment;
and the MCU main control chip of the slave equipment adjusts the carrier of the slave equipment according to the direction adjusting signal.
In one possible design, the determining, by the CPLD operation chip of the slave device, the phase adjustment information of the carrier of the slave device according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal includes: the CPLD operation chip of the slave equipment determines the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; and the CPLD operation chip of the slave equipment determines the phase adjustment information of the carrier of the slave equipment according to the phase difference.
In one possible design, the determining, by the CPLD operation chip of the slave device, the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal includes:
the CPLD operation chip of the slave equipment acquires a first moment when the rising edge of the slave high-frequency synchronous square wave signal is detected; the CPLD operation chip of the slave equipment acquires a second moment of detecting the rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal; and determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the time difference between the second moment and the first moment.
In one possible design, the determining, by the CPLD operation chip of the slave device according to the phase difference, phase adjustment information of the carrier of the slave device includes: if the phase difference is smaller than T/2, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is advanced adjustment; otherwise, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment; and the T is the duration of a high-level signal of the high-frequency synchronous square wave signal of the host in one high-frequency synchronous square wave signal period.
In a possible design, if the phase difference is smaller than T/2, the determining, by the CPLD operation chip of the slave device, that the phase adjustment information of the carrier of the slave device is an advance adjustment includes: if the phase difference is greater than a preset threshold and smaller than T/2, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is advanced adjustment; if not, the step of determining that the phase adjustment information of the slave high-frequency square wave signal is the hysteresis adjustment by the CPLD operation chip of the slave device comprises the following steps: and if the phase difference is greater than or equal to T/2 and smaller than the difference between T and the preset threshold, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment.
Accordingly, a second aspect of the embodiments of the present invention provides a slave device, including:
the CPLD operation chip is used for acquiring a host high-frequency synchronous square wave signal sent by the host equipment from the bus;
the CPLD operation chip is also used for acquiring a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment;
the CPLD operation chip is also used for determining the phase adjustment information of the carrier of the slave equipment according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal;
the CPLD operation chip is also used for transmitting a direction adjusting signal carrying the phase adjusting information to the MCU main control chip;
and the MCU main control chip is used for adjusting the carrier of the slave equipment according to the direction adjusting signal.
In one possible design, the CPLD operation chip includes: the phase difference determining module is used for determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; and the phase adjustment information determining module is used for determining the phase adjustment information of the carrier of the slave equipment according to the phase difference.
In one possible design, the phase difference determination module includes: the first time acquisition unit is used for acquiring a first time when the rising edge of the slave high-frequency synchronous square wave signal is detected; a second time acquiring unit, configured to acquire a second time when a rising edge of the master high-frequency synchronous square wave signal closest to a rising edge of the slave high-frequency synchronous square wave signal is detected; and the phase difference determining unit is used for determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the time difference between the second moment and the first moment.
In one possible design, the phase adjustment information determination module includes: an advance adjustment determining unit, configured to determine that phase adjustment information of a carrier of the slave device is advance adjustment if the phase difference is smaller than T/2; a hysteresis adjustment determination unit configured to determine that phase adjustment information of a carrier of the slave device is hysteresis adjustment; and the T is the duration of a high-level signal of the high-frequency synchronous square wave signal of the host in one high-frequency synchronous square wave signal period.
A third aspect of the embodiments of the present invention provides a system for implementing high-frequency carrier synchronization, including the slave device, the bus, and the host device provided in the first aspect of the embodiments of the present invention, where:
the host equipment is used for sending a host high-frequency synchronous square wave signal to the bus;
the slave equipment is used for acquiring a master high-frequency synchronous square wave signal sent by the master equipment from the bus; acquiring a slave high-frequency synchronous square wave signal of the slave equipment; determining phase adjustment information of a carrier of the slave equipment according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; and adjusting the carrier of the slave equipment according to the phase adjustment information.
In the embodiment of the present invention, a CPLD (Complex Programmable Logic Device) operation chip of a slave Device determines phase adjustment information of a carrier of the slave Device according to a master high-frequency synchronous square wave signal and a slave high-frequency synchronous square wave signal by acquiring the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal, and transmits a direction adjustment signal carrying the phase adjustment information to an MCU main control chip of the slave Device, where the MCU main control chip adjusts the carrier of the slave Device according to the direction adjustment signal to synchronize the slave carrier with the master carrier, and the phase adjustment information is determined by the CPLD operation chip, and the MCU main control chip does not need to capture the square wave signal of the master Device, that is, master-slave synchronization can be achieved without a capture port of the MCU main control chip.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for implementing high frequency carrier synchronization according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of determining a phase difference between a master high-frequency synchronous square wave signal and a slave high-frequency synchronous square wave signal according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a CPLD chip of a slave device transmitting phase adjustment information to an MCU master control chip of the slave device in an embodiment of the present invention;
fig. 4 is a schematic flow chart of another implementation method of high frequency carrier synchronization in the embodiment of the present invention;
fig. 5 is a flowchart illustrating a method for implementing high frequency carrier synchronization according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of a slave device in an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a CPLD operation chip of the slave device in the embodiment of the present invention;
fig. 8 is a schematic structural diagram of a phase difference determination module in a CPLD operation chip of the slave device in the embodiment of the present invention;
fig. 9 is a schematic structural diagram of a phase adjustment information determination module in a CPLD operation chip of the slave device in the embodiment of the present invention;
fig. 10 is a schematic structural diagram of a system for implementing high frequency carrier synchronization in an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Referring to fig. 1, fig. 1 is a schematic flowchart of a method for implementing high frequency carrier synchronization in an embodiment of the present invention, where the method includes:
step S101: and the CPLD operation chip of the slave equipment acquires the host high-frequency synchronous square wave signal sent by the host equipment from the bus.
Optionally, the bus may be a 485 bus, an IIC bus, or the like.
And the host high-frequency synchronous square wave signal is sent out by an MCU main control chip of the host equipment.
The host high-frequency synchronous square wave signal and the carrier of the host equipment have a corresponding relation, and the detected moment of the rising edge or the falling edge of the host high-frequency synchronous square wave signal is the zero-crossing moment of the carrier of the host equipment.
Step S102: and the CPLD operation chip of the slave equipment acquires a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment.
The slave high-frequency synchronous square wave signal and the carrier of the slave device have a corresponding relationship, and the time when the rising edge or the falling edge of the slave high-frequency synchronous square wave signal is detected is the time when the carrier of the slave device crosses the zero point.
Step S103: and the CPLD operation chip of the slave equipment determines the phase adjustment information of the carrier of the slave equipment according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal.
Optionally, the CPLD operation chip of the slave device may determine a phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; and determining the phase adjustment information of the carrier of the slave equipment according to the phase difference.
Optionally, the CPLD operation chip of the slave device may obtain a first time when a rising edge of the slave high-frequency synchronous square wave signal is detected and a second time when a rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal is detected; and determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the time difference between the second moment and the first moment.
In a specific implementation, the CPLD operation chip of the slave device may set a counter of the CPLD operation chip of the slave device to the following counting manner: and when the rising edge of the host high-frequency synchronous square wave signal is detected, the counter of the CPLD operation chip starts counting from zero, and is reset and starts counting again when the next rising edge of the host high-frequency synchronous square wave signal is detected. The CPLD operation chip of the slave device can acquire a first time when the rising edge of the slave high-frequency synchronous square wave signal is detected and a second time when the rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal is detected by reading the numerical value of the counter, and determine the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the first numerical value of the counter corresponding to the first time and the second numerical value of the counter corresponding to the second time. And determining that the second value is 0 or the last value before the counter is cleared according to a counting rule of the counter, wherein if the first time occurs before the second time, the last value before the counter is cleared is used as the second value, and if the first time occurs after the second time, 0 is used as the second value.
For example, as shown in fig. 2, fig. 2 is a schematic diagram of determining a phase difference between a master high-frequency synchronous square wave signal and a slave high-frequency synchronous square wave signal according to an embodiment of the present invention. In fig. 2, when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the counter starts counting, and is cleared when the next rising edge of the master high-frequency synchronous square wave signal is detected, so as to obtain a maximum reading Tm before the counter is cleared, and when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the CPLD operation chip of the slave device obtains a reading t1 of the counter. There are two cases of phase difference, where Tm is the second value t2 and Tm-t1 when the first time occurs before the second time, and Tm 2 and 0 when the first time occurs after the second time, and the phase difference is t 1.
Optionally, the phase adjustment information is determined by the phase difference, and if the phase difference is smaller than T/2, the CPLD operation chip of the slave device determines that the phase adjustment information of the carrier of the slave device is adjusted in advance; otherwise, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment; and the T is the duration of a high-level signal of the high-frequency synchronous square wave signal of the host in one high-frequency synchronous square wave signal period.
In a specific implementation, the CPLD operation chip of the slave device may determine the T by reading a value of the counter, and may use a third value of the counter when the falling edge of the master high-frequency synchronous square-wave signal is detected as a duration T of a high-level signal of the master high-frequency synchronous square-wave signal of the master device within one high-frequency synchronous square-wave signal period.
In a further implementation, an adjustment threshold may be set to avoid continuous adjustment of the carrier of the slave device, that is, when the phase difference is small, the carrier of the slave device is not adjusted, that is, the phase adjustment information is determined by the phase difference and the preset threshold. If the phase difference is greater than a preset threshold and smaller than T/2, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is advanced adjustment; and if the phase difference is greater than or equal to T/2 and smaller than the difference between T and the preset threshold, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment.
Step S104: and the CPLD operation chip of the slave equipment transmits the direction adjusting signal carrying the phase adjusting information to the MCU main control chip of the slave equipment.
Optionally, the CPLD operation chip of the slave device transmits the direction signal carrying the phase adjustment information to the MCU main control chip of the slave device through an adjustment direction indicator line.
In a specific implementation, the CPLD operation chip of the slave device transmits a high level signal or a low level signal on the adjustment direction indication line to transmit the phase adjustment information to the MCU main control chip of the slave device, as shown in fig. 3, in fig. 3, two adjusting direction indicating lines are arranged between the MCU main control chip of the slave device and the CPLD operation chip of the slave device, when the CPLD operation chip of the slave device determines that the phase adjustment information of the carrier of the slave device is the advanced adjustment, 01 is sent to the MCU main control chip of the slave device, when the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier wave of the slave equipment is lag adjustment, the phase adjustment information is sent to an MCU main control chip of the slave equipment 10, and when the CPLD operation chip of the slave equipment determines that the carrier of the slave equipment is not regulated, 00 or 11 is sent to the MCU main control chip of the slave equipment.
Step S105: and the MCU main control chip of the slave equipment adjusts the carrier of the slave equipment according to the direction adjusting signal.
Specifically, after the MCU main control chip of the slave device acquires the direction indication signal from the adjustment direction indication line, the MCU main control chip adjusts the carrier of the slave device according to the direction indication signal.
In the embodiment of the invention, the CPLD operation chip of the slave device determines the phase adjustment information of the carrier wave of the slave device according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal by acquiring the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal, and transmits the direction adjustment signal carrying the phase adjustment information to the MCU main control chip of the slave device, the MCU main control chip adjusts the carrier wave of the slave device according to the direction adjustment signal to realize the synchronization of the slave carrier wave and the master carrier wave, the phase adjustment information is determined by the CPLD operation chip, the MCU main control chip is not required to capture the square wave signal of the master device, namely, the master-slave synchronization can be realized under the condition that the MCU main control chip does not have a capture.
Referring to fig. 4 again, fig. 4 is a schematic flowchart of another implementation method for high frequency carrier synchronization in the embodiment of the present invention, where the method includes:
step S201: and the CPLD operation chip of the slave equipment acquires the master high-frequency synchronous square wave signal sent by the master equipment from the bus and records each moment when the rising edge of the master high-frequency synchronous square wave signal is detected.
Optionally, the bus may be a 485 bus, an IIC bus, or the like.
And the host high-frequency synchronous square wave signal is sent out by an MCU main control chip of the host equipment.
The host high-frequency synchronous square wave signal and the carrier of the host equipment have a corresponding relation, and the detected moment of the rising edge or the falling edge of the host high-frequency synchronous square wave signal is the zero-crossing moment of the carrier of the host equipment.
Optionally, the CPLD operation chip of the slave device may record each time when the rising edge of the master high-frequency synchronous square wave signal is detected by reading the value of the counter of the CPLD operation chip of the slave device.
Step S202: and the CPLD operation chip of the slave equipment acquires a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment and records the first moment of detecting the rising edge of the slave high-frequency synchronous square wave signal.
The slave high-frequency synchronous square wave signal and the carrier of the slave device have a corresponding relationship, and the time when the rising edge or the falling edge of the slave high-frequency synchronous square wave signal is detected is the time when the zero-crossing point of the high-frequency carrier of the slave device is detected.
Optionally, the CPLD operation chip of the slave device may read a value of a counter of the CPLD operation chip of the slave device to detect a first time of a rising edge of the slave high-frequency synchronous square wave signal.
Step S203: and the CPLD operation chip of the slave equipment determines the second moment of the rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal from the moments.
Step S204: and determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the time difference between the second moment and the first moment.
In a specific implementation, the CPLD operation chip of the slave device may set a counter of the CPLD operation chip of the slave device to the following counting manner: and when the rising edge of the host high-frequency synchronous square wave signal is detected, the counter of the CPLD operation chip starts counting from zero, and is reset and starts counting again when the next rising edge of the host high-frequency synchronous square wave signal is detected.
The CPLD operation chip of the slave device may determine the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the first value of the counter corresponding to the first time and the second value of the counter corresponding to the second time. And determining that the second value is 0 or the last value before the counter is cleared according to a counting rule of the counter, wherein if the first time occurs before the second time, the last value before the counter is cleared is used as the second value, and if the first time occurs after the second time, 0 is used as the second value.
For example, as shown in fig. 2, fig. 2 is a schematic diagram of determining a phase difference between a master high-frequency synchronous square wave signal and a slave high-frequency synchronous square wave signal according to an embodiment of the present invention. In fig. 2, when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the counter starts counting, and is cleared when the next rising edge of the master high-frequency synchronous square wave signal is detected, so as to obtain a maximum reading Tm before the counter is cleared, and when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the CPLD operation chip of the slave device obtains a reading t1 of the counter. There are two cases of the phase difference, that is, Tm-t1 when the first time occurs before the second time, Tm 2 is 0 when the first time occurs after the second time, and t 1.
Step S205: and the CPLD operation chip of the slave equipment determines the phase adjustment information of the carrier of the slave equipment according to the phase difference.
Optionally, if the phase difference is smaller than T/2, the CPLD operation chip of the slave device determines that the phase adjustment information of the carrier of the slave device is an advanced adjustment; otherwise, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment; and the T is the duration of a high-level signal of the high-frequency synchronous square wave signal of the host in one high-frequency synchronous square wave signal period.
In a specific implementation, the CPLD operation chip of the slave device may determine the T by reading a value of the counter, and may use a third value of the counter when the falling edge of the master high-frequency synchronous square wave signal is detected as a duration T of a high-level signal of the master high-frequency synchronous square wave signal lasting within a period of the high-frequency synchronous square wave signal.
In a further implementation, an adjustment threshold may be set to avoid continuous adjustment of the carrier of the slave device, that is, when the phase difference is small, the carrier of the slave device is not adjusted, that is, the phase adjustment information is determined by the phase difference and the preset threshold. If the phase difference is greater than a preset threshold and smaller than T/2, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is advanced adjustment; and if the phase difference is greater than or equal to T/2 and smaller than the difference between T and the preset threshold, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment.
Step S206: and the CPLD operation chip of the slave equipment transmits the direction adjusting signal carrying the phase adjusting information to the MCU main control chip of the slave equipment.
Optionally, the CPLD operation chip of the slave device transmits the direction signal carrying the phase adjustment information to the MCU main control chip of the slave device through an adjustment direction indicator line.
In a specific implementation, the CPLD operation chip of the slave device transmits a high level signal or a low level signal on the adjustment direction indication line to transmit the phase adjustment information to the MCU main control chip of the slave device, as shown in fig. 3, in fig. 3, two adjusting direction indicating lines are arranged between the MCU main control chip of the slave device and the CPLD operation chip of the slave device, when the CPLD operation chip of the slave device determines that the phase adjustment information of the carrier of the slave device is the advanced adjustment, 01 is sent to the MCU main control chip of the slave device, when the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier wave of the slave equipment is lag adjustment, the phase adjustment information is sent to an MCU main control chip of the slave equipment 10, and when the CPLD operation chip of the slave equipment determines that the carrier of the slave equipment is not regulated, 00 or 11 is sent to the MCU main control chip of the slave equipment.
Step S207: and the MCU main control chip of the slave equipment adjusts the carrier of the slave equipment according to the direction adjusting signal.
Specifically, after the MCU main control chip of the slave device acquires the direction indication signal from the adjustment direction indication line, the MCU main control chip adjusts the carrier of the slave device according to the direction indication signal.
In the embodiment of the present invention, a CPLD operation chip of a slave device acquires a master high-frequency synchronous square wave signal and records each time when a rising edge of the master high-frequency synchronous square wave signal is detected, acquires a slave high-frequency synchronous square wave signal sent by an MCU master control chip of the slave device and records a first time when a rising edge of the slave high-frequency synchronous square wave signal is detected, determines a second time of the rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal from the times, determines a phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to a time difference between the second time and the first time, thereby determining phase adjustment information of a carrier of the slave device, and transmits a direction adjustment signal carrying the phase adjustment information to the MCU master control chip of the slave device, the MCU main control chip adjusts the carrier of the slave equipment according to the direction adjusting signal so as to realize the synchronization of the slave carrier and the host carrier, the phase adjusting information is determined by the CPLD operation chip, the MCU main control chip is not required to capture the square wave signal of the host, namely, the master-slave synchronization can be realized under the condition that the MCU main control chip does not have a capture port.
Referring to fig. 5 again, fig. 5 is a schematic flowchart of another implementation method for high frequency carrier synchronization in the embodiment of the present invention, where the method includes:
step S301: and the CPLD operation chip of the slave equipment acquires the host high-frequency synchronous square wave signal sent by the host equipment from the bus.
Optionally, the bus may be a 485 bus, an IIC bus, or the like.
And the host high-frequency synchronous square wave signal is sent out by an MCU main control chip of the host equipment.
The host high-frequency synchronous square wave signal and the high-frequency carrier wave of the host equipment have a corresponding relation, and the detected moment of the rising edge or the falling edge of the host high-frequency synchronous square wave signal is the zero-crossing moment of the high-frequency carrier wave of the host equipment.
Step S302: and the CPLD operation chip of the slave equipment acquires a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment.
The slave high-frequency synchronous square wave signal and the high-frequency carrier wave of the slave device have a corresponding relation, and the time when the rising edge or the falling edge of the slave high-frequency synchronous square wave signal is detected represents the time when the high-frequency carrier wave of the slave device crosses the zero point.
Step S303: and the CPLD operation chip of the slave equipment determines the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal.
Optionally, the CPLD operation chip of the slave device may obtain a first time when a rising edge of the slave high-frequency synchronous square wave signal is detected and a second time when a rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal is detected; and determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the time difference between the second moment and the first moment.
In a specific implementation, the CPLD operation chip of the slave device may set a counter of the CPLD operation chip of the slave device to the following counting manner: and when the rising edge of the host high-frequency synchronous square wave signal is detected, the counter of the CPLD operation chip starts counting from zero, and is reset and starts counting again when the next rising edge of the host high-frequency synchronous square wave signal is detected. The CPLD operation chip of the slave device can acquire a first time when the rising edge of the slave high-frequency synchronous square wave signal is detected and a second time when the rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal is detected by reading the numerical value of the counter, and determine the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the first numerical value of the counter corresponding to the first time and the second numerical value of the counter corresponding to the second time. And determining that the second value is 0 or the last value before the counter is cleared according to a counting rule of the counter, wherein if the first time occurs before the second time, the last value before the counter is cleared is used as the second value, and if the first time occurs after the second time, 0 is used as the second value.
For example, as shown in fig. 2, fig. 2 is a schematic diagram of determining a phase difference between a master high-frequency synchronous square wave signal and a slave high-frequency synchronous square wave signal according to an embodiment of the present invention. In fig. 2, when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the counter starts counting, and is cleared when the next rising edge of the master high-frequency synchronous square wave signal is detected, so as to obtain a maximum reading Tm before the counter is cleared, and when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the CPLD operation chip of the slave device obtains a reading t1 of the counter. There are two cases of phase difference, where Tm is the second value t2 and Tm-t1 when the first time occurs before the second time, and Tm 2 and 0 when the first time occurs after the second time, and the phase difference is t 1.
Step S304: and if the phase difference is greater than a preset threshold and smaller than T/2, determining that the phase adjustment information of the carrier of the slave equipment is advanced adjustment by the CPLD operation chip of the slave equipment, wherein T is the duration of a high-level signal of the master high-frequency synchronous square wave signal in a high-frequency synchronous square wave signal period.
In a specific implementation, the CPLD operation chip of the slave device may determine the T by reading a value of the counter, and may use a third value of the counter when the falling edge of the master high-frequency synchronous square wave signal is detected as a duration T of a high-level signal of the master high-frequency synchronous square wave signal lasting within a period of the high-frequency synchronous square wave signal.
The preset threshold is an adjusting threshold with a smaller adjusting threshold.
Step S305: and if the phase difference is greater than or equal to T/2 and smaller than the difference between T and the preset threshold, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment.
Step S306: and the CPLD operation chip of the slave equipment transmits the direction adjusting signal carrying the phase adjusting information to the MCU main control chip of the slave equipment.
Optionally, the CPLD operation chip of the slave device transmits the direction signal carrying the phase adjustment information to the MCU main control chip of the slave device through an adjustment direction indicator line.
In a specific implementation, the CPLD operation chip of the slave device transmits a high level signal or a low level signal on the adjustment direction indication line to transmit the phase adjustment information to the MCU main control chip of the slave device, as shown in fig. 3, in fig. 3, two adjusting direction indicating lines are arranged between the MCU main control chip of the slave device and the CPLD operation chip of the slave device, when the CPLD operation chip of the slave device determines that the phase adjustment information of the carrier of the slave device is the advanced adjustment, 01 is sent to the MCU main control chip of the slave device, when the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier wave of the slave equipment is lag adjustment, the phase adjustment information is sent to an MCU main control chip of the slave equipment 10, and when the CPLD operation chip of the slave equipment determines that the carrier of the slave equipment is not regulated, 00 or 11 is sent to the MCU main control chip of the slave equipment.
Step S307: and the MCU main control chip of the slave equipment adjusts the carrier of the slave equipment according to the direction adjusting signal.
Specifically, after the MCU main control chip of the slave device acquires the direction indication signal from the adjustment direction indication line, the MCU main control chip adjusts the carrier of the slave device according to the direction indication signal.
In the embodiment of the invention, a CPLD operation chip of slave equipment determines the phase difference of a carrier of the slave equipment according to a master high-frequency synchronous square wave signal and a slave high-frequency synchronous square wave signal by acquiring the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal, compares the phase difference with a carrier period T and a preset threshold of a master, determines that the phase adjustment information of the carrier of the slave equipment is advanced adjustment if the phase difference is greater than the preset threshold and smaller than T/2, determines that the phase adjustment information of the carrier of the slave equipment is lag adjustment if the phase difference is greater than or equal to T/2 and smaller than the difference between T and the preset threshold, transmits a direction adjustment signal carrying the phase adjustment information to an MCU main control chip of the slave equipment, and the MCU main control chip adjusts the carrier of the slave equipment according to the direction adjustment signal to realize the identity of the slave carrier and the master carrier The phase adjustment information is determined by the CPLD operation chip, the MCU master control chip is not required to capture the square wave signal of the host, namely, master-slave synchronization can be realized under the condition that the MCU master control chip does not have a capture port, and the setting of the preset threshold value can avoid continuous adjustment of the carrier of the slave equipment.
Referring to fig. 6, fig. 6 is a schematic diagram of a component structure of a slave device in an embodiment of the present invention, where the slave device at least includes:
the CPLD operation chip 410 is used for acquiring a host high-frequency synchronous square wave signal sent by the host device from the bus.
Optionally, the bus may be a 485 bus, an IIC bus, or the like.
And the host high-frequency synchronous square wave signal is sent out by an MCU main control chip of the host equipment.
The host high-frequency synchronous square wave signal has a corresponding relation with the carrier of the host device, and the detected time of the rising edge or the falling edge of the host high-frequency synchronous square wave signal is the zero-crossing time of the carrier of the host device.
The CPLD operation chip 410 is further configured to obtain a slave high-frequency synchronous square wave signal sent by the MCU main control chip 420 of the slave device.
The slave high-frequency synchronous square wave signal has a corresponding relation with the carrier of the slave device, and the time when the rising edge or the falling edge of the slave high-frequency synchronous square wave signal is detected is the time when the carrier of the slave device crosses the zero point.
The CPLD operation chip 410 is further configured to determine phase adjustment information of a carrier of the slave device according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal.
Optionally, as shown in fig. 7, the CPLD operation chip 410 may include:
the phase difference determining module 411 is configured to determine a phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal.
Optionally, as shown in fig. 8, the phase difference determining module 411 may include:
a first time obtaining unit 4111, configured to obtain a first time when a rising edge of the slave high-frequency synchronous square wave signal is detected.
Optionally, the first time obtaining unit 4111 may obtain the first time when the rising edge of the slave high-frequency synchronous square wave signal is detected by reading the value of the counter.
A second time obtaining unit 4112, configured to obtain a second time when a rising edge of the master high-frequency synchronous square wave signal closest to a rising edge of the slave high-frequency synchronous square wave signal is detected.
Optionally, the second time obtaining unit 4112 may obtain, by reading the value of the counter, a second time at which a rising edge of the master high-frequency synchronous square wave signal closest to a rising edge of the slave high-frequency synchronous square wave signal is detected in a manner of reading the value.
In a specific implementation, the CPLD operation chip 410 of the slave device may set a counter of the CPLD operation chip 410 of the slave device to the following counting manner: the counter of the CPLD operation chip 410 starts counting from zero when the rising edge of the host high-frequency synchronous square wave signal is detected, and is cleared and starts counting again when the next rising edge of the host high-frequency synchronous square wave signal is detected.
A phase difference determining unit 4113, configured to determine a phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to a time difference between the second time and the first time.
The phase difference determining unit 4113 determines a phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal according to a first value of a counter corresponding to the first time and a second value of a counter corresponding to the second time. And determining that the second value is 0 or the last value before the counter is cleared according to a counting rule of the counter, wherein if the first time occurs before the second time, the last value before the counter is cleared is used as the second value, and if the first time occurs after the second time, 0 is used as the second value.
For example, as shown in fig. 2, fig. 2 is a schematic diagram of determining a phase difference between a master high-frequency synchronous square wave signal and a slave high-frequency synchronous square wave signal according to an embodiment of the present invention. In fig. 2, when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the counter starts counting, and is cleared when the next rising edge of the master high-frequency synchronous square wave signal is detected, so as to obtain a maximum reading Tm before the counter is cleared, and when the CPLD operation chip of the slave device detects a rising edge of the master high-frequency synchronous square wave signal, the CPLD operation chip of the slave device obtains a reading t1 of the counter. There are two cases of phase difference, where Tm is the second value t2 and Tm-t1 when the first time occurs before the second time, and Tm 2 and 0 when the first time occurs after the second time, and the phase difference is t 1.
And a phase adjustment information determining module 412, configured to determine phase adjustment information of a carrier of the slave device according to the phase difference.
Optionally, as shown in fig. 9, the phase adjustment information determining module 412 may include:
an advance adjustment determining unit 4121, configured to determine that the phase adjustment information of the carrier of the slave device is an advance adjustment if the phase difference is smaller than T/2, where T is a duration of a high-level signal of the master high-frequency synchronous square wave signal lasting within one high-frequency synchronous square wave signal period.
In a specific implementation, the CPLD operation chip 410 of the slave device may determine the T by reading a value of the counter, and may use a third value of the counter when the falling edge of the master high-frequency synchronous square wave signal is detected as a duration T of a high-level signal of the master high-frequency synchronous square wave signal in a period of the high-frequency synchronous square wave signal in a carrier period of the master device.
A hysteresis adjustment determining unit 4122 for determining the phase adjustment information of the carrier of the slave device as hysteresis adjustment.
Optionally, an adjustment threshold may be set to avoid continuous adjustment of the carrier of the slave device, that is, when the phase difference is small, the carrier of the slave device is not adjusted, that is, the advance adjustment determining unit 4121 is specifically configured to: if the phase difference is larger than a preset threshold and smaller than T/2, determining that the phase adjustment information of the carrier of the slave equipment is advanced adjustment; the hysteresis adjustment determination unit 4122 is specifically configured to: and if the phase difference is greater than or equal to T/2 and smaller than the difference between T and the preset threshold, determining that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment.
The CPLD operation chip 410 is further configured to transmit a direction adjustment signal carrying the phase adjustment information to the MCU main control chip.
Optionally, the CPLD operation chip 410 transmits a direction signal carrying the phase adjustment information to the MCU main control chip 420 of the slave device through an adjustment direction indicator line.
In a specific implementation, the CPLD operation chip 410 of the slave device transmits a high level signal or a low level signal on the adjustment direction indication line to transmit the phase adjustment information to the MCU main control chip of the slave device, as shown in fig. 3, in fig. 3, two adjusting direction indicating lines are arranged between the MCU main control chip of the slave device and the CPLD operation chip of the slave device, when the CPLD operation chip of the slave device determines that the phase adjustment information of the carrier of the slave device is the advanced adjustment, 01 is sent to the MCU main control chip of the slave device, when the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier wave of the slave equipment is lag adjustment, the phase adjustment information is sent to an MCU main control chip of the slave equipment 10, and when the CPLD operation chip of the slave equipment determines that the carrier of the slave equipment is not regulated, 00 or 11 is sent to the MCU main control chip of the slave equipment.
And the MCU main control chip 420 is used for adjusting the carrier of the slave device according to the direction adjusting signal.
Specifically, after the MCU main control chip 420 of the slave device obtains the direction indication signal from the adjustment direction indication line, the carrier of the slave device is adjusted according to the direction indication signal.
In the embodiment of the invention, the CPLD operation chip of the slave device determines the phase adjustment information of the carrier of the slave device according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal by acquiring the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal, and transmits the direction adjustment signal carrying the phase adjustment information to the MCU main control chip of the slave device, the MCU main control chip adjusts the carrier of the slave device according to the direction adjustment signal to realize the synchronization of the slave carrier and the master carrier, the phase adjustment information is determined by the CPLD operation chip, the MCU main control chip is not required to capture the square wave signal of the master device, and the master-slave synchronization can be realized under the condition that the MCU main control chip does not have a capture port.
Fig. 10 is a schematic structural diagram of a system for implementing high frequency carrier synchronization in an embodiment of the present invention, where the system includes a slave device 510, a bus 520, and a master device 530, where:
in an embodiment, the slave device 510 is the slave device described in the foregoing embodiment of the present invention with reference to fig. 6;
the host device 530 is configured to send a host high-frequency synchronous square wave signal onto the bus 520;
the slave device 510 is configured to obtain a master high-frequency synchronous square wave signal sent by the master device from the bus; acquiring a slave high-frequency synchronous square wave signal of the slave equipment; determining phase adjustment information of a carrier of the slave equipment according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; and adjusting the carrier of the slave equipment according to the phase adjustment information.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (6)
1. A method for realizing high-frequency carrier synchronization is characterized in that the method comprises the following steps:
a CPLD operation chip of the slave equipment acquires a host high-frequency synchronous square wave signal sent by an MCU main control chip of the host equipment from a bus;
the CPLD operation chip of the slave equipment acquires a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment;
the CPLD operation chip of the slave equipment acquires the first moment of detecting the rising edge of the slave high-frequency synchronous square wave signal, and acquires the reading t1 of the counter;
the CPLD operation chip of the slave equipment clears the counter at the next rising edge of the master high-frequency synchronous square wave signal to obtain the maximum reading Tm of the counter before clearing;
the CPLD operation chip of the slave equipment acquires a second moment of detecting the rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal;
when the first time is before the second time, determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal to be Tm-t 1;
when the first time occurs after the second time, determining that the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal is t 1;
determining phase adjustment information of a carrier of the slave equipment according to the phase difference and T/2 of the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; the T is the duration of a high-level signal of the host high-frequency synchronous square wave signal in a high-frequency synchronous square wave signal period;
the CPLD operation chip of the slave equipment transmits a direction adjusting signal carrying the phase adjusting information to an MCU main control chip of the slave equipment through an adjusting direction indicating line, wherein the direction adjusting signal comprises 01 or 10; wherein 01 represents that the phase adjustment information of the carrier of the slave device is advance adjustment, and 10 represents that the phase adjustment information of the carrier of the slave device is lag adjustment;
and the MCU main control chip of the slave equipment adjusts the carrier of the slave equipment according to the direction adjusting signal.
2. The method according to claim 1, wherein the determining phase adjustment information of the carrier of the slave device according to the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal and T/2 comprises:
if the phase difference is smaller than T/2, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is advanced adjustment;
otherwise, the CPLD operation chip of the slave device determines that the phase adjustment information of the carrier of the slave device is hysteresis adjustment.
3. The method for implementing high-frequency carrier synchronization according to claim 2, wherein if the phase difference is smaller than T/2, the determining, by the CPLD operation chip of the slave device, that the phase adjustment information of the carrier of the slave device is adjusted in advance includes:
if the phase difference is greater than a preset threshold and smaller than T/2, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is advanced adjustment;
if not, the step of determining that the phase adjustment information of the slave high-frequency square wave signal is the hysteresis adjustment by the CPLD operation chip of the slave device comprises the following steps:
and if the phase difference is greater than or equal to T/2 and smaller than the difference between T and the preset threshold, the CPLD operation chip of the slave equipment determines that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment.
4. A slave device, characterized in that the slave device comprises:
the CPLD operation chip is used for acquiring a host high-frequency synchronous square wave signal sent by the MCU main control chip of the host equipment from the bus;
the CPLD operation chip is also used for acquiring a slave high-frequency synchronous square wave signal sent by the MCU master control chip of the slave equipment;
the CPLD operation chip is also used for acquiring the first moment of detecting the rising edge of the slave high-frequency synchronous square wave signal, and a counter starts counting when the rising edge of the master high-frequency synchronous square wave signal is detected, so as to acquire the reading t1 of the counter;
the CPLD operation chip is also used for resetting the counter when the next rising edge of the host high-frequency synchronous square wave signal is reached, and obtaining the maximum reading Tm of the counter before resetting;
the CPLD operation chip is also used for acquiring a second moment, wherein the second moment is the moment when the CPLD operation chip detects the rising edge of the master high-frequency synchronous square wave signal closest to the rising edge of the slave high-frequency synchronous square wave signal;
the CPLD operation chip is also used for determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal to be Tm-t1 under the condition that the first moment is before the second moment;
the CPLD operation chip is also used for determining the phase difference between the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal as t1 under the condition that the first moment occurs after the second moment;
the CPLD operation chip is also used for determining the phase adjustment information of the carrier of the slave equipment according to the phase difference and T/2 of the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; the T is the duration of a high-level signal of the host high-frequency synchronous square wave signal in a high-frequency synchronous square wave signal period;
the CPLD operation chip is also used for transmitting a direction adjusting signal carrying the phase adjusting information to the MCU main control chip by adjusting a direction indicating line, and the direction adjusting signal comprises 01 or 10; wherein 01 represents that the phase adjustment information of the carrier of the slave device is advance adjustment, and 10 represents that the phase adjustment information of the carrier of the slave device is lag adjustment;
and the MCU main control chip is used for adjusting the carrier of the slave equipment according to the direction adjusting signal.
5. The slave device of claim 4, wherein the phase adjustment information determination module comprises:
an advance adjustment determining unit, configured to determine that phase adjustment information of a carrier of the slave device is advance adjustment if the phase difference is smaller than T/2;
and the hysteresis adjustment determining unit is used for determining that the phase adjustment information of the carrier of the slave equipment is hysteresis adjustment.
6. A system for implementing high frequency carrier synchronization, comprising the slave device, the bus and the master device according to any one of claims 4 to 5, wherein:
the host equipment is used for sending a host high-frequency synchronous square wave signal to the bus;
the slave equipment is used for acquiring a master high-frequency synchronous square wave signal sent by the master equipment from the bus; acquiring a slave high-frequency synchronous square wave signal of the slave equipment; determining phase adjustment information of a carrier of the slave equipment according to the master high-frequency synchronous square wave signal and the slave high-frequency synchronous square wave signal; and adjusting the carrier of the slave equipment according to the phase adjustment information.
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| PCT/CN2017/100470 WO2019046999A1 (en) | 2017-09-05 | 2017-09-05 | Method for realizing high-frequency carrier synchronization, and related apparatus |
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| CN116455545B (en) * | 2023-06-16 | 2023-09-12 | 惠州市乐亿通科技有限公司 | Signal synchronization method, device and system |
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