CN110235394A - A kind of implementation method and relevant apparatus that high frequency carrier is synchronous - Google Patents
A kind of implementation method and relevant apparatus that high frequency carrier is synchronous Download PDFInfo
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- CN110235394A CN110235394A CN201780084715.1A CN201780084715A CN110235394A CN 110235394 A CN110235394 A CN 110235394A CN 201780084715 A CN201780084715 A CN 201780084715A CN 110235394 A CN110235394 A CN 110235394A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
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- H04J3/06—Synchronising arrangements
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The embodiment of the present invention provides a kind of implementation method and relevant apparatus that high frequency carrier is synchronous.A kind of implementation method that high frequency carrier is synchronous, comprising: the CPLD operation chip of slave devices obtains the host high-frequency synchronous square-wave signal of host equipment transmission from bus；The CPLD operation chip of the slave devices obtains the slave high-frequency synchronous square-wave signal that the MCU main control chip of the slave devices is sent；The CPLD operation chip of the slave devices determines the phase adjusted information of the carrier wave of the slave devices according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices by the CPLD operation chip of the slave devices；The MCU main control chip of the slave devices is adjusted the carrier wave of the slave devices according to the direction adjustment signal.Technical solution of the present invention can realize master-slave synchronisation in the case where MCU main control chip does not have capture mouth.
Description
The present invention relates to field of communication technology more particularly to a kind of high frequency carrier synchronous implementation methods and relevant apparatus.
In inverter or DC source application, in order to expand capacity usually the equipment parallel connection of N platform, play the role of expanding capacity, parallel connection can increase the capacity of system, but can bring circulation problem, and circulation can make the efficiency of system reduce and increase system loss.High frequency carrier synchronization can effectively reduce circulation, the synchronous implementation method of high frequency carrier is relatively more, common method is the square-wave signal of host generation and carrier wave same frequency, slave captures the edge signal of square wave using capture mouth, to judge the phase difference between slave and host, the carrier cycle of adjustment slave realizes that slave follows host, to realize master-slave synchronisation.
Need to control chip MCU (Micro Controller Unit using the above method, microcontroller unit) there is capturing function, the relatively small number of MCU main control chip of resources of chip can be used sometimes based upon cost consideration, do not have the MCU main control chip of capture mouth, the MCU main control chip for not capturing mouth cannot achieve master-slave synchronisation.
Summary of the invention
The embodiment of the present invention provides a kind of implementation method and relevant apparatus that high frequency carrier is synchronous, can realize master-slave synchronisation in the case where MCU main control chip does not have capture mouth.
First aspect of the embodiment of the present invention provides a kind of implementation method that high frequency carrier is synchronous, which comprises
The CPLD operation chip of slave devices obtains the host high-frequency synchronous square-wave signal of host equipment transmission from bus；
The CPLD operation chip of the slave devices obtains the slave high-frequency synchronous square-wave signal that the MCU main control chip of the slave devices is sent；
The CPLD operation chip of the slave devices determines the phase adjusted information of the carrier wave of the slave devices according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；
The direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices by the CPLD operation chip of the slave devices；
The MCU main control chip of the slave devices is adjusted the carrier wave of the slave devices according to the direction adjustment signal.
In a kind of possible design, the CPLD operation chips of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices includes: that the CPLD operation chip of the slave devices determines according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The CPLD operation chip of the slave devices determines the phase adjusted information of the carrier wave of the slave devices according to the phase difference.
In a kind of possible design, the CPLD operation chips of the slave devices determines that the phase difference of the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal includes: according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal
The CPLD operation chip of the slave devices obtains the first moment for detecting the rising edge of the slave high-frequency synchronous square-wave signal；The CPLD operation chip of the slave devices obtains the second moment for detecting the rising edge of the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal；The phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal is determined according to the time difference at second moment and first moment.
In a kind of possible design, if the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices includes: that the phase difference is less than T/2 according to the phase difference, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；Otherwise, then the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag；Wherein, the duration T lasting within a high-frequency synchronous square-wave signal period for the high level signal of the host high-frequency synchronous square-wave signal.
In a kind of possible design, if the phase difference is less than T/2, if then the CPLD operation chip of the slave devices confirms that the phase adjusted information of the carrier wave of the slave devices is that load regulation includes: the phase difference greater than preset threshold and is less than T/2, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；It is described otherwise, then the CPLD operation chip of the slave devices determines the phase adjusted information of the slave high-frequency square-wave signal for lag
If adjusting includes: that the phase difference is more than or equal to T/2 and is less than the difference of T and the preset threshold, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag.
Correspondingly, second aspect of the embodiment of the present invention provides a kind of slave devices, and the slave devices include:
CPLD operation chip, the host high-frequency synchronous square-wave signal sent for obtaining host equipment from bus；
The CPLD operation chip is also used to obtain the slave high-frequency synchronous square-wave signal that the MCU main control chip of the slave devices is sent；
The CPLD operation chip is also used to determine the phase adjusted information of the carrier wave of the slave devices according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；
The CPLD operation chip is also used to the direction adjustment signal for carrying the phase adjusted information being transferred to MCU main control chip；
MCU main control chip, for the carrier wave of the slave devices to be adjusted according to the direction adjustment signal.
In a kind of possible design, the CPLD operation chip includes: phase difference determining module, for determining the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；Phase adjusted information determination module, the phase adjusted information of the carrier wave for determining the slave devices according to the phase difference.
In a kind of possible design, the phase difference determining module includes: the first moment acquiring unit, for obtaining the first moment for detecting the rising edge of the slave high-frequency synchronous square-wave signal；Second moment acquiring unit, for obtaining the second moment for detecting the rising edge of the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal；Phase difference determination unit, for determining the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the time difference at second moment and first moment.
In a kind of possible design, the phase adjusted information determination module includes: load regulation determination unit, if being less than T/2 for the phase difference, it is determined that the phase adjusted information of the carrier wave of the slave devices is load regulation；Lag adjusts determination unit, for determining that the phase adjusted information of carrier wave of the slave devices is adjusted for lag；Wherein, the duration T lasting within a high-frequency synchronous square-wave signal period for the high level signal of the host high-frequency synchronous square-wave signal.
The third aspect of the embodiment of the present invention provides a kind of realization system that high frequency carrier is synchronous, the slave devices, bus and the host equipment provided including first aspect of the embodiment of the present invention, in which:
The host equipment is used to send the bus for host high-frequency synchronous square-wave signal；
The host high-frequency synchronous square-wave signal that the slave devices are sent for obtaining host equipment from bus；Obtain the slave high-frequency synchronous square-wave signal of the slave devices；The phase adjusted information of the carrier wave of the slave devices is determined according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The carrier wave of the slave devices is adjusted according to the phase adjusted information.
CPLD (the Complex Programmable Logic Device of slave devices in the embodiment of the present invention, Complex Programmable Logic Devices) operation chip is by obtaining host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal, the phase adjusted information of the carrier wave of slave devices is determined according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal, and the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices, the MCU main control chip is adjusted the carrier wave of the slave devices according to the direction adjustment signal to realize that slave carrier wave is synchronous with host carrier wave, phase adjusted information is determined by CPLD operation chip, MCU main control chip capture host is not needed Master-slave synchronisation may be implemented in the case where MCU main control chip does not have capture mouth in square-wave signal.
To describe the technical solutions in the embodiments of the present invention more clearly, the drawings to be used in the embodiments are briefly described below, apparently, drawings in the following description are only some embodiments of the invention, for those of ordinary skill in the art, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the synchronous implementation method of one of embodiment of the present invention high frequency carrier；
Fig. 2 is the schematic diagram that the phase difference of host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal is determined in the embodiment of the present invention；
Fig. 3 is that the CPLD chip of the slave devices in the embodiment of the present invention transmits the schematic diagram of phase adjusted information to the MCU main control chip of slave devices；
Fig. 4 is the flow diagram of the synchronous implementation method of another high frequency carrier in the embodiment of the present invention；
Fig. 5 is the flow diagram of the synchronous implementation method of another high frequency carrier in the embodiment of the present invention；
Fig. 6 is the composed structure schematic diagram of one of embodiment of the present invention slave devices；
Fig. 7 is the CPLD operation chip composition structural schematic diagram of the slave devices in the embodiment of the present invention；
Fig. 8 is the composed structure schematic diagram of the phase difference determining module in the CPLD operation chip of the slave devices in the embodiment of the present invention；
Fig. 9 is the composed structure schematic diagram of the phase adjusted information determination module in the CPLD operation chip of the slave devices in the embodiment of the present invention；
Figure 10 is the composed structure schematic diagram of the synchronous realization system of one of embodiment of the present invention high frequency carrier.
Following will be combined with the drawings in the embodiments of the present invention, and technical scheme in the embodiment of the invention is clearly and completely described, it is clear that the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, every other embodiment obtained by those of ordinary skill in the art without making creative efforts, shall fall within the protection scope of the present invention.
Description and claims of this specification and term " first " in above-mentioned attached drawing, " second ", etc. be to be not use to describe a particular order for distinguishing different objects.In addition, term " includes " and " having " and their any deformations, it is intended that cover and non-exclusive include.Such as it contains the process, method, system, product or equipment of a series of steps or units and is not limited to listed step or unit, but optionally further comprising the step of not listing or unit, or optionally further comprising other step or units intrinsic for these process, methods, product or equipment.
The flow diagram of the synchronous implementation method of one of embodiment of the present invention high frequency carrier referring first to Fig. 1, Fig. 1, as shown in the figure the described method includes:
Step S101: the CPLD operation chip of slave devices obtains the host high-frequency synchronous square-wave signal of host equipment transmission from bus.
Optionally, the bus can be 485 buses, iic bus etc..
Wherein, the host high-frequency synchronous square-wave signal is issued by the MCU main control chip of the host equipment.
Wherein, the carrier wave of the host high-frequency synchronous square-wave signal and the host equipment has corresponding relationship, at the time of detecting the zero crossing of the carrier wave of the as described host equipment at the time of rising edge or failing edge of the host high-frequency synchronous square-wave signal.
Step S102: the CPLD operation chip of the slave devices obtains the slave high-frequency synchronous square-wave signal that the MCU main control chip of the slave devices is sent.
Wherein, the carrier wave of the slave high-frequency synchronous square-wave signal and the slave devices has corresponding relationship, at the time of detecting the zero crossing of the carrier wave of the as described slave devices at the time of rising edge or failing edge of the slave high-frequency synchronous square-wave signal.
Step S103: the CPLD operation chip of the slave devices determines the phase adjusted information of the carrier wave of the slave devices according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal.
Optionally, the CPLD operation chip of the slave devices can determine the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The phase adjusted information of the carrier wave of the slave devices is determined according to the phase difference.
Optionally, the first moment of the available rising edge for detecting the slave high-frequency synchronous square-wave signal of the CPLD operation chip of the slave devices and detect the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal rising edge the second moment；The phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal is determined according to the time difference at second moment and first moment.
In the specific implementation, the CPLD operation chip of the slave devices can set following counting mode for the counter of the CPLD operation chip of the slave devices: when detecting the rising edge of the host high-frequency synchronous square-wave signal, the counter of the CPLD operation chip counts from zero and resets when detecting next rising edge of the host high-frequency synchronous square-wave signal and start counting again.The CPLD operation chip of the slave devices can be obtained by way of reading the numerical value of the counter detect the first moment of the rising edge of the slave high-frequency synchronous square-wave signal and the rising edge that detects the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal second when
It carves, and determines the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the second value of the first numerical value of first moment corresponding counter counter corresponding with second moment.Wherein, it can determine that the second value is the last one numerical value before 0 or the counter O reset according to the counting rule of the counter, if first moment occurred before second moment, then using the last one numerical value before the counter O reset as second value, if first moment occurred after second moment, second value is used as by 0.
For example, as shown in Fig. 2, Fig. 2 is the schematic diagram for determining the phase difference of host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal in the embodiment of the present invention.The rising edge hour counter of the CPLD operation chip detection host high-frequency synchronous square-wave signal of slave devices is started counting and is reset in next rising edge hour counter of the host high-frequency synchronous square-wave signal in Fig. 2, full-scale reading Tm before obtaining counter O reset, the CPLD operation chip of slave devices obtain the reading t1 of counter when detecting the rising edge of host high-frequency synchronous square-wave signal.There are two types of phase difference situations, and when occurring before second moment at first moment, second value t2=Tm, phase difference Tm-t1 occur when after second moment, second value t2=0 when first moment, and the phase difference is t1.
Optionally, the phase adjusted information is determined by the phase difference, if the phase difference is less than T/2, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；Otherwise, then the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag；Wherein, the duration T lasting within a high-frequency synchronous square-wave signal period for the high level signal of the host high-frequency synchronous square-wave signal.
In specific implementation, the CPLD operation chip of the slave devices can determine the T by reading the numerical value of the counter, can will test the third value of the counter when failing edge of the host high-frequency synchronous square-wave signal duration T lasting within a high-frequency synchronous square-wave signal period as the high level signal of the host high-frequency synchronous square-wave signal of the host equipment.
In a further implementation, adjusting threshold value constantly regulate to avoid the carrier wave to slave devices can be set, i.e. when the phase difference is smaller, the carrier wave of the slave devices is not adjusted, i.e., phase adjusted information is determined by the phase difference and preset threshold.If the phase difference is greater than preset threshold and is less than T/2, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；If the phase difference is more than or equal to T/2 and is less than the difference of T and the preset threshold, the CPLD operation chip of the slave devices determines the phase of the carrier wave of the slave devices
Adjusting information is that lag is adjusted.
Step S104: the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices by the CPLD operation chip of the slave devices.
Optionally, the MCU main control chip that the direction signal for carrying the phase adjusted information is transferred to the slave devices by adjusting direction instruction line by the CPLD operation chip of the slave devices.
In specific implementation, the CPLD operation chip of the slave devices transmits the MCU main control chip that the phase adjusted information is transferred to the slave devices by high level signal or low level signal on the adjusting direction instruction line, as shown in Figure 3, there are two adjusting direction instruction lines in Fig. 3 between the MCU main control chip of slave devices and the CPLD operation chip of the slave devices, then when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation, 01 is sent to the MCU main control chip of the slave devices, when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag, 10 are sent to the MCU main control chip of the slave devices, when the CPLD operation chip of slave devices is true When the carrier wave of the fixed slave devices does not have to adjust, the MCU main control chip of Xiang Suoshu slave devices sends 00 or 11.
Step S105: the MCU main control chip of the slave devices is adjusted the carrier wave of the slave devices according to the direction adjustment signal.
Specifically, being adjusted after the MCU main control chip of the slave devices gets the direction instruction signal from the adjusting direction instruction line according to carrier wave of the direction instruction signal to the slave devices.
The CPLD operation chip of slave devices is by obtaining host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal in the embodiment of the present invention, the phase adjusted information of the carrier wave of slave devices is determined according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal, and the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices, the MCU main control chip is adjusted the carrier wave of the slave devices according to the direction adjustment signal to realize that slave carrier wave is synchronous with host carrier wave, phase adjusted information is determined by CPLD operation chip, the square-wave signal of MCU main control chip capture host is not needed, master-slave synchronisation may be implemented in the case where MCU main control chip does not have capture mouth.
Fig. 4 is referred to again, and Fig. 4 is the synchronous realization side of another high frequency carrier in the embodiment of the present invention
The flow diagram of method, as shown in the figure the described method includes:
Step S201: the CPLD operation chip of slave devices obtains the host high-frequency synchronous square-wave signal of host equipment transmission from bus and records each moment for detecting the rising edge of the host high-frequency synchronous square-wave signal.
Optionally, the bus can be the buses such as 485 buses, iic bus.
Wherein, the host high-frequency synchronous square-wave signal is issued by the MCU main control chip of the host equipment.
Wherein, the carrier wave of the host high-frequency synchronous square-wave signal and the host equipment has corresponding relationship, at the time of detecting the zero crossing of the carrier wave of the as described host equipment at the time of rising edge or failing edge of the host high-frequency synchronous square-wave signal.
Optionally, the CPLD operation chip of the slave devices can record each moment for the rising edge for detecting the host high-frequency synchronous square-wave signal by the numerical value of the counter of the CPLD operation chip of the reading slave devices.
Step S202: slave high-frequency synchronous square-wave signal and record that the MCU main control chip that the CPLD operation chip of the slave devices obtains the slave devices is sent detect the first moment of the rising edge of the slave high-frequency synchronous square-wave signal.
Wherein, the carrier wave of the slave high-frequency synchronous square-wave signal and the slave devices has corresponding relationship, at the time of detecting the zero crossing of the high frequency carrier of the as described slave devices at the time of rising edge or failing edge of the slave high-frequency synchronous square-wave signal.
Optionally, the CPLD operation chip of the slave devices can be by the numerical value of the counter of the CPLD operation chip of the reading slave devices come the first moment to the rising edge for detecting the slave high-frequency synchronous square-wave signal.
Step S203: the second moment of the CPLD operation chip of slave devices rising edge of the determining host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal from each moment.
Step S204: the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal is determined according to the time difference at second moment and first moment.
In the specific implementation, the CPLD operation chip of the slave devices can set following counting mode for the counter of the CPLD operation chip of the slave devices: detecting the host high-frequency synchronous
The counter of the CPLD operation chip counts from zero and resets when detecting next rising edge of the host high-frequency synchronous square-wave signal and start counting again when the rising edge of square-wave signal.
The CPLD operation chip of the slave devices can determine the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the second value of the first numerical value counter corresponding with second moment of first moment corresponding counter.Wherein, it can determine that the second value is the last one numerical value before 0 or the counter O reset according to the counting rule of the counter, if first moment occurred before second moment, then using the last one numerical value before the counter O reset as second value, if first moment occurred after second moment, second value is used as by 0.
For example, as shown in Fig. 2, Fig. 2 is the schematic diagram for determining the phase difference of host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal in the embodiment of the present invention.The rising edge hour counter of the CPLD operation chip detection host high-frequency synchronous square-wave signal of slave devices is started counting and is reset in next rising edge hour counter of the host high-frequency synchronous square-wave signal in Fig. 2, full-scale reading Tm before obtaining counter O reset, the CPLD operation chip of slave devices obtain the reading t1 of counter when detecting the rising edge of host high-frequency synchronous square-wave signal.There are two types of phase difference situations, and second value t2=Tm, phase difference Tm-t1 when occurring before second moment at first moment occur when after second moment, second value t2=0 when first moment, and the phase difference is t1.
Step S205: the CPLD operation chip of the slave devices determines the phase adjusted information of the carrier wave of the slave devices according to the phase difference.
Optionally, if the phase difference is less than T/2, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；Otherwise, then the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag；Wherein, the duration T lasting within a high-frequency synchronous square-wave signal period for the high level signal of the host high-frequency synchronous square-wave signal.
In specific implementation, the CPLD operation chip of the slave devices can determine the T by reading the numerical value of the counter, can will test the third value of the counter when failing edge of the host high-frequency synchronous square-wave signal duration T lasting within a high-frequency synchronous square-wave signal period as the high level signal of the host high-frequency synchronous square-wave signal.
In a further implementation, an adjusting threshold value can be set to avoid the carrier wave to slave devices not
It is disconnected to adjust, i.e., when the phase difference is smaller, the carrier wave of the slave devices is not adjusted, i.e., phase adjusted information is determined by the phase difference and preset threshold.If the phase difference is greater than preset threshold and is less than T/2, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；If the phase difference is more than or equal to T/2 and is less than the difference of T and the preset threshold, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag.
Step S206: the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices by the CPLD operation chip of the slave devices.
Optionally, the MCU main control chip that the direction signal for carrying the phase adjusted information is transferred to the slave devices by adjusting direction instruction line by the CPLD operation chip of the slave devices.
In specific implementation, the CPLD operation chip of the slave devices transmits the MCU main control chip that the phase adjusted information is transferred to the slave devices by high level signal or low level signal on the adjusting direction instruction line, as shown in Figure 3, there are two adjusting direction instruction lines in Fig. 3 between the MCU main control chip of slave devices and the CPLD operation chip of the slave devices, then when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation, 01 is sent to the MCU main control chip of the slave devices, when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag, 10 are sent to the MCU main control chip of the slave devices, when the CPLD operation chip of slave devices is true When the carrier wave of the fixed slave devices does not have to adjust, the MCU main control chip of Xiang Suoshu slave devices sends 00 or 11.
Step S207: the MCU main control chip of the slave devices is adjusted the carrier wave of the slave devices according to the direction adjustment signal.
Specifically, being adjusted after the MCU main control chip of the slave devices gets the direction instruction signal from the adjusting direction instruction line according to carrier wave of the direction instruction signal to the slave devices.
The CPLD operation chip of slave devices passes through acquisition host high-frequency synchronous square-wave signal and records each moment for detecting the rising edge of the host high-frequency synchronous square-wave signal in the embodiment of the present invention, it obtains the slave high-frequency synchronous square-wave signal of the MCU main control chip transmission of the slave devices and records the first moment for detecting the rising edge of the slave high-frequency synchronous square-wave signal, the rising of the determining host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal from each moment
Second moment on edge, the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal is determined according to the time difference at the second moment and first moment, so that it is determined that the phase adjusted information of the carrier wave of machine equipment, the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices, the MCU main control chip is adjusted the carrier wave of the slave devices according to the direction adjustment signal to realize that slave carrier wave is synchronous with host carrier wave, phase adjusted information is determined by CPLD operation chip, the square-wave signal of MCU main control chip capture host is not needed, master-slave synchronisation may be implemented in the case where MCU main control chip does not have capture mouth.
Refer to Fig. 5 again, Fig. 5 is the flow diagram of the synchronous implementation method of another high frequency carrier in the embodiment of the present invention, as shown in the figure the described method includes:
Step S301: the CPLD operation chip of slave devices obtains the host high-frequency synchronous square-wave signal of host equipment transmission from bus.
Optionally, the bus can be the buses such as 485 buses, iic bus.
Wherein, the host high-frequency synchronous square-wave signal is issued by the MCU main control chip of the host equipment.
Wherein, the high frequency carrier of the host high-frequency synchronous square-wave signal and the host equipment has corresponding relationship, at the time of detecting the zero crossing of the high frequency carrier of the as described host equipment at the time of rising edge or failing edge of the host high-frequency synchronous square-wave signal.
Step S302: the CPLD operation chip of the slave devices obtains the slave high-frequency synchronous square-wave signal that the MCU main control chip of the slave devices is sent.
Wherein, the high frequency carrier of the slave high-frequency synchronous square-wave signal and the slave devices has corresponding relationship, at the time of the zero crossing for the high frequency carrier for representing the slave devices at the time of detecting the rising edge or failing edge of the slave high-frequency synchronous square-wave signal.
Step S303: the CPLD operation chip of the slave devices determines the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal.
Optionally, the first moment of the available rising edge for detecting the slave high-frequency synchronous square-wave signal of the CPLD operation chip of the slave devices and detect the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal rising edge the second moment；According to described
The time difference at two moment and first moment determines the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal.
In the specific implementation, the CPLD operation chip of the slave devices can set following counting mode for the counter of the CPLD operation chip of the slave devices: when detecting the rising edge of the host high-frequency synchronous square-wave signal, the counter of the CPLD operation chip counts from zero and resets when detecting next rising edge of the host high-frequency synchronous square-wave signal and start counting again.The CPLD operation chip of the slave devices can detect the first moment of the rising edge of the slave high-frequency synchronous square-wave signal and the second moment of the rising edge that detects the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal obtain by way of reading the numerical value of the counter, and the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal is determined according to the second value of the first numerical value of first moment corresponding counter counter corresponding with second moment.Wherein, it can determine that the second value is the last one numerical value before 0 or the counter O reset according to the counting rule of the counter, if first moment occurred before second moment, then using the last one numerical value before the counter O reset as second value, if first moment occurred after second moment, second value is used as by 0.
For example, as shown in Fig. 2, Fig. 2 is the schematic diagram for determining the phase difference of host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal in the embodiment of the present invention.The rising edge hour counter of the CPLD operation chip detection host high-frequency synchronous square-wave signal of slave devices is started counting and is reset in next rising edge hour counter of the host high-frequency synchronous square-wave signal in Fig. 2, full-scale reading Tm before obtaining counter O reset, the CPLD operation chip of slave devices obtain the reading t1 of counter when detecting the rising edge of host high-frequency synchronous square-wave signal.There are two types of phase difference situations, and when occurring before second moment at first moment, second value t2=Tm, phase difference Tm-t1 occur when after second moment, second value t2=0 when first moment, and the phase difference is t1.
Step S304: if the phase difference is greater than preset threshold and is less than T/2, then the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation, wherein, the duration T lasting within a high-frequency synchronous square-wave signal period for the high level signal of the host high-frequency synchronous square-wave signal.
In the specific implementation, the CPLD operation chip of the slave devices can determine the T by reading the numerical value of the counter, when can will test the failing edge of the host high-frequency synchronous square-wave signal
The third value of the counter duration T lasting within a high-frequency synchronous square-wave signal period as the high level signal of the host high-frequency synchronous square-wave signal.
Wherein, preset threshold is the small adjusting threshold value of an adjusting threshold value comparison.
Step S305: if the phase difference is more than or equal to T/2 and is less than the difference of T and the preset threshold, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag.
Step S306: the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices by the CPLD operation chip of the slave devices.
Optionally, the MCU main control chip that the direction signal for carrying the phase adjusted information is transferred to the slave devices by adjusting direction instruction line by the CPLD operation chip of the slave devices.
In specific implementation, the CPLD operation chip of the slave devices transmits the MCU main control chip that the phase adjusted information is transferred to the slave devices by high level signal or low level signal on the adjusting direction instruction line, as shown in Figure 3, there are two adjusting direction instruction lines in Fig. 3 between the MCU main control chip of slave devices and the CPLD operation chip of the slave devices, then when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation, 01 is sent to the MCU main control chip of the slave devices, when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag, 10 are sent to the MCU main control chip of the slave devices, when the CPLD operation chip of slave devices is true When the carrier wave of the fixed slave devices does not have to adjust, the MCU main control chip of Xiang Suoshu slave devices sends 00 or 11.
Step S307: the MCU main control chip of the slave devices is adjusted the carrier wave of the slave devices according to the direction adjustment signal.
Specifically, being adjusted after the MCU main control chip of the slave devices gets the direction instruction signal from the adjusting direction instruction line according to carrier wave of the direction instruction signal to the slave devices.
The CPLD operation chip of slave devices is by obtaining host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal in the embodiment of the present invention, the phase difference of the carrier wave of slave devices is determined according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal, phase difference is compared with the carrier cycle T and preset threshold of host, if the phase difference is greater than preset threshold and is less than T/2, the phase adjusted information for then determining the carrier wave of the slave devices is load regulation, if the phase difference is more than or equal to
T/2 and the difference for being less than T and the preset threshold, then determine that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag, the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices, the MCU main control chip is adjusted the carrier wave of the slave devices according to the direction adjustment signal to realize that slave carrier wave is synchronous with host carrier wave, phase adjusted information is determined by CPLD operation chip, the square-wave signal of MCU main control chip capture host is not needed, master-slave synchronisation may be implemented in the case where MCU main control chip does not have capture mouth, the setting of preset threshold can constantly regulate to avoid the carrier wave of slave devices.
It is the composed structure schematic diagram of one of embodiment of the present invention slave devices referring to Fig. 6, Fig. 6, the slave devices as shown in the figure include at least:
CPLD operation chip 410, the host high-frequency synchronous square-wave signal sent for obtaining host equipment from bus.
Optionally, the bus can be the buses such as 485 buses, iic bus.
Wherein, the host high-frequency synchronous square-wave signal is issued by the MCU main control chip of the host equipment.
Wherein, the host high-frequency synchronous square-wave signal has corresponding relationship by the carrier wave of the host equipment, at the time of detecting the zero crossing of the carrier wave of the as described host equipment at the time of rising edge or failing edge of the host high-frequency synchronous square-wave signal.
The CPLD operation chip 410 is also used to obtain the slave high-frequency synchronous square-wave signal that the MCU main control chip 420 of the slave devices is sent.
Wherein, the slave high-frequency synchronous square-wave signal has corresponding relationship by the carrier wave of the slave devices, at the time of detecting the zero crossing of the carrier wave of the as described slave devices at the time of rising edge or failing edge of the slave high-frequency synchronous square-wave signal.
The CPLD operation chip 410 is also used to determine the phase adjusted information of the carrier wave of the slave devices according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal.
Optionally, as shown in fig. 7, the CPLD operation chip 410 may include:
Phase difference determining module 411, for determining the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal.
Optionally, as shown in figure 8, the phase difference determining module 411 may include:
First moment acquiring unit 4111, for obtaining the first moment for detecting the rising edge of the slave high-frequency synchronous square-wave signal.
Optionally, the first moment acquiring unit 4111 can detect the first moment of the rising edge of the slave high-frequency synchronous square-wave signal obtaining by way of reading the numerical value of the counter.
Second moment acquiring unit 4112, for obtaining the second moment for detecting the rising edge of the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal.
Optionally, the second moment acquiring unit 4112 can read the counter numerical value can by the numerical value of reading by way of obtain and detect the second moment of the rising edge of the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal.
In the specific implementation, the CPLD operation chip 410 of the slave devices can set following counting mode for the counter of the CPLD operation chip 410 of the slave devices: when detecting the rising edge of the host high-frequency synchronous square-wave signal, the counter of the CPLD operation chip 410 counts from zero and resets when detecting next rising edge of the host high-frequency synchronous square-wave signal and start counting again.
Phase difference determination unit 4113, for determining the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the time difference at second moment and first moment.
Phase difference determination unit 4113 determines the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the second value of the first numerical value counter corresponding with second moment of first moment corresponding counter.Wherein, it can determine that the second value is the last one numerical value before 0 or the counter O reset according to the counting rule of the counter, if first moment occurred before second moment, then using the last one numerical value before the counter O reset as second value, if first moment occurred after second moment, second value is used as by 0.
For example, as shown in Fig. 2, Fig. 2 is the schematic diagram for determining the phase difference of host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal in the embodiment of the present invention.The rising edge hour counter of the CPLD operation chip detection host high-frequency synchronous square-wave signal of slave devices is started counting and is reset in next rising edge hour counter of the host high-frequency synchronous square-wave signal in Fig. 2, full-scale reading Tm before obtaining counter O reset, the CPLD operation chip of slave devices obtain the reading t1 of counter when detecting the rising edge of host high-frequency synchronous square-wave signal.There are two types of phase difference situations, occurs when first moment in institute
When stating before the second moment, second value t2=Tm, phase difference Tm-t1 occur when after second moment, second value t2=0 when first moment, and the phase difference is t1.
Phase adjusted information determination module 412, the phase adjusted information of the carrier wave for determining the slave devices according to the phase difference.
Optionally, as shown in figure 9, the phase adjusted information determination module 412 may include:
Load regulation determination unit 4121, if being less than T/2 for the phase difference, the phase adjusted information for then determining the carrier wave of the slave devices is load regulation, wherein the duration lasting within a high-frequency synchronous square-wave signal period of the high level signal of host high-frequency synchronous square-wave signal described in the T.
In specific implementation, the CPLD operation chip 410 of the slave devices can determine the T by reading the numerical value of the counter, can will test the high level signal of host high-frequency synchronous square-wave signal described in carrier cycle of the third value of the counter when failing edge of the host high-frequency synchronous square-wave signal as host equipment duration T lasting within a high-frequency synchronous square-wave signal period.
Lag adjusts determination unit 4122, for determining that the phase adjusted information of carrier wave of the slave devices is adjusted for lag.
Optionally, adjusting threshold value constantly regulate to avoid the carrier wave to slave devices can be set, i.e. when the phase difference is smaller, the carrier wave of the slave devices is not adjusted, the i.e. described load regulation determination unit 4121 is specifically used for: if the phase difference is greater than preset threshold and is less than T/2, it is determined that the phase adjusted information of the carrier wave of the slave devices is load regulation；The lag adjusts determination unit 4122 and is specifically used for: if the phase difference is more than or equal to T/2 and is less than the difference of T and the preset threshold, it is determined that the phase adjusted information of the carrier wave of the slave devices is that lag is adjusted.
The CPLD operation chip 410 is also used to the direction adjustment signal for carrying the phase adjusted information being transferred to MCU main control chip.
Optionally, the MCU main control chip 420 that the direction signal for carrying the phase adjusted information is transferred to the slave devices by adjusting direction instruction line by the CPLD operation chip 410.
In specific implementation, the CPLD operation chip 410 of the slave devices transmits the MCU main control chip that the phase adjusted information is transferred to the slave devices by high level signal or low level signal on the adjusting direction instruction line, as shown in Figure 3, there are two adjusting direction instruction lines in Fig. 3 between the MCU main control chip of slave devices and the CPLD operation chip of the slave devices, then when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation, to
The MCU main control chip of the slave devices sends 01, when the CPLD operation chip of slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag, 10 are sent to the MCU main control chip of the slave devices, when the CPLD operation chip of slave devices determines the carrier wave of the slave devices without adjusting, the MCU main control chip of Xiang Suoshu slave devices sends 00 or 11.
MCU main control chip 420, for the carrier wave of the slave devices to be adjusted according to the direction adjustment signal.
Specifically, being adjusted after the MCU main control chip 420 of the slave devices gets the direction instruction signal from the adjusting direction instruction line according to carrier wave of the direction instruction signal to the slave devices.
The CPLD operation chip of slave devices is by obtaining host high-frequency synchronous square-wave signal and slave high-frequency synchronous square-wave signal in the embodiment of the present invention, the phase adjusted information of the carrier wave of slave devices is determined according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal, and the direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices, the MCU main control chip is adjusted the carrier wave of the slave devices according to the direction adjustment signal to realize that slave carrier wave is synchronous with host carrier wave, phase adjusted information is determined by CPLD operation chip, square-wave signal without MCU main control chip capture host, master-slave synchronisation may be implemented in the case where MCU main control chip does not have capture mouth.
Figure 10 is the composed structure schematic diagram of the synchronous realization system of one of embodiment of the present invention high frequency carrier, and the system comprises slave devices 510, bus 520 and host equipments 530 as shown in the figure, in which:
In one embodiment, the slave devices 510 are the slave devices of 6 description of the attached drawing of embodiment combination above of the invention；
The host equipment 530 is used to send the bus 520 for host high-frequency synchronous square-wave signal；
The host high-frequency synchronous square-wave signal that the slave devices 510 are sent for obtaining host equipment from bus；Obtain the slave high-frequency synchronous square-wave signal of the slave devices；The phase adjusted information of the carrier wave of the slave devices is determined according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The carrier wave of the slave devices is adjusted according to the phase adjusted information.
Those of ordinary skill in the art will appreciate that realizing all or part of stream in above-described embodiment method
Journey is relevant hardware can be instructed to complete by computer program, and the program can be stored in a computer-readable storage medium, and the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic disk, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access Memory, RAM) etc..
The steps in the embodiment of the present invention can be sequentially adjusted, merged and deleted according to actual needs.
Unit in the device of that embodiment of the invention can be combined, divided and deleted according to actual needs.
The above disclosure is only the preferred embodiments of the present invention, and of course, the scope of rights of the present invention cannot be limited by this, therefore equivalent changes made in accordance with the claims of the present invention, is still within the scope of the present invention.
Claims (10)
- A kind of implementation method that high frequency carrier is synchronous, which is characterized in that the described method includes:The CPLD operation chip of slave devices obtains the host high-frequency synchronous square-wave signal of host equipment transmission from bus；The CPLD operation chip of the slave devices obtains the slave high-frequency synchronous square-wave signal that the MCU main control chip of the slave devices is sent；The CPLD operation chip of the slave devices determines the phase adjusted information of the carrier wave of the slave devices according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The direction adjustment signal for carrying the phase adjusted information is transferred to the MCU main control chip of the slave devices by the CPLD operation chip of the slave devices；The MCU main control chip of the slave devices is adjusted the carrier wave of the slave devices according to the direction adjustment signal.
- The synchronous implementation method of high frequency carrier as described in claim 1, it is characterized in that, the CPLD operation chip of the slave devices determines that the phase adjusted information of carrier wave of the slave devices includes: according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signalThe CPLD operation chip of the slave devices determines the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The CPLD operation chip of the slave devices determines the phase adjusted information of the carrier wave of the slave devices according to the phase difference.
- The synchronous implementation method of high frequency carrier as claimed in claim 2, it is characterized in that, the CPLD operation chip of the slave devices determines that the phase difference of the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal includes: according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signalThe CPLD operation chip of the slave devices obtains the first moment for detecting the rising edge of the slave high-frequency synchronous square-wave signal；The CPLD operation chip of the slave devices obtains the second moment for detecting the rising edge of the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal；The phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal is determined according to the time difference at second moment and first moment.
- The synchronous implementation method of high frequency carrier as claimed in claim 2, which is characterized in that the CPLD operation chip of the slave devices determines that the phase adjusted information of carrier wave of the slave devices includes: according to the phase differenceIf the phase difference is less than T/2, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；Otherwise, then the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag；Wherein, the duration T lasting within a high-frequency synchronous square-wave signal period for the high level signal of the host high-frequency synchronous square-wave signal.
- The synchronous implementation method of high frequency carrier as claimed in claim 4, which is characterized in that if the phase difference is less than T/2, the CPLD operation chip of the slave devices confirms that the phase adjusted information of the carrier wave of the slave devices includes: for load regulationIf the phase difference is greater than preset threshold and is less than T/2, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is load regulation；It is described otherwise, then the CPLD operation chip of the slave devices determines that the phase adjusted information of the slave high-frequency square-wave signal is adjusted for lag and includes:If the phase difference is more than or equal to T/2 and is less than the difference of T and the preset threshold, the CPLD operation chip of the slave devices determines that the phase adjusted information of the carrier wave of the slave devices is adjusted for lag.
- A kind of slave devices, which is characterized in that the slave devices include:CPLD operation chip, the host high-frequency synchronous square-wave signal sent for obtaining host equipment from bus；The CPLD operation chip is also used to obtain the slave high-frequency synchronous square-wave signal that the MCU main control chip of the slave devices is sent；The CPLD operation chip is also used to determine the phase adjusted information of the carrier wave of the slave devices according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The CPLD operation chip is also used to the direction adjustment signal for carrying the phase adjusted information being transferred to MCU main control chip；MCU main control chip, for the carrier wave of the slave devices to be adjusted according to the direction adjustment signal.
- Slave devices as claimed in claim 6, which is characterized in that the CPLD operation chip includes:Phase difference determining module, for determining the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；Phase adjusted information determination module, the phase adjusted information of the carrier wave for determining the slave devices according to the phase difference.
- Slave devices as claimed in claim 7, which is characterized in that the phase difference determining module includes:First moment acquiring unit, for obtaining the first moment for detecting the rising edge of the slave high-frequency synchronous square-wave signal；Second moment acquiring unit, for obtaining the second moment for detecting the rising edge of the host high-frequency synchronous square-wave signal nearest with the rising edge of the slave high-frequency synchronous square-wave signal；Phase difference determination unit, for determining the phase difference of the host high-frequency synchronous square-wave signal Yu the slave high-frequency synchronous square-wave signal according to the time difference at second moment and first moment.
- Slave devices as claimed in claim 7, which is characterized in that the phase adjusted information determination module includes:Load regulation determination unit, if being less than T/2 for the phase difference, it is determined that the slave devices Carrier wave phase adjusted information be load regulation；Lag adjusts determination unit, for determining that the phase adjusted information of carrier wave of the slave devices is adjusted for lag；Wherein, the duration T lasting within a high-frequency synchronous square-wave signal period for the high level signal of the host high-frequency synchronous square-wave signal.
- A kind of realization system that high frequency carrier is synchronous, which is characterized in that including slave devices, bus and the host equipment as described in any one of claim 6-9, in which:The host equipment is used to send the bus for host high-frequency synchronous square-wave signal；The host high-frequency synchronous square-wave signal that the slave devices are sent for obtaining host equipment from bus；Obtain the slave high-frequency synchronous square-wave signal of the slave devices；The phase adjusted information of the carrier wave of the slave devices is determined according to the host high-frequency synchronous square-wave signal and the slave high-frequency synchronous square-wave signal；The carrier wave of the slave devices is adjusted according to the phase adjusted information.
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