CN110233610A

CN110233610A - A kind of copped wave sequence circuit

Info

Publication number: CN110233610A
Application number: CN201910383757.6A
Authority: CN
Inventors: 曹骁飞
Original assignee: Scarlett Ruipu Microelectronics Technology (suzhou) Ltd By Share Ltd
Current assignee: Scarlett Ruipu Microelectronics Technology (suzhou) Ltd By Share Ltd
Priority date: 2019-05-08
Filing date: 2019-05-08
Publication date: 2019-09-13
Anticipated expiration: 2039-05-08
Also published as: CN110233610B

Abstract

Present invention discloses a kind of copped wave sequence circuits, by the switch S1 of discrete time, S2, S1d, S2d, CHOP_S1, CHOP_S2, capacitor C1, C2 and OTA circuit connects composition, it is characterized in that being equipped with pairs of PMOS tube in OTA circuit, the switch S1P of NMOS tube and common-mode feedback clock, S2P, capacitor C3, C4, wherein the time series main body of switch S1P and switch S1, the time series of S1d is consistent, the time series main body and switch S2 of switch S2P, the time series of S2d is consistent, and switch S1P, S2P is in switch CHOP_S1, CHOP_S2's jumps moment hold mode, in switch CHOP_S1, next timing cycles after the completion of the jumping of CHOP_S2 are corresponding Follow switch S1, S2.Using copped wave Sequential Circuit Design of the invention, Charge Injection Error caused by switched-capacitor CMFB is eliminated, reduces requirement and overall power to OTA circuit bandwidth, while reducing settling time of the OTA circuit in copped wave.

Description

A kind of copped wave sequence circuit

Technical field

The present invention relates to the switching capacity chopper circuits more particularly to one kind of a kind of discrete time to be able to suppress switching capacity Common-mode feedback causes the copped wave sequence circuit of Charge Injection Error.

Background technique

In High Definition Systems design, need to use a kind of switching capacity chopper circuit of discrete time.Traditional is such Circuit and its input timing are as shown in Figure 1, Figure 2 and Figure 3, and conventional func is realized and the mode of connection is existing mature design, therefore It omits and is described in detail.But as seen from the figure, wherein design access has OTA circuit to improve the difference component of processing input signal.And OTA electricity The main control terminal of three of road includes control signal VCOM and switch S1, S2 that input clock sequence shares, that is, passes through switch electricity The clock sequence for holding common-mode feedback is consistent with external timing timing.

But as application practice is found, during copped wave occurs before switch S1 shutdown, switch S2 conducting, due to The common-mode feedback of switching capacity establishes speed and slightly has sluggishness, leads to have the problem of charge injection can be by second mining sample in copped wave, causes Charge Injection Error is introduced in each copped wave.

Although the bandwidth for improving common mode feedback loop can solve this problem, under normal conditions, copped wave switching is all The non-overlapping time in PH1 and PH2 occurs, it is therefore desirable to which the common mode feedback loop bandwidth much larger than difference mode signal bandwidth could allow OTA is completely set up, to cause the waste of power consumption.

Summary of the invention

In view of the problems of the above-mentioned prior art, the purpose of the present invention is directed to a kind of copped wave sequence circuit, improves Chopping process.

In order to achieve the above object, the technology used in the present invention solution is a kind of copped wave sequence circuit, by discrete Switch S1, S2, S1d, S2d, CHOP_S1, CHOP_S2 of time, capacitor C1, C2 and OTA circuit connect composition, and feature exists In: the OTA circuit interior switch S1P, S2P for being equipped with pairs of PMOS tube, NMOS tube and common-mode feedback clock, capacitor C3, C4, Wherein the time series main body of switch S1P is consistent with the time series of switch S1, S1d, the time series main body of switch S2P with open The time series for closing S2, S2d is consistent, and switch S1P, S2P jump moment hold mode in switch CHOP_S1, CHOP_S2, Switch S1, S2 are followed in next timing cycles correspondence after the completion of jumping of switch CHOP_S1, CHOP_S2.

Using copped wave Sequential Circuit Design of the invention, have substantive distinguishing features outstanding and significant progress: the electricity Road eliminates Charge Injection Error caused by switched-capacitor CMFB, reduces the requirement to OTA circuit bandwidth and whole function Consumption, while reducing settling time of the OTA circuit in copped wave.

Detailed description of the invention

Fig. 1 is the wiring schematic diagram of conventional chopper sequence circuit.

Fig. 2 is the wiring schematic diagram of OTA circuit in conventional chopper sequence circuit.

Fig. 3 is the input timing of the such circuit of tradition.

Fig. 4 is the wiring schematic diagram of copped wave sequence circuit of the present invention.

Fig. 5 is the wiring schematic diagram of OTA circuit in copped wave sequence circuit of the present invention.

Fig. 6 is the input timing of circuit shown in corresponding diagram 3 of the present invention and Fig. 4.

Specific embodiment

Just attached drawing in conjunction with the embodiments below, the embodiment of the present invention is described in further detail, so that of the invention Technical solution is more readily understood, grasps, to make relatively sharp define to protection scope of the present invention.

Designer of the present invention is for conventional chopper sequence circuit since to establish speed relatively slow for the common-mode feedback of switching capacity Stagnant, the deficiency for being easily introduced error etc. has carried out comprehensive analysis, and in conjunction with experience and creative work, innovation proposes a kind of new The copped wave sequence circuit of type improves input clock sequence to the control logic of switching capacity on the basis of traditional such circuit, To meet the speed for adapting to common-mode feedback and establishing.

For convenient for understanding with being more embodied, as shown in Figures 4 to 6, this kind of copped wave sequence circuit, by the switch of discrete time S1, S2, S1d, S2d, CHOP_S1, CHOP_S2, capacitor C1, C2 and OTA circuit connect composition.In contrast, outside the OTA circuit The mode of connection of switch S1, S2, S1d, S2d, CHOP_S1, CHOP_S2 involved in portion and capacitor C1, C2 are that existing routine must Want technology, i.e. pulse sequence switch S1, S2, S1d, S2d fixed according to the respective period, and change switching charge the circuit not With the flow direction in branch, and switch CHOP_S1, CHOP_S2 are inputted according to timing and are realized that the signal of copped wave exports.In this regard, this hair The bright technique improvement for not doing wiring etc..

And switch S1P, S2P of pairs of PMOS tube, NMOS tube and common-mode feedback clock are equipped in the OTA circuit, capacitor C3,C4.OTA circuit corresponds to the switching capacity wiring construction mirror settings of the common-mode feedback clock of Vout+ and the two sides Vout-, A termination output Vout+ or Vout- of middle capacitor C4, and pass through the tandem link of switch S1P, S2P and control signal VCOM phase Connect, the common gate of another termination a pair of NMOS tube of capacitor C4 exports Vctrl, and by the tandem link of switch S1P, S2P and Control signal VB4 connects, and is connected to electricity between the make and break contact of tandem link and the make and break contact of another tandem link Hold C3.As shown in fig. 6, wherein the time series main body of switch S1P is consistent with the time series of switch S1, S1d, switch S2P's Time series main body is consistent with the time series of switch S2, S2d, and switch S1P, S2P are in the jump of switch CHOP_S1, CHOP_S2 Turn moment hold mode, follows switch in next timing cycles correspondence after the completion of jumping of switch CHOP_S1, CHOP_S2 S1、S2。

Completely new copped wave sequence circuit after the technique improvement, in the chopping process of switch CHOP_S1, CHOP_S2 jumped In, by the clock of the common-mode feedback of switching capacity in OTA circuit, i.e. the switch state of switch S1P, S2P is clamped down on without sending Overturning, therefore copped wave will not introduce the Charge Injection Error as caused by the clock feedthrough of switched-capacitor CMFB every time.And OTA The difference component that the clock feedthrough that circuit does not need processing common-mode feedback introduces reduces to reduce the requirement to OTA bandwidth The power consumption of entire OTA.

In the moment for jumping switching of switch CHOP_S1, CHOP_S2, switch S1P is in closed state, therefore C3 and C4 It is the load capacitance that OTA circuit is seen.By the value of this load capacitance of Rational choice C3, it can optimize and improve OTA electricity Bandwidth and phase margin of the road in this transient state.

It to sum up combines the embodiment of diagram to be described in detail, using copped wave Sequential Circuit Design of the invention, eliminates switching capacity Charge Injection Error caused by common-mode feedback reduces requirement and overall power to OTA circuit bandwidth, while reducing OTA Settling time of the circuit in copped wave.

The preferred embodiment of the present invention has been described above in detail, and still, the invention is not limited to above-mentioned particular implementations Mode, those skilled in the art can modify within the scope of the claims or equivalents, should be included in this hair Within bright protection scope.

Claims

1. a kind of copped wave sequence circuit, by switch S1, S2, S1d, S2d, CHOP_S1, CHOP_S2 of discrete time, capacitor C1, C2 and OTA circuit connects composition, it is characterised in that: pairs of PMOS tube, NMOS tube and common-mode feedback are equipped in the OTA circuit Switch S1P, S2P of clock, capacitor C3, C4, wherein the time series one of the time series main body of switch S1P and switch S1, S1d It causes, the time series main body of switch S2P is consistent with the time series of switch S2, S2d, and switch S1P, S2P are in switch CHOP_ S1, CHOP_S2's jumps moment hold mode, in next timing week after the completion of jumping of switch CHOP_S1, CHOP_S2 Phase correspondence follows switch S1, S2.

2. copped wave sequence circuit according to claim 1, it is characterised in that: the OTA circuit corresponds to Vout+ and Vout- two The switching capacity wiring construction mirror settings of the common-mode feedback clock of side, wherein capacitor C4 one termination output Vout+ or Vout-, and connected by the tandem link of switch S1P, S2P with control signal VCOM, another termination a pair of NMOS of capacitor C4 The common gate of pipe exports Vctrl, and is connected by the tandem link of switch S1P, S2P with control signal VB4, a tandem link Make and break contact and another tandem link make and break contact between be connected to capacitor C3.