CN110233098A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN110233098A CN110233098A CN201810178872.5A CN201810178872A CN110233098A CN 110233098 A CN110233098 A CN 110233098A CN 201810178872 A CN201810178872 A CN 201810178872A CN 110233098 A CN110233098 A CN 110233098A
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- 238000000034 method Methods 0.000 title claims abstract description 82
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 230000004888 barrier function Effects 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000137 annealing Methods 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 238000005224 laser annealing Methods 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 claims description 3
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 3
- RGZQGGVFIISIHZ-UHFFFAOYSA-N strontium titanium Chemical compound [Ti].[Sr] RGZQGGVFIISIHZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000004513 sizing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 411
- 230000008569 process Effects 0.000 description 29
- -1 oxonium ion Chemical class 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000007772 electrode material Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor devices and forming method thereof, method includes: offer substrate；Dielectric layer is formed on the substrate, there is the first opening through dielectric layer in dielectric layer, the first opening exposes part of substrate surface.Boundary layer is formed in the first open bottom；After forming boundary layer, gate dielectric layer is formed in the first opening sidewalls and interface layer surfaces；The adjusting work-function layer for being located at gate dielectric layer surface is formed in first opening；It is formed in first opening and is located at the barrier layer for adjusting work-function layer surface；The sacrificial layer for being located at barrier layer surface is formed on the dielectric layer and in the first opening；It is formed after sacrificial layer, gate dielectric layer is made annealing treatment；After annealing, sacrificial layer is removed；After removing sacrificial layer, gate electrode layer, full first opening of gate electrode layer filling are formed in barrier layer surface.The method improves the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density and more high integration
Direction develop, the grid size of planar transistor is smaller and smaller, so that grid dies down to the control ability of channel current, is easy
Short-channel effect is generated, causes current leakage, and then influence the electric property of semiconductor devices.
It is introduced on the basis of fin formula field effect transistor to further reduce device size, improve device density
High-K metal gate transistor, i.e., using high K dielectric material as gate dielectric layer, using metal material as grid.The high-K metal gate
Transistor is formed using rear grid (gate last) technique, and grid technique is in removal dummy grid oxide layer and pseudo- grid after one of which
After the layer of pole, so as to form gate trench, the gate dielectric layer of high K dielectric material is formed then at the inner wall surface of gate trench.
However, the electricity for the semiconductor devices that the MOS transistor or fin formula field effect transistor of either plane formula are constituted
It learns performance and yield is still to be improved.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor devices and forming method thereof, to improve semiconductor devices
Performance.
In order to solve the above technical problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide substrate；
Dielectric layer is formed on the substrate, there is the first opening through dielectric layer in dielectric layer, the first opening exposes part of substrate table
Face.Boundary layer is formed in the first open bottom；After forming boundary layer, gate medium is formed in the first opening sidewalls and interface layer surfaces
Layer；The adjusting work-function layer for being located at gate dielectric layer surface is formed in first opening；Position is formed in first opening
In the barrier layer for adjusting work-function layer surface；The sacrifice for being located at barrier layer surface is formed on the dielectric layer and in the first opening
Layer；It is formed after sacrificial layer, gate dielectric layer is made annealing treatment；After annealing, sacrificial layer is removed；After removing sacrificial layer,
Gate electrode layer, full first opening of gate electrode layer filling are formed in barrier layer surface.
Optionally, the material of the sacrificial layer includes unformed silicon, amorphous silicon.
Optionally, the material on the barrier layer includes TaN, Ta and combinations thereof.
Optionally, barrier layer with a thickness of 10 angstroms~20 angstroms.
Optionally, the material for adjusting work-function layer is TiN or TaN.
Optionally, annealing includes laser annealing or spike annealing.
Optionally, it is 800 degrees Celsius~1100 that the parameter of the annealing, which includes: the temperature range of the annealing,
Degree Celsius, the time of the annealing is 5 seconds~100 seconds, and the gas of the annealing utilized is nitrogen, the nitrogen
Range of flow be 10sccm~1000sccm.
Optionally, the material of the gate dielectric layer include hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthana, zirconium silicon oxide,
Titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.
Optionally, the material of the boundary layer is silica or silicon oxynitride.
Optionally, the substrate includes: semiconductor substrate, positioned at several fins of semiconductor substrate surface；Positioned at partly leading
The separation layer on body substrate surface, the side wall of the separation layer covering part fin, and the insulation surface are lower than the fin
Top surface.
Optionally, first opening is across the fin, and first opening exposes part fin side wall and top
Portion surface.
Optionally, the boundary layer is formed in partial sidewall and the atop part surface for the fin that the first opening exposes.
Optionally, the material of the fin includes monocrystalline silicon, germanium or SiGe.
Optionally, the forming method of first opening includes: to form the first pseudo- grid structure in substrate surface, and described first
Pseudo- grid structure includes the first pseudo- gate dielectric layer and the first dummy gate layer positioned at the first pseudo- gate dielectric layer surface；In the substrate table
Face forms dielectric layer, and the surface of the dielectric layer is flushed with the top surface of the described first pseudo- grid structure；It is pseudo- to remove described first
Grid structure forms the first opening in dielectric layer.
Optionally, further includes: before forming dielectric layer, form first in the substrate of the described first pseudo- grid structure two sides
Source and drain doping area.
Optionally, further includes: after removing the sacrificial layer, formed before gate electrode layer, formed in the barrier layer surface
Main work-function layer.
Optionally, also there is the second opening, third opening and the 4th opening, second opening, the in the dielectric layer
Three openings and the 4th opening run through the dielectric layer；The boundary layer is also located at second opening, third opening and the 4th is opened
On mouth bottom；The gate dielectric layer is also located at the second opening, third opening and the 4th opening sidewalls；The adjusting work-function layer is also
In the second opening, third opening and the 4th opening；The barrier layer is also located at the second opening, third opening and the 4th opening
It is interior；In the opening of sacrificial layer second, third opening and the 4th opening；The gate electrode layer is also located at the second opening, third is opened
In mouth and the 4th opening；The main work-function layer includes the first main work-function layer being located in the first opening, is located at the second opening
In the second main work-function layer, positioned at third opening in the main work-function layer of third, positioned at the 4th opening in the 4th main work content
Several layers；
The method for forming the first main work-function layer includes: to form the first main work content in the side wall of first opening and bottom
Several layers；The method for forming the second main work-function layer includes: to form the second main work function in the side wall of second opening and bottom
Layer；The method for forming the main work-function layer of third includes: to form the main work-function layer of third in the side wall of third opening and bottom；
The method for forming the 4th main work-function layer includes: to form the 4th main work-function layer in the side wall of the 4th opening and bottom.
Optionally, the described first main work-function layer, the second main work-function layer, the main work-function layer of third and the 4th main work function
The forming method of layer includes: to form the in the side wall of first opening, the second opening, third opening and the 4th opening and bottom
One initial workfunction layer；After the first initial workfunction layer in the first opening of removal, the second opening and third opening, described the
The second initial workfunction layer of side wall and bottom formation of one opening, the second opening, third opening and the 4th opening；Removal first is opened
After the second initial workfunction layer in mouth, the second opening, it is open in first opening, the second opening, third opening and the 4th
Side wall and bottom formed third initial workfunction layer；Third initial workfunction layer in the first opening of removal, described first
The 4th initial workfunction layer of side wall and bottom formation of opening, the second opening, third opening and the 4th opening；
Wherein, the described first main work-function layer includes the 4th initial workfunction layer in the first opening；Second main work function
Layer includes the 4th initial workfunction layer and third initial workfunction layer in the second opening；The main work-function layer of third includes that third is opened
The 4th initial workfunction layer, third initial workfunction layer and the second initial workfunction layer in mouthful；4th main work-function layer includes
The 4th initial workfunction layer, third initial workfunction layer, the second initial workfunction layer and the first initial work content in 4th opening
Several layers.
The present invention also provides a kind of semiconductor devices formed using above-mentioned any one method.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method of semiconductor devices provided by the invention, barrier layer is formed adjusting work-function layer surface, is formed
Sacrificial layer is formed in barrier layer surface again behind barrier layer；It is isolated with barrier layer and adjusts work-function layer and sacrificial layer, forms sacrificial layer
Gate dielectric layer is carried out in annealing process afterwards, sacrificial layer with barrier reaction, does not remain when removing sacrificial layer, will not
Influence the performance of semiconductor devices.Meanwhile by the blocking on barrier layer, in annealing process, oxonium ion is more difficult to get access to arrive sacrificial layer
In, the oxonium ion loss in gate dielectric layer is less, forms less oxygen ion hole, the leakage current of semiconductor devices is relatively
It is small.To improve the performance of device.
Detailed description of the invention
Fig. 1 to Fig. 2 is a kind of structural schematic diagram of semiconductor devices forming process；
Fig. 3 to Figure 11 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
Referring to FIG. 1, providing substrate 100, there is fin 110 and separation layer 101, the separation layer in the substrate 100
101 covering 110 partial sidewalls of fin；Dielectric layer 130 is formed in the substrate 100, the dielectric layer 130 has opening 150,
130 top surface of dielectric layer is higher than the top surface of fin 110, and the opening 150 exposes 110 top surface of fin；
Boundary layer 161 is formed on 110 surface of fin that 150 bottom-exposeds of the opening go out；In 150 side walls of the opening and boundary layer
161 surfaces form gate dielectric layer 162, are formed on 162 surface of gate dielectric layer and adjust work-function layer 163；Adjusting work-function layer 163
Surface forms sacrificial layer 164；After forming sacrificial layer 164, the gate dielectric layer 162 is made annealing treatment.
Referring to FIG. 2, removing sacrificial layer 164 after annealing, exposes and adjust work-function layer 163.
Work content table structure and gate electrode layer are formed in extended meeting opening 150 afterwards.
Wherein, the threshold voltage for adjusting work-function layer 163 and being used to adjust semiconductor devices.Annealing process be used for so that
Gate dielectric layer 162 is finer and close.Sacrificial layer 164 is used to protect boundary layer 161 in annealing process, and boundary layer 161 is avoided to thicken.
However, the material of the sacrificial layer 164 is unformed silicon, the material for adjusting work-function layer 163 is TiN, TiN
It is easy to generate metal silicide with unformed pasc reaction, when subsequent removal sacrificial layer 164, metal silicide is difficult to remove, and can deposit
It is to adjust the surface of work-function layer 163.Due to the presence of metal silicide, the threshold voltage adjustments effect of work-function layer is adjusted
It is bad, will cause the threshold voltage of device drift and serious load effect.
Meanwhile temperature is higher in annealing process, is easy driving oxonium ion migration, and the material of sacrificial layer 164 is without fixed
Type silicon, unformed silicon are easy the oxonium ion of absorption, cause oxonium ion to enter in sacrificial layer 164, so as to cause in gate dielectric layer 162
Oxonium ion pass through and adjust work-function layer 163 and enter in sacrificial layer 164, the decline of oxonium ion content in gate dielectric layer 162,
Oxygen ion hole is formed in gate dielectric layer 162, causes the threshold voltage of semiconductor devices to increase, and leakage current is caused to increase,
Influence the performance of semiconductor devices.
The present invention is adjusting work-function layer surface formation barrier layer, is formed to be formed in barrier layer surface again behind barrier layer and be sacrificed
Layer；Barrier layer isolation adjusts work-function layer and sacrificial layer, and sacrificial layer removes not residual when sacrificial layer not with barrier reaction
It stays, will not influence the formation of semiconductor devices.By the blocking on barrier layer, in annealing process, oxonium ion is more difficult to get access to sacrificing
In layer, the oxonium ion damage in gate dielectric layer is less, forms less oxygen ion hole, the leakage current of semiconductor devices is relatively
It is small.To improve the performance of device.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 3 to Figure 11 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 3, substrate is provided.
In the present embodiment, the substrate includes: first area A, second area B, third region C and the fourth region D.At it
In his embodiment, the substrate can also be only included: first area and second area or the substrate can also only include: the
One region, second area and third region or substrate can also only include: first area, second area and the fourth region.
In the present embodiment, the first area A is used to form ultralow threshold value voltage NMOS transistor；The second area B
It is used to form high threshold voltage NMOS transistor；The third region C is used to form high threshold voltage PMOS transistor；Described
Four region D are used to form ultralow threshold value voltage PMOS transistor.
It is to form fin field effect with first area A, second area B, third region C and the fourth region D in the present embodiment
Transistor is answered to be illustrated for example.In other embodiments, first area A, second area B, third region C and the fourth region
D is used to form the MOS transistor of plane formula.
In the present embodiment, the substrate includes: semiconductor substrate 200 and several fins positioned at 200 surface of semiconductor substrate
Portion 201.In other embodiments, the substrate can also be planar substrate.
In the present embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.The semiconductor substrate 200 can also be
Polysilicon or amorphous silicon.The material of the semiconductor substrate 200 can also be the semiconductor materials such as germanium, SiGe, GaAs.
In the present embodiment, the fin 201 is formed by the graphical semiconductor substrate 200.In other embodiments
In, it may is that formation fin material layer on the semiconductor substrate, then the graphical fin material layer, to be formed
Fin 201.
In the present embodiment, the material of the fin 201 is monocrystalline silicon.In other embodiments, the material of fin 201 is single
Brilliant germanium silicon or other semiconductor materials.
In the present embodiment, also there is separation layer (not shown) in the semiconductor substrate 200, the separation layer covers fin
Partial sidewall surface, and the insulation surface be lower than the fin top surface.The material of the separation layer includes oxygen
SiClx.
With continued reference to Fig. 3, dielectric layer 250 is formed on the substrate, is had in the dielectric layer 250 through dielectric layer
First opening 210.
The dielectric layer 250 is for realizing the electric isolution between different crystal pipe.
The forming method of first opening 210 includes: to form the first pseudo- grid structure, the described first pseudo- grid in substrate surface
Structure includes the first pseudo- gate dielectric layer and the first dummy gate layer positioned at the first pseudo- gate dielectric layer surface；In the substrate surface shape
At dielectric layer, the surface of the dielectric layer is flushed with the top surface of the described first pseudo- grid structure；Remove the described first pseudo- grid knot
Structure forms the first opening in dielectric layer.
The forming method of first opening 210 further include: before forming dielectric layer 250, in the described first pseudo- grid knot
The first source and drain doping area is formed in the substrate of structure two sides.
Also there is the second opening 220, third opening 230 and the 4th opening 240, described second opens in the dielectric layer 250
Mouth 220, third opening 230 and the 4th opening 240 run through the dielectric layer 250.
Specifically, respectively corresponding to be formed in the substrate of first area A, second area B, third region C and the fourth region D
First dummy gate structure, the second dummy gate structure, third dummy gate structure and the 4th dummy gate structure；In the first dummy grid knot
Source and drain doping area is formed in structure, the second dummy gate structure, third dummy gate structure and the substrate of the 4th dummy gate structure two sides
202；After forming source and drain doping area, it is pseudo- that the first dummy gate structure of covering, the second dummy gate structure, third are formed in the substrate
The initial medium layer of gate structure and the top surface of the 4th dummy gate structure；The initial medium layer is carried out at planarization
Reason, exposes the top of first dummy gate structure, the second dummy gate structure, third dummy gate structure and the 4th dummy gate structure
Portion surface forms dielectric layer 220；After forming dielectric layer 220, the first dummy gate structure of removal, the second dummy gate structure, third are pseudo-
Gate structure and the 4th dummy gate structure respectively correspond to form the first opening 210, second opening 220, third opening 230 and the
Four openings 240.
First opening 210 is located in the dielectric layer 250 on the A of substrate first area, and second opening 220 is located at base
In dielectric layer 250 on the second area B of bottom, the third opening 230 is located in the dielectric layer 250 on substrate third region C, institute
The 4th opening 240 is stated to be located in the dielectric layer 250 on substrate the fourth region D.
First dummy gate structure covers the fin 201 on the surface first area A across the fin 201 on the first area surface A
Atop part surface and partial sidewall surface.Fin 201 of second dummy gate structure across second area B surface, covering second
The atop part surface and partial sidewall surface of the fin 201 of region B surface.Third dummy gate structure is across third region C table
The fin 201 in face covers the atop part surface and partial sidewall surface of the fin 201 of third region C Surface.4th dummy grid
Structure covers the atop part surface and part of the fin 201 on the surface the fourth region D across the fin 201 on the surface the fourth region D
Sidewall surfaces.
First dummy gate structure includes the first pseudo- gate dielectric layer of the fin 201 across the first area surface A and is located at pair
First dummy gate layer on the first pseudo- gate dielectric layer surface；Second dummy gate structure includes the fin 201 across second area B surface
The second pseudo- gate dielectric layer and the second dummy gate layer positioned at the second pseudo- gate dielectric layer surface；Third dummy gate structure include across
The third puppet gate dielectric layer of the fin 201 of third region C Surface and positioned at the third dummy grid to third puppet gate dielectric layer surface
Layer；4th dummy gate structure includes the 4th pseudo- gate dielectric layer of the fin 201 across the surface the fourth region D and is located to the 4th puppet
4th dummy gate layer on gate dielectric layer surface.
First pseudo- gate electrode layer, the second dummy gate layer, third dummy gate layer and the 4th dummy gate layer material be polysilicon.
In the present embodiment, the first pseudo- gate dielectric layer, the second pseudo- gate dielectric layer, third puppet gate dielectric layer and the 4th pseudo- gate dielectric layer material
For silica.
The source and drain doping area 202 include positioned at the first dummy gate structure two sides fin in the first source and drain doping area,
The second source and drain doping area in the fin of the second dummy gate structure two sides, in the fin of third dummy gate structure two sides
Third source and drain doping area and the 4th source and drain doping area in the fin of the 4th dummy gate structure two sides.
With reference to Fig. 4, boundary layer 203 is formed in first opening, 210 bottoms；After forming the boundary layer 203, described
First 210 side walls of opening and 203 surface of boundary layer form gate dielectric layer 204.
The boundary layer 203 is used to improve the bond strength between the gate dielectric layer 204 and fin 201, and for repairing
The defect of interface between the multiple gate dielectric layer 204 and fin 201.
The formation process of the boundary layer 203 is oxidation technology, such as thermal oxidation technology or wet process oxidation technology.
In the present embodiment, the formation process of the boundary layer 203 is thermal oxidation technology.
The material of the boundary layer 203 is silica or silicon oxynitride.
In the present embodiment, the material of the boundary layer 203 is silica；The boundary layer 203 with a thickness of 10 angstroms to 15
Angstrom.Interface state is bad when the thickness of the boundary layer 203 is too small, can make device threshold electric when 203 thickness of boundary layer is blocked up
Pressure is raised, and device requirement is not met.
The material of the gate dielectric layer 204 is high k (K is greater than 3.9) dielectric material, the material packet of the gate dielectric layer 204
Include hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, oxygen
Change strontium titanium or aluminium oxide.
In the present embodiment, the material of the gate dielectric layer 204 is hafnium oxide.
In the present embodiment, the gate dielectric layer 204 with a thickness of 10 angstroms~40 angstroms.
The technique for forming the gate dielectric layer 204 includes chemical vapor deposition process, physical gas-phase deposition or atom
Layer depositing operation.
In the present embodiment, the technique for forming the gate dielectric layer 204 is chemical vapor deposition process.
The boundary layer 203 is formed in the partial sidewall and atop part table for the fin 201 that the first opening 210 exposes
Face.
The boundary layer 203 is also located on second opening 220, third opening 230 and the 4th 240 bottoms of opening；Tool
Body, the boundary layer 203 is formed in the fin 201 that the second opening 220, third opening 230 and the 4th opening 240 expose
Partial sidewall and atop part surface.
The gate dielectric layer 204 is also located at the second opening 220, third opening 230 and the 4th 240 side walls of opening；Specifically
The gate dielectric layer 204 be also located at the second opening 220 side wall and positioned at the second 220 bottoms of opening 203 surface of boundary layer, the
Three opening 230 side wall and positioned at third be open 230 bottoms 203 surface of boundary layer and the 4th opening 240 side wall and be located at
203 surface of boundary layer of 4th 240 bottoms of opening.
With reference to Fig. 5, after forming the gate dielectric layer 204, is formed in first opening 210 and be located at gate dielectric layer 204
The adjusting work-function layer 205 on surface and positioned at adjust 205 surface of work-function layer barrier layer 206.
The adjusting work-function layer 205 avoids subsequent main work-function layer, grid layer for protecting the gate dielectric layer 204
Material spread into the gate dielectric layer 204, to guarantee that the dielectric constant of gate dielectric layer 204 is not susceptible to change, then institute
The threshold voltage of the transistor of formation is not susceptible to deviate.
The material for adjusting work-function layer 205 includes TiN or TaN.
In the present embodiment, the material for adjusting work-function layer 205 is TiN；It is described adjust work function with a thickness of 10 angstroms
~25 angstroms.Gate dielectric layer 204, the adjusting work content cannot be effectively protected less than 10 angstroms in 205 thickness of adjusting work-function layer
Several layers of 205 thickness are greater than 25 angstroms, have raised the threshold voltage of semiconductor devices, have been unfavorable for the performance of semiconductor devices.
It is described adjust work-function layer 205 formation process include chemical vapor deposition process, physical gas-phase deposition or
Atom layer deposition process.
The barrier layer 206 is used to be subsequently formed stop-layer when main work-function layer, while as in annealing process
Oxonium ion barrier layer 206 and it is subsequent removal sacrificial layer 207 when protective layer.
The material on the barrier layer 206 includes TaN, Ta and combinations thereof.
In the present embodiment, the material on the barrier layer 206 is TaN.
The first initial workfunction layer, the second initial workfunction layer, third initial power barrier layer 206 and be subsequently formed
The material of function layer and the 4th initial workfunction layer is different, so that at the beginning of the barrier layer 206 and the first initial workfunction layer, second
There is selectivity between beginning work-function layer, third initial workfunction layer and the 4th initial workfunction layer.
In the present embodiment, barrier layer 206 with a thickness of 10 angstroms~20 angstroms.Adjust work-function layer 205, barrier layer 206 and after
The continuous main work-function layer formed adjust jointly semiconductor devices to be formed threshold voltage, the 206 thickness mistake of barrier layer
Thickness is unfavorable for the adjusting of threshold voltage of semiconductor device, and 206 thickness of barrier layer is excessively thin, forms main work content in subsequent be used as
It when several layers of etching stop layer, can be etched away, and then adjusting work-function layer can not be protected, to influence the property of semiconductor devices
Energy.
The formation process on the barrier layer 206 includes chemical vapor deposition process, physical gas-phase deposition or atomic layer
Depositing operation.
The adjusting work-function layer 205 is also located in the second opening 220, third opening 230 and the 4th opening 240；Specifically
The adjusting work-function layer 205 be also located at 204 surface of gate dielectric layer in the second opening 220, third opening 230 in grid be situated between
204 surface of gate dielectric layer in 204 surface of matter layer and the 4th opening 240.
The barrier layer 206 is also located in the second opening 220, third opening 230 and the 4th opening 240；It is specific described
Barrier layer 206 is also located at 205 surface of adjusting work-function layer in the second opening 220, the adjusting work-function layer in third opening 230
205 surface of adjusting work-function layer in 205 surfaces and the 4th opening 240.
With reference to Fig. 6, after forming the barrier layer 206, is formed in first opening 210 and be located at 206 surface of barrier layer
Sacrificial layer 207.
In the opening of sacrificial layer 207 second 220, third opening 230 and the 4th opening 240；The specific sacrificial layer
207 are also located at 206 surface of barrier layer in the second opening 220,206 surface of barrier layer in third opening 230 and the 4th opening
206 surface of barrier layer in 240.
The sacrificial layer 207 is used to protect boundary layer 203 in annealing process, and the oxonium ion in air is avoided to enter
Into the fin 201 of 203 lower section of boundary layer, so that the thickness of boundary layer 203 thickens, so that the threshold voltage of device be caused to float
It moves.
The material of the sacrificial layer 207 includes unformed silicon, amorphous silicon.The material selection of the sacrificial layer 207 is unformed
Silicon, the benefit of amorphous silicon: processing procedure is simple, easily removes.
In the present embodiment, the material of the sacrificial layer 207 is unformed silicon.
In the present embodiment, the sacrificial layer 207 with a thickness of 30 angstroms~100 angstroms.
The sacrificial layer thickness is excessively thin, in annealing process, sacrificial layer can not the first boundary layer of effective protection it is not oxidized；Institute
It states initial sacrificial thickness and spends thickness, technique is caused to waste.
The formation process of the sacrificial layer 207 includes chemical vapor deposition process, physical gas-phase deposition or atomic layer
Depositing operation.
It with reference to Fig. 7, is formed after the sacrificial layer 207, the gate dielectric layer 204 is made annealing treatment.
The quality for improving gate dielectric layer 204 is made annealing treatment, so that gate dielectric layer 204 is finer and close, to improve grid
The performance of dielectric layer 204.
The annealing includes laser annealing or spike annealing.
The parameter of the annealing includes: that the temperature range of the annealing is 800 degrees Celsius~1100 degrees Celsius,
The time of the annealing is 5 seconds~100 seconds, and the gas of the annealing utilized is nitrogen, the flow of the nitrogen
Range is 10sccm~1000sccm.
The annealing includes: that laser annealing and spike annealing heated up using the benefit of laser annealing or spike annealing
Journey is very fast, avoids temperature-rise period that the ion of the doped region of semiconductor devices is caused to have biggish diffusion, improves doped region
Stability.
In annealing process, due to the presence of sacrificial layer 207, the material of sacrificial layer 207 is unformed silicon, sacrificial layer 207 with
Oxygen reaction, has consumed most oxygen, enters oxygen in fin 201 and reduces, to boundary layer 203 thicken compared with
Small, 203 thickness of boundary layer is relatively small, to improve the performance of semiconductor devices.
Meanwhile by the blocking on barrier layer 206, in annealing process, oxonium ion is more difficult to get access into sacrificial layer 207, and grid are situated between
Oxonium ion loss in matter layer 204 is less, forms less oxygen ion hole, the leakage current of semiconductor devices is relatively small.From
And improve the performance of device.
With reference to Fig. 8, after annealing, the sacrificial layer 207 is removed, barrier layer 206 is exposed.
The technique for removing sacrificial layer 207 is dry etch process or wet-etching technology.
In the present embodiment, the technique of removal sacrificial layer 207 is wet-etching technology, the etching liquid of the wet-etching technology
For tetramethyl ammonium hydroxide solution.
The material on the barrier layer 206 is TaN, and the material of sacrificial layer 207 is unformed silicon, therebetween without reaction life
At metal silicide, sacrificial layer 207 is only removed, removes simple process, residual is few, reduces the shadow to device work-function layer
It rings, to improve the performance of semiconductor devices.
After removing sacrificial layer 207, gate electrode layer is formed in first opening 210, the filling of gate electrode layer 217 is full
First opening 210.
In the present embodiment further include: after removing the sacrificial layer 207, formed before gate electrode layer 217, on the barrier layer
206 surfaces form main work-function layer.
The main work-function layer includes the first main work-function layer being located in the first opening 210, is located in the second opening 220
The second main work-function layer, the main work-function layer of third in third opening 230, the in the 4th opening 240 the 4th main
Work-function layer.
With reference to Fig. 9, after removing the sacrificial layer 207, in 206 table of barrier layer of the first opening 210 side walls and bottom
The main work-function layer in face first.
Correspondingly, in 206 the second main work-function layer of surface of barrier layer of the second opening 220 side walls and bottom；Institute
State the 206 main work-function layer of surface third of barrier layer of third opening 230 side walls and bottom；It is described 4th opening 240 side walls and
The main work-function layer in 206 surface of barrier layer the 4th of bottom.
In the present embodiment, in the present embodiment, the first main work-function layer, the second main work-function layer, the main work function of third
The forming method of layer and the 4th main work-function layer includes: in 210, second opening 220 of the first opening, 230 and of third opening
First initial workfunction layer 211 is formed on the side wall of the 4th opening 240 and bottom；220 and of removal the 210, second opening of the first opening
After the first initial workfunction layer 211 in third opening 230, in 210, second opening 220 of the first opening, third opening
230 and the 4th opening 240 side wall and bottom formed the second initial workfunction layer 212；Removal the 210, second opening of the first opening
After the second initial workfunction layer 212 in 220, in 210, second opening 220 of the first opening, third opening 230 and the 4th
Third initial workfunction layer 213 is formed on the side wall of opening 240 and bottom；Third initial workfunction in the first opening 210 of removal
Layer 213 is formed in the side wall of 210, second opening 220 of the first opening, third opening 230 and the 4th opening 240 and bottom
4th initial workfunction layer 214.
In the present embodiment, the first area A is used to form ultralow threshold value voltage NMOS transistor；The second area B
It is used to form high threshold voltage NMOS transistor；The third region C is used to form high threshold voltage PMOS transistor；Described
Four region D are used to form ultralow threshold value voltage PMOS transistor.
In the present embodiment, the first initial workfunction layer 211, the second initial workfunction layer 212, third initial workfunction
The material of layer 213 is P-type workfunction layer；The 4th initial workfunction layer 214 is N-type workfunction layer.
The first initial workfunction layer 211, the second initial workfunction layer 212, third initial workfunction layer material packet
It includes: titanium nitride, tantalum carbide, molybdenum nitride or tantalum nitride.
The material of the 4th initial workfunction layer 214 includes: TaC, Ti, Al or TiAl.
In the present embodiment, the first initial workfunction layer 211, the second initial workfunction layer 2122, the initial work content of third
Several layers of material is titanium nitride, and the material of the 4th initial workfunction layer 214 is TiAl.
Wherein, the described first main work-function layer includes the 4th initial workfunction layer 214 in the first opening 210；The
Two main work-function layers include the 4th initial workfunction layer 214 and third initial workfunction layer 213 in the second opening 220；
The main work-function layer of third includes the 4th initial workfunction layer 214, third initial workfunction layer 213 in third opening 230
With the second initial workfunction layer 212；4th main work-function layer includes the 4th initial workfunction layer in the 4th opening 240
214, third initial workfunction layer 213, the second initial workfunction layer 212 and the first initial workfunction layer 211.
With reference to Figure 10, after forming main work-function layer, layer of gate electrode material 216 is formed on the main work-function layer surface.
The technique for forming layer of gate electrode material 216 includes: that plasma activated chemical vapour deposition technique, low pressure chemical phase are heavy
Product technique, electroplating technology or sputtering technology.
The material of the layer of gate electrode material 216 is metal material, and the metal material includes copper, tungsten, nickel, chromium, titanium, tantalum
With one of aluminium or multiple combinations.
The formation process of the layer of gate electrode material 216 is one of physical gas-phase deposition and electroplating technology or two
Kind combination.The formation process of layer of gate electrode material described in the present embodiment is physical gas-phase deposition.
With reference to Figure 11, after forming layer of gate electrode material 216, planarizes the layer of gate electrode material 216, barrier layer 206, adjusts
Work-function layer 205, gate dielectric layer 204 are saved, until exposing the top surface of dielectric layer 250, forms gate electrode layer 217, the grid
Full first opening 210 of the filling of electrode layer 217.
In the present embodiment, planarizes the layer of gate electrode material 216, barrier layer 206, adjusts work-function layer 205, gate medium
The 204, first initial workfunction layer 211 of layer, the second initial workfunction layer 212, third initial workfunction layer 213 and the 4th are initial
Work-function layer 214 forms gate electrode layer 217 until exposing the top surface of dielectric layer 250.
The gate electrode layer 217 is also located in the second opening 220, third opening 230 and the 4th opening 240, fills full institute
State the second opening 220, third opening 230 and the 4th opening 240.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of semiconductor devices characterized by comprising
Substrate is provided；
Dielectric layer is formed on the substrate, and there is the first opening through dielectric layer, first opening in the dielectric layer
Expose part of substrate surface.
Boundary layer is formed in first open bottom；
After forming the boundary layer, gate dielectric layer is formed in first opening sidewalls and interface layer surfaces；
The adjusting work-function layer for being located at gate dielectric layer surface is formed in first opening；
It is formed in first opening and is located at the barrier layer for adjusting work-function layer surface；
The sacrificial layer for being located at barrier layer surface is formed on the dielectric layer and in the first opening；
It is formed after the sacrificial layer, the gate dielectric layer is made annealing treatment；
After annealing, the sacrificial layer is removed；
After removing the sacrificial layer, gate electrode layer, the gate electrode layer filling full described first are formed in the barrier layer surface
Opening.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the sacrificial layer includes nothing
Sizing silicon, amorphous silicon.
3. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material on the barrier layer includes
TaN, Ta and combinations thereof.
4. the forming method of semiconductor devices as described in claim 1, which is characterized in that barrier layer with a thickness of 10 angstroms~20
Angstrom.
5. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material for adjusting work-function layer
For TiN or TaN.
6. the forming method of semiconductor devices as described in claim 1, which is characterized in that annealing include laser annealing or
Spike annealing.
7. the forming method of semiconductor devices as claimed in claim 6, which is characterized in that the parameter packet of the annealing
Include: the temperature range of the annealing is 800 degrees Celsius~1100 degrees Celsius, and the time of the annealing is 5 seconds~100
Second, the gas of the annealing utilized is nitrogen, and the range of flow of the nitrogen is 10sccm~1000sccm.
8. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the gate dielectric layer includes
Hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, oxidation
Strontium titanium or aluminium oxide.
9. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the boundary layer is oxidation
Silicon or silicon oxynitride.
10. the forming method of semiconductor devices as described in claim 1, which is characterized in that the substrate includes: semiconductor lining
Bottom, positioned at the fin of semiconductor substrate surface；Positioned at the separation layer of semiconductor substrate surface, the separation layer covering part fin
Side wall, and the insulation surface be lower than the fin top surface.
11. the forming method of semiconductor devices as claimed in claim 10, which is characterized in that first opening is across described
Fin, and first opening exposes part fin side wall and top surface.
12. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that the boundary layer is formed in first
The partial sidewall for the fin that opening exposes and atop part surface.
13. the forming method of semiconductor devices as claimed in claim 12, which is characterized in that the material of the fin includes single
Crystal silicon, germanium or SiGe.
14. the forming method of semiconductor devices as described in claim 1, which is characterized in that the dielectric layer and the first opening
Forming method include: to form the first pseudo- grid structure in substrate surface, the described first pseudo- grid structure includes the first pseudo- gate dielectric layer
With the first dummy gate layer for being located at the first pseudo- gate dielectric layer surface；Dielectric layer is formed in the substrate surface, the dielectric layer
Surface is flushed with the top surface of the described first pseudo- grid structure；The described first pseudo- grid structure is removed, forms first in dielectric layer
Opening.
15. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that further include: forming dielectric layer
Before, the first source and drain doping area is formed in the substrate of the described first pseudo- grid structure two sides.
16. the forming method of semiconductor devices as described in claim 1, which is characterized in that further include: remove the sacrificial layer
Afterwards, it is formed before gate electrode layer, forms main work-function layer in the barrier layer surface.
17. the forming method of semiconductor devices as claimed in claim 16, which is characterized in that also have the in the dielectric layer
Two openings, third opening and the 4th opening, second opening, third opening and the 4th opening run through the dielectric layer；It is described
Boundary layer is also located in second opening, third opening and the 4th open bottom；The gate dielectric layer be also located at the second opening,
Third opening and the 4th opening sidewalls；The adjusting work-function layer is also located in the second opening, third opening and the 4th opening；Institute
Barrier layer is stated to be also located in the second opening, third opening and the 4th opening；The opening of sacrificial layer second, third opening and the 4th
In opening；The gate electrode layer is also located in the second opening, third opening and the 4th opening；The main work-function layer includes being located at
The first main work-function layer in first opening, the second main work-function layer in the second opening, the in third opening
Three main work-function layers, the 4th main work-function layer in the 4th opening.
18. the forming method of semiconductor devices as claimed in claim 17, which is characterized in that the first main work-function layer,
The forming method of second main work-function layer, the main work-function layer of third and the 4th main work-function layer includes: in first opening, the
First initial workfunction layer is formed on two openings, the side wall of third opening and the 4th opening and bottom；The first opening of removal, second open
Mouth is open in first opening, the second opening, third with after the first initial workfunction layer in third opening and the 4th is open
Side wall and bottom formed the second initial workfunction layer；After the second initial workfunction layer in the first opening of removal, the second opening,
Third initial workfunction layer is formed in the side wall of first opening, the second opening, third opening and the 4th opening and bottom；It goes
Except the third initial workfunction layer in the first opening, in the side of first opening, the second opening, third opening and the 4th opening
4th initial workfunction layer is formed on wall and bottom；
The first main work-function layer includes the 4th initial workfunction layer in the first opening；Second main work-function layer includes second
The 4th initial workfunction layer and third initial workfunction layer in opening；The main work-function layer of third includes the 4 in third opening
Initial workfunction layer, third initial workfunction layer and the second initial workfunction layer；4th main work-function layer includes in the 4th opening
The 4th initial workfunction layer, third initial workfunction layer, the second initial workfunction layer and the first initial workfunction layer.
19. a kind of according to claim 1 to the semiconductor devices that 18 any one methods are formed.
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| CN113539824A (en) * | 2020-04-17 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| WO2023133997A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Method for preparing semiconductor device, and semiconductor device |
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| CN107437562A (en) * | 2016-05-27 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113539824A (en) * | 2020-04-17 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| WO2023133997A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Method for preparing semiconductor device, and semiconductor device |
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