CN110213168B - Data conversion flow control method and device for converting FC (fiber channel) into Ethernet - Google Patents
Data conversion flow control method and device for converting FC (fiber channel) into Ethernet Download PDFInfo
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- CN110213168B CN110213168B CN201810167956.9A CN201810167956A CN110213168B CN 110213168 B CN110213168 B CN 110213168B CN 201810167956 A CN201810167956 A CN 201810167956A CN 110213168 B CN110213168 B CN 110213168B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
- H04L43/0882—Utilisation of link capacity
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
Abstract
The invention relates to a data conversion flow control method and device for converting FC into Ethernet, wherein the method detects the data flow of Ethernet when the FC data is converted with the Ethernet data; comparing the data traffic of the Ethernet with a set data traffic upper limit value: and when the data flow of the Ethernet is judged to be larger than the set data flow upper limit value, controlling and triggering FC data back pressure. The invention does not use the traditional mechanism for triggering FC data back pressure, when the FC data is converted with the Ethernet data, the original FC data flow is detected, instead, the Ethernet data flow is actively detected, and when the Ethernet data flow is detected to be overlarge, the FC data back pressure is triggered. That is to say, the FC data backpressure is triggered in advance, so that the situation of data loss caused by large flow is avoided, the FC data and the ethernet data are ensured not to be lost during conversion transmission, and the reliability of data transmission is improved.
Description
Technical Field
The invention belongs to the technical field of optical fiber transmission, and particularly relates to a data conversion flow control method and device for converting FC (fiber channel) into Ethernet.
Background
FC-AE is a novel optical fiber channel technology, has the characteristics of high broadband, low time delay, high reliability and high anti-interference performance, and is widely used in the fields of aerospace and the like. The FC network conforming to the FC-AE-ASM protocol is applied to various types of products in the aviation field, and provides communication support for interconnection among new generation airborne subsystems.
In the overall design process of the system, when the FC network is used as the backbone network, the ethernet network is selected as the local bus in the subsystem in consideration of the communication requirements among the functional modules in the subsystem, the effective data volume, the compatibility of the existing devices, the technical maturity and other factor requirements. Meanwhile, the FC has a data back pressure mechanism, and when the data flow of the FC reaches the upper limit of the FC data bandwidth, the data back pressure is triggered, so that the phenomenon of data packet loss caused by overlarge data flow is avoided.
However, FC bus bandwidths include 2.125Gbps, 4.25Gbps, and 8.5Gbps, which are much larger than the Ethernet bandwidth of a gigabit Ethernet. When the subsystem is interconnected and communicated with the FC backbone network, and FC data sends signals to a network port, when the FC data flow reaches the upper limit of the FC data bandwidth, the data backpressure is not triggered, but the data flow may already exceed the upper limit of the bandwidth processed by the gigabit Ethernet. At this time, a phenomenon of packet loss due to insufficient ethernet data bandwidth may occur greatly, so that the FC network with high reliability becomes unreliable.
Disclosure of Invention
The invention aims to provide a data conversion flow control method and a data conversion flow control device for converting FC (fiber channel) data into Ethernet, which are used for solving the problem of data loss in the prior art when FC data and Ethernet data are converted.
In order to solve the technical problems, the technical scheme of the invention is as follows:
the invention provides a data conversion flow control method for converting FC into Ethernet, which comprises the following steps:
detecting the data flow of the Ethernet port when the FC port and the Ethernet port perform data conversion;
comparing the data traffic of the Ethernet port with a set data traffic upper limit value:
and when the data flow of the Ethernet port is judged to be larger than the set data flow upper limit value, controlling to trigger FC data back pressure to enable the FC port to stop receiving data.
Further, the data traffic of the ethernet port is detected by detecting the number of ethernet frames buffered by the ethernet port.
Further, when the data flow of the ethernet port is judged to be less than or equal to the set data flow upper limit value, the FC port is restored to the state of receiving data.
Further, the data traffic upper limit value is fixed, or is set through an external configuration interface.
The invention also provides a data conversion flow control device for converting FC into Ethernet, which comprises a processor, a memory and an interface chip, wherein the processor is used for executing instructions to realize the following method:
detecting the data flow of the Ethernet port when the FC port and the Ethernet port perform data conversion;
comparing the data traffic of the Ethernet port with a set data traffic upper limit value:
and when the data flow of the Ethernet port is judged to be larger than the set data flow upper limit value, controlling to trigger FC data back pressure to enable the FC port to stop receiving data.
Further, the data traffic of the ethernet port is detected by detecting the number of ethernet frames buffered by the ethernet port.
Further, when the data flow of the ethernet port is judged to be less than or equal to the set data flow upper limit value, the FC port is restored to the state of receiving data.
Further, the data traffic upper limit value is fixed, or is set through an external configuration interface.
The invention has the beneficial effects that:
the FC-to-Ethernet data conversion flow control method does not use a traditional FC data back pressure triggering mechanism independently, changes the original detection of the data flow of the FC port into the active detection of the data flow of the Ethernet port when the FC port and the Ethernet port perform data conversion, and triggers the FC data back pressure when the data flow of the Ethernet port is detected to be overlarge so that the FC port stops receiving data. That is to say, the FC data back pressure is triggered in advance, the data loss caused by large flow is avoided, the FC data and Ethernet data transmission and conversion are ensured not to lose packets, and the reliability of data transmission is improved.
The FC-to-Ethernet data conversion flow control device is used for realizing the FC-to-Ethernet data conversion flow control method, can realize data conversion of the FC port and the Ethernet port, can ensure that no packet loss occurs in transmission and conversion of FC data and Ethernet data, and improves the reliability of data transmission.
Drawings
FIG. 1 is a schematic diagram of a data conversion device;
FIG. 2 is a functional block diagram of an FPGA;
FIG. 3 is a functional block diagram of an Ethernet data processing module;
FIG. 4 is a functional block diagram of a data conversion module.
Detailed Description
In order to implement the FC to ethernet data conversion flow control method of the present invention, a data conversion device is now designed.
As shown in fig. 1, the apparatus includes an FPGA chip, an optical module, a power conversion chip, and an ethernet data processing chip. The device can convert two paths of Ethernet signals into standard FC signals for point-to-point transmission or transmission through an FC switch.
The FPGA is a core processing chip of the conversion device and is used for realizing the functions of protocol conversion, state reporting and the like between Ethernet data and FC data. Here, Xilinx Kintex7xc7k325t-ffg676 chip was used.
The Ethernet data processing chip is used for receiving and transmitting signals and interacting with the FPGA through the GMII interface. The 88E1111 of Marvell is used here.
The device also comprises a serial port module and an indicator light module. The device can be configured through a serial port, and can also report some self state information through the serial port. The indicating lamp module can display the working state of the current conversion device in real time.
And in order to ensure the reliable transmission of link data, the FC data adopts a credit value back pressure mechanism to ensure that the data flow of a port is in a reasonable range, thereby avoiding the loss of data packets due to insufficient bandwidth.
In order to realize the conversion between the ethernet data and the FC data, as shown in fig. 2, the FPGA chip includes an ethernet data cache monitoring module, an FC credit back pressure control module, an FC data processing module, a data conversion module, an ethernet data cache module (including two ethernet data cache modules in fig. 2), and an ethernet data processing module (including two ethernet data processing modules in fig. 2).
Generally speaking, the state information of the ethernet cache (i.e. the data traffic of the ethernet port) is detected and stored by the ethernet data cache monitoring module, and the state information of each cache can be compared with the corresponding set upper limit value of the data traffic in real time, and when the data traffic of the ethernet port is judged to be greater than the set upper limit value of the data traffic, FC data backpressure is triggered by the FC credit backpressure control module, so that the FC port stops receiving data. The method does not trigger FC data back pressure when the upper limit of the FC data bandwidth is reached, but controls the FC not to receive data any more when the data flow of the Ethernet is larger, thereby preventing the phenomenon of data packet loss from occurring, preventing the phenomenon of data packet loss from the source and improving the reliability of data transmission.
Each block designed in the FPGA will be described and illustrated in detail below. Note that each module herein is a software module, not an actual hardware configuration.
1. Ethernet data cache monitoring module
The module can collect the states of all Ethernet caches, namely the data traffic of the Ethernet can be expressed by the number of Ethernet frames; and the state of each cache can be compared with the corresponding set data flow upper limit value in real time. In order to clearly show the information, a cache state table is maintained in the module, and the collected states of the caches and the comparison results of the caches are stored. The table may be as shown in table 1.
TABLE 1
And if the data storage amount of a certain cache exceeds the set data flow upper limit value corresponding to the storage, setting the state information corresponding to the cache to be high, and informing the FC credit back pressure control module.
2. FC credit back pressure control module
The FC credit back pressure control module can monitor the state information corresponding to each cache in the Ethernet cache monitoring module in real time and control the credit value of the FC port according to the state information.
If the state information of the Ethernet cache is detected to be high, namely the cache exceeds the set data flow upper limit value, controlling the current port not to send the RDY signal any more, and stopping receiving the data by the FC port; if the state information of the Ethernet cache is detected to be low, namely the cache does not exceed the set data flow upper limit value any more, the RDY signal of the current port is restored to normal sending, and data can be received normally.
3. Ethernet data processing module
As shown in fig. 3, the module includes a receiving-end cache module, a received frame counting module, an MAC address extraction module, a transmitting-end cache module, and a transmitted frame counting module.
The receiving end cache module stores the Ethernet data from the outside, and other modules can read the data from the receiving end cache by receiving the read enabling control signal generated by the frame counting module.
The received frame counting module can record the number of the Ethernet data frames stored in the current receiving end buffer. When one frame of data is completely written into the receiving end for buffering, the module adds 1; when one frame of data is completely read from the receiving end buffer, the module subtracts 1. And meanwhile, the module also generates a receiving end cache read enabling control signal, when the counted number of frames in the cache is more than or equal to 1, the read enabling control signal is started, otherwise, the read enabling control signal is closed, and the data cannot be read from the receiving end cache.
The MAC address extraction module extracts a destination MAC address and a source MAC address from the received ethernet data frame. The destination MAC address is transmitted to the next module for use, the source MAC address is recorded in the MAC address table and used as the identifier of the current network port, and the correct distribution of Ethernet signals can be realized by inquiring the address information.
The sending end cache module stores the Ethernet data from the FPGA, reads the data frame by frame from the sending end cache through the read enabling control signal generated by the sending frame counting module and sends the data to an external chip.
The sending frame counting module can record the number of the Ethernet data frames stored in the current sending end cache. When one frame of data is completely written into the receiving end for buffering, the module adds 1; when there is a frame of data completely read from the start buffer, the module decrements 1. And meanwhile, the module also generates a sending end cache read enabling control signal, when the counted number of frames in the cache is more than or equal to 1, the read enabling control signal is started, otherwise, the read enabling control signal is closed, and the data cannot be read from the cache. Thereby ensuring that the data frame can be completely transmitted frame by frame.
4. Data conversion module
One end of the data conversion module converts the Ethernet data frame into an FC data frame, and the other end converts the received FC data frame into the Ethernet data frame. As shown in fig. 4, the data conversion module includes a destination MAC address mapping module, an ethernet signal acquisition module, an FC data frame output module, an FC data frame input module, an ethernet signal extraction module, an MAC address extraction module, and a data distribution module.
The destination MAC address mapping module maintains an address mapping table, which stores the corresponding relationship between the destination MAC address of the ethernet frame and the D _ ID address of the FC frame (i.e., FC _ DID in table 2), as shown in table 2. The table may be configured through an external configuration port.
TABLE 2
Through the table, the D _ ID address of the FC data frame corresponding to the destination MAC address of the current Ethernet data frame can be obtained according to the destination MAC address of the current Ethernet data frame, and the D _ ID address is used for subsequent data interaction.
The ethernet signal obtaining module judges whether there is data to be sent currently by detecting the number of frames counted by each received frame counting module in the ethernet data processing module. When data needs to be sent, the ethernet signal acquisition module controls the FC data frame output module to start framing, and reads data to be sent out from a receiving end cache module of the ethernet data processing module to send the data.
And the FC data frame output module performs data framing according to the D _ ID signal mapped in the destination MAC address mapping module, and assembles the Ethernet data in a data domain of the data frame according to the control signal of the Ethernet signal acquisition module for sending.
The FC data frame input module receives the FC data frame output by the front-end module and generates an indication signal of each byte.
The Ethernet signal extraction module outputs the Ethernet signal in the data domain according to the input data frame.
The MAC address extraction module maintains an address lookup table, which stores the correspondence between MAC addresses and ports, as shown in table 3.
TABLE 3
After the destination MAC address in the ethernet signal output from the ethernet signal extraction module is extracted, the corresponding port number is obtained according to table 3, and the data distribution module is controlled to correctly distribute the ethernet data according to the port number.
The data distribution module distributes the Ethernet data to the correct port according to the control signal generated by the MAC address extraction module.
5. FC data processing module
The FC data processing module is realized by a photoelectric transceiver, a GTX (high-speed serial transceiver), an FC _ IP core and the like. The conversion from FC electric signals to optical signals is realized through the photoelectric transceiver; serdes realizes functions of serial/parallel conversion, 8B/10B coding, clock recovery, CRC (cyclic redundancy check) and the like of an FC (fiber channel) signal based on GTX (GTX) of an FPGA (field programmable gate array); and an FC MAC protocol IP core is adopted to process an FC link primitive signal and a primitive sequence, so that the analysis and the encapsulation of an FC data frame are realized.
In addition, as for the data conversion module, in this embodiment, the structural form thereof is as shown in fig. 4. However, the present invention is not limited to this form as long as the data conversion between the FC port and the ethernet port can be realized.
Claims (6)
1. A data conversion flow control method for FC to Ethernet is characterized by comprising the following steps:
detecting the data flow of the Ethernet port when the FC port and the Ethernet port perform data conversion;
comparing the data traffic of the Ethernet port with a set data traffic upper limit value:
when the data flow of the Ethernet port is judged to be larger than the set upper limit value of the data flow, controlling and triggering FC data back pressure through an FC credit back pressure control module to enable the FC port to stop receiving data; when the data flow of the Ethernet port is judged to be less than or equal to the set data flow upper limit value, the FC port is recovered to a data receiving state;
the FC credit back pressure module is used for monitoring state information corresponding to each cache in the Ethernet cache monitoring module in real time, and controlling a credit value of the FC port according to the state information: if the state information of the Ethernet cache is detected to be high, namely the cache exceeds the set data flow upper limit value, controlling the current FC port not to send the RDY signal any more, and stopping receiving the data by the FC port; if the state information of the Ethernet cache is detected to be low, namely the cache does not exceed the set data flow upper limit value any more, the RDY signal of the current FC port is restored to be normally sent, and data can be normally received.
2. The method according to claim 1, wherein the data traffic of the ethernet port is detected by detecting the number of ethernet frames buffered by the ethernet port.
3. The method of claim 1, wherein the upper limit value of the data traffic is fixed or set through an external configuration interface.
4. The data conversion flow control device for the FC-Ethernet is characterized by comprising a processor, a memory and an interface chip, wherein the processor is used for executing instructions to realize the following method:
detecting the data flow of the Ethernet port when the FC port and the Ethernet port perform data conversion;
comparing the data traffic of the Ethernet port with a set data traffic upper limit value:
when the data flow of the Ethernet port is judged to be larger than the set upper limit value of the data flow, controlling and triggering FC data back pressure through an FC credit back pressure control module to enable the FC port to stop receiving data; when the data flow of the Ethernet port is judged to be less than or equal to the set data flow upper limit value, the FC port is recovered to a data receiving state;
the FC credit back pressure module is used for monitoring state information corresponding to each cache in the Ethernet cache monitoring module in real time, and controlling a credit value of the FC port according to the state information: if the state information of the Ethernet cache is detected to be high, namely the cache exceeds the set data flow upper limit value, controlling the current FC port not to send the RDY signal any more, and stopping receiving the data by the FC port; if the state information of the Ethernet cache is detected to be low, namely the cache does not exceed the set data flow upper limit value any more, the RDY signal of the current FC port is restored to be normally sent, and data can be normally received.
5. The FC-to-Ethernet data conversion flow control device according to claim 4, wherein the data flow of the Ethernet port is detected by detecting the number of Ethernet frames buffered by the Ethernet port.
6. The FC-to-Ethernet data conversion flow control device according to claim 4, wherein the upper limit value of the data flow is fixed or set through an external configuration interface.
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