CN110211920A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN110211920A CN110211920A CN201810167630.6A CN201810167630A CN110211920A CN 110211920 A CN110211920 A CN 110211920A CN 201810167630 A CN201810167630 A CN 201810167630A CN 110211920 A CN110211920 A CN 110211920A
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- Prior art keywords
- dielectric
- low
- layer
- semiconductor devices
- hard mask
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
Abstract
The invention discloses a kind of forming methods of semiconductor devices, comprising: forms metal connecting layer on a semiconductor substrate, and forms cap rock in metal connecting layer；Low k dielectric is formed, low k dielectric is formed in the top of cap rock, forms interlayer dielectric layer on low k dielectric, and form hard mask layer on interlayer dielectric layer；Connecting hole, exposure low k dielectric are formed as mask etching interlayer dielectric layer using hard mask layer；Form the side wall of the inner wall of covering connecting hole；With the low k dielectric and hard mask layer for removing exposure.It avoids low k dielectric from occurring etching the defect excessively generated, ensure that the regular of low k dielectric structure size.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of forming method of semiconductor devices.
Background technique
With the reduction of dimensions of semiconductor devices, the position between different semiconductor devices starts to be stacked from plane to solid
Direction is developed, and is connected between different semiconductor devices by metal wire.When forming metal contact wires, usually will device it
Between form metal connecting hole, to fill metal material.
In the prior art, metal connecting hole usually is formed by exposure mask of hard mask layer, exposes low k dielectric, then uses
Wet-etching technology first removes hard mask layer, then removes low k dielectric.This technique is easy after removing hard mask layer to low
K dielectric layer causes uncontrollable defect damage, reduces the performance of semiconductor devices.
Therefore, it needs a kind of to remove hard mask layer again and will not cause low k dielectric the semiconductor device of defect damage
The forming method of part.
Summary of the invention
The embodiment of the invention discloses a kind of forming methods of semiconductor devices, form side in the connecting hole inner wall of formation
Wall, subsequent recycling atomic layer etching technics removal low k dielectric and hard mask layer, avoid excessive to remaining low k dielectric
It etches and defect occurs.
The invention discloses a kind of forming methods of semiconductor devices, comprising: forms metal connection on a semiconductor substrate
Layer, and cap rock is formed in metal connecting layer；Low k dielectric is formed, low k dielectric is formed in the top of cap rock, in low k dielectric
Interlayer dielectric layer is formed on layer, and forms hard mask layer on interlayer dielectric layer；Using hard mask layer as mask etching inter-level dielectric
Layer is to form connecting hole, exposure low k dielectric；Form the side wall of the inner wall of covering connecting hole；With the low k dielectric for removing exposure
And hard mask layer.
According to an aspect of the present invention, the material for forming hard mask layer includes: one of TiN, TaN, AlN or more
Kind.
According to an aspect of the present invention, the material for forming low k dielectric includes: AlN and/or Al2O3。
According to an aspect of the present invention, the technique for forming low k dielectric is atom layer deposition process.
According to an aspect of the present invention, the technical process for removing exposed low k dielectric and hard mask layer includes: first to remove
Low k dielectric is removed, then removes hard mask layer.
According to an aspect of the present invention, the technique for removing low k dielectric includes atomic layer etching technics.
According to an aspect of the present invention, the processing step of atomic layer etching technics includes: acetylacetone,2,4-pentanedione tin Sn
(acac)2, Al in hydrogen fluoride HF and low k dielectric2O3It is chemically reacted, generates the product Al (acac) easily removed3, no
It is chemically reacted disconnectedly, until the low k dielectric exposed is removed, the temperature of chemical reaction is 150 DEG C~250 DEG C.
According to an aspect of the present invention, the technique for removing hard mask layer is dry etch process.
According to an aspect of the present invention, dry etch process is etched including the first chemical drying method.
According to an aspect of the present invention, the process conditions of the first chemical drying method etching include: gas CF4、N2、O2In
One or more mixing, CF4Gas flow range be 10sccm~50sccm, N2Gas flow range be 30sccm~
100sccm, O2Gas flow range be 5sccm~30sccm, range of reaction temperature be 20 DEG C~70 DEG C, reaction time range
For 100s~300s.
According to an aspect of the present invention, the first chemical drying method etching is selected to hard mask layer and to the etching of interlayer dielectric layer
It selects than being more than or equal to 100.
According to an aspect of the present invention, the first chemical drying method etching is big to hard mask layer and to the etching selection ratio of side wall
In equal to 20.
According to an aspect of the present invention, further includes: after removal hard mask layer, remove cap rock and side wall.
According to an aspect of the present invention, the technical process of exposed low k dielectric and hard mask layer is removed further include: first
Low k dielectric is removed, then removes hard mask layer and cap rock simultaneously.
According to an aspect of the present invention, while to remove the technique of hard mask layer and cap rock include that the second chemical drying method is carved
Erosion.
According to an aspect of the present invention, the process conditions of the second chemical drying method etching include: gas CF4、N2、O2, in Ar
One or more mixing, CF4Gas flow range be 10sccm~50sccm, N2Gas flow range be 30sccm~
100sccm, O2Gas flow range be 5sccm~30sccm, the gas flow range of Ar is 10sccm~100sccm, instead
Answering temperature range is 20 DEG C~70 DEG C, and reaction time range is 100s~300s.
According to an aspect of the present invention, the second chemical drying method etching is selected to hard mask layer and to the etching of interlayer dielectric layer
It selects than being more than or equal to 100.
According to an aspect of the present invention, the second chemical drying method etching is big to hard mask layer and to the etching selection ratio of side wall
In equal to 1.
According to an aspect of the present invention, further includes: while removing low k dielectric and hard mask layer.
According to an aspect of the present invention, while to remove the technique of low k dielectric and hard mask layer include that third chemistry is dry
Method etching technics.
According to an aspect of the present invention, the process conditions of third chemical drying method etching technics include: gas H2And gas
CF4、N2、O2One of or a variety of mixing, H2Gas flow range be 200sccm~1000sccm, CF4Gas flow model
It encloses for 10sccm~50sccm, N2Gas flow range be 30sccm~100sccm, O2Gas flow range be 5sccm~
30sccm, range of reaction temperature are 20 DEG C~70 DEG C, and reaction time range is 100s~300s.
According to an aspect of the present invention, further includes: after removing low k dielectric and hard mask layer, be using temperature range
50 DEG C~90 DEG C deionized water etching products.
According to an aspect of the present invention, further includes: after deionized water etching product, recycle third chemical drying method
Etching removal cap rock.
According to an aspect of the present invention, the material of side wall includes SiN and/or SiON.
Compared with prior art, the technical solution of the embodiment of the present invention has following advantages:
In embodiments of the present invention, the side wall of covering connecting hole inner wall is formed.Subsequent etching work can be guaranteed by forming side wall
Skill will not damage the inner wall of connecting hole, ensure that the regular of connection pore size.Meanwhile removing exposed low k dielectric
And hard mask layer.It is being removed according to different etching technics by low k dielectric removal simultaneously alternatively, first removing low k dielectric
Hard mask layer ensure that remaining low k dielectric is not in overetch bring defect.
Further, the technique for removing low k dielectric includes atomic layer etching technics.The process ratio of atomic layer etching technics
It is easier to control, while also can quickly remove low k dielectric, and low k dielectric overetch will not be ensure that
Low k dielectric structure it is regular.
Detailed description of the invention
Fig. 1-Fig. 5 is the cross section structure schematic diagram for forming connecting hole according to an embodiment of the present invention；
Fig. 6-Fig. 7 is the cross section structure schematic diagram for forming connecting hole according to a further embodiment of the invention；
Fig. 8-Figure 10 is the cross section structure schematic diagram that another embodiment forms connecting hole according to the present invention.
Specific embodiment
As previously mentioned, existing technical solution is when forming connecting hole, the low k dielectric of connecting hole bottom is by overetch
And there is defect.
It has been investigated that the reason of causing the above problem are as follows: after forming connecting hole exposure low k dielectric, carved using wet process
Etching technique etches low k dielectric and hard mask layer, causes low k dielectric overetch, forms defect.
In order to solve this problem, the present invention provides a kind of forming methods of semiconductor devices, etch work using atomic layer
The low k dielectric of skill removal exposure, ensure that the regular of low k dielectric dimensional structure.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, the component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments is not understood that
For limitation of the scope of the invention.
In addition, it should be understood that for ease of description, the size of all parts shown in attached drawing is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the present invention and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as a part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then will not need that it is further discussed in the explanation of subsequent attached drawing.
First embodiment.
Referring to FIG. 1, sequentially forming metal connecting layer 110, cap rock 120, low k dielectric 130, interlayer on substrate 100
Dielectric layer 140 and hard mask layer 150.
Basis of formation of the substrate 100 as Subsequent semiconductor device.The material of substrate 100 can use undoped monocrystalline
Silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc..Specifically, in embodiments of the present invention, the material of substrate 100
For undoped monocrystalline silicon.Substrate 100 can also include other semiconductor component (not shown)s.
Metal connecting layer 110 is used to connect the different components of semiconductor device inside, or reaches connection and be located at different positions
The purpose for setting semiconductor devices realizes specific function.The material of metal connecting layer 110 includes: that copper, tungsten, aluminium etc. are a kind of or more
The combination of kind metal.Specifically, in embodiments of the present invention, the material of metal connecting layer 110 is copper.It is connected using copper as metal
The material of layer 110, can guarantee that the operating resistance of this layer is lower, promote the performance of circuit.
Cap rock 120 is for isolating metal articulamentum 110 and low k dielectric 130.Formed cap rock 120 material include:
SiCN, SiON, SiN etc..Specifically, in embodiments of the present invention, the material of cap rock 120 is SiCN.
In a kind of semiconductor devices, the dielectric layer material between cap rock 120 and interlayer dielectric layer 140 is SiO2, isolation
Excellent effect.But with the continuous reduction of dimensions of semiconductor devices, the distance between each layer is closer in semiconductor devices, and
The thickness of each layer becomes smaller simultaneously.Utilize SiO2After isolation, it is easy to produce excessive parasitic capacitance, increases semiconductor devices
In-fighting influences the performance of semiconductor devices.In the embodiment of the present invention, low k dielectric 130 is formed in cap rock 120 and inter-level dielectric
Between layer 140, it is used as dielectric layer, plays buffer action.Herein, low k refers to that dielectric constant k is less than or equal to 3.9.Low k dielectric
The material of layer 130 includes: AlN, Al2O3, fluorine doped SiO2, carbon dope SiO2, organic matter, one of porous structure material etc. or more
Kind combines, and does not do tool limitation herein.Specifically, in embodiments of the present invention, the material of low k dielectric 130 is Al2O3.Phase
Than other materials, such as fluorine doped SiO2, carbon dope SiO2Deng Al2O3Material as low k dielectric 130 can be avoided ion implanting etc.
Complicated process flow simplifies production technology, and cost is relatively low.
Herein, it should be noted that in another embodiment of the invention, the material of low k dielectric 130 is AlN.And
In yet another embodiment of the present invention, the material of low k dielectric 130 is organic matter polyimides.
The technique for forming low k dielectric 130 includes: spin coating proceeding, chemical vapor deposition process (CVD), atomic layer deposition
Technique (ALD) etc..Specifically, in embodiments of the present invention, the technique for forming low k dielectric 130 is ALD technique.In the present invention
Another embodiment in, formed low k dielectric 130 technique CVD technique.
Interlayer dielectric layer 140 is as the separation layer between different components or between different structure.Interlayer dielectric layer 140
For SiO2。
Hard mask layer 150 is forming corresponding etching pattern structure after patterning, and is exposure mask with hard mask layer 150
The interlayer dielectric layer 140 of lower layer is etched, to form connecting hole.
The material of hard mask layer 150 includes: one of TiN, TaN, AlN or a variety of.Specifically, in the embodiment of the present invention
In, the material of hard mask layer 150 is TiN.
It should be noted that in other embodiments of the invention, the material of hard mask layer 150 can also be TiN and TaN
Two kinds of combination herein and is not particularly limited.
Referring to FIG. 2, being that mask etching interlayer dielectric layer 140 forms connecting hole 170, and is connecting with hard mask layer 150
The inner wall in hole 170 forms side wall 160.
Forming connecting hole 170 is to be formed in the interior thereof metal connecting structure to be subsequent.After forming connecting hole 170, expose
The surface of low k dielectric 130.
The side wall 160 for forming covering 170 inner wall of connecting hole is to protect interlayer in order to subsequent when removing low k dielectric 130
Dielectric layer 140 is not etched, to guarantee the regular of 170 structure size of connecting hole.The material of side wall 160 includes: SiN, SiON, gathers
Close object etc..Specifically, in embodiments of the present invention, the material of side wall 160 is SiN.
Referring to FIG. 3, etching removes the low k dielectric 130 of 170 bottom-exposed of connecting hole.
The metal connecting structure being subsequently formed will be contacted with the metal connecting layer 110 of 100 top of substrate, so will the company of removing
The low k dielectric 130 and cap rock 120 of 170 bottom of hole are connect, and then exposes metal connecting layer 110.Therefore, it is necessary to remove respectively
The low k dielectric 130 and cap rock 120 of 170 bottom of connecting hole.Specifically, in embodiments of the present invention, using first removing connecting hole
The low k dielectric 130 of 170 bottoms, then remove the processing step of cap rock 120.
Specifically, in embodiments of the present invention, the technique for removing low k dielectric 130 is atomic layer etching technics (Atomic
Layer Etching,ALE).Effectively the low k dielectric 130 containing aluminium can be removed using ALE technique, without destroying other
The integrality of structure.
It in embodiments of the present invention, include: acetylacetone,2,4-pentanedione tin Sn using the principle of ALE technique removal low k dielectric 130
(acac)2, hydrogen fluoride HF and Al2O3Reaction, the Al (acac) for generating fluorine-containing, stanniferous product SnF (acac) and easily distilling3.Instead
Answer equation as follows:
Al2O3+6Sn(acac)2+6HF→2Al(acac)3+6SnF(acac)+3H2O is constantly added into reaction chamber
Acetylacetone,2,4-pentanedione tin Sn (acac)2, hydrogen fluoride HF carry out above-mentioned chemical reaction, until the low k for completely removing 170 bottom of connecting hole is situated between
Electric layer 130.
The temperature range reacted in above-mentioned reaction process is 150 DEG C~250 DEG C, and (herein, the range of reaction temperature is
More than or equal to 150 DEG C, it is less than or equal to 250 DEG C, i.e. range includes endpoint value, subsequent range statement and meaning phase herein
Together).When reaction temperature within the above range when, the Al (acac) of generation3More easily distil.Specifically, in the embodiment of the present invention
In, the temperature of reaction process is 200 DEG C.
It should be noted that in other embodiments of the invention, removing reactant used in low k dielectric 130 and may be used also
There was only HF, HF and Al2O3Reaction generates the preferable AlF of stability3, the subsequent mode using cleaning is by AlF3Removal, in turn
Achieve the purpose that remove 170 bottom low k dielectric 130 of connecting hole.Generate AlF3Reaction equation is as follows:
Al2O3+6HF→2AlF3+3H2O
But acetylacetone,2,4-pentanedione tin Sn (acac) is increased in reactant2Afterwards, the fast speed of reaction, and the process reacted
It is easier to control, reaction product is also easier to remove.
And compared with the wet etching in other techniques, the amount being added by control reaction temperature and reactant, ALE work
Skill process and intensity can also avoid overetch convenient for control very well, bring to remaining low k dielectric 130 scarce
Fall into damage.
Referring to FIG. 4, removing hard mask layer after removing low k dielectric 130 and exposing cap rock 120.
It will be evident that in embodiments of the present invention, first removing low k dielectric 130, then the technique for removing hard mask layer is utilized
Step.
In embodiments of the present invention, the technique for removing hard mask layer is dry etch process, and is carved for the first chemical drying method
Erosion.
The process conditions of first chemical drying method etching include: gas CF4、N2、O2One of or a variety of mixing, CF4Gas
Body range of flow is 10sccm~50sccm, N2Gas flow range be 30sccm~100sccm, O2Gas flow range
For 5sccm~30sccm, range of reaction temperature is 20 DEG C~70 DEG C, and reaction time range is 100s~300s.Of the invention
In one embodiment, the process conditions of the first chemical drying method etching are CF4、N2、O2The mixing of gas, CF4Gas flow be
50sccm, N2Gas flow be 80sccm, O2Gas flow be 30sccm, reaction temperature is 50 DEG C, and the reaction time is
150s。
Due to needing to retain interlayer dielectric layer 140 and side wall 160, so the first chemical drying method etching removes hard mask layer
When, there is certain etching selection ratio to interlayer dielectric layer 140 and side wall 160.Herein, etching selection ratio refers to that etching is covered firmly
The speed ratio of film layer and etching interlayer dielectric layer 140 or side wall 160.First chemical drying method etching is situated between to hard mask layer and to interlayer
The etching selection ratio of matter layer 140 is more than or equal to 100, and is more than or equal to 20 to the etching selection ratio of side wall 160.Specifically, at this
In inventive embodiments, the first chemical drying method etching is 100 to hard mask layer and to the etching selection ratio of interlayer dielectric layer 140, right
The etching selection ratio of side wall 160 is 30.
It will be evident that the rate being etched due to side wall 160 is less than the rate that hard mask layer is etched, so removing hard exposure mask
After layer, the top surface of side wall 160 is more slightly higher than the top of interlayer dielectric layer 140, as shown in Figure 4.
Referring to FIG. 5, removing the cap rock 120 of side wall and 170 bottom of connecting hole.
As previously mentioned, the cap rock 120 for removing 170 bottom of connecting hole is for exposing metal articulamentum 110.Of the invention real
It applies in example, the technique of removing side wall and cap rock 120 is also the first chemical drying method etching above.So far, the formation of connecting hole 170,
Space is provided for subsequent filling metal connecting structure.
In conclusion the forming method of semiconductor devices disclosed in first embodiment of the invention, is forming metal connecting hole
During 170, it is initially formed side wall, so that interlayer dielectric layer is protected, it is subsequent first to remove low k dielectric, then hard mask layer is removed,
So that it is guaranteed that low k dielectric structured size, avoids overetch and defect occur, guarantee the function admirable of semiconductor devices.
Second embodiment.
Fig. 6-Fig. 7 is the technical process of second embodiment of the invention.The difference of second embodiment and first embodiment
It is: after removing low k dielectric, side wall, hard mask layer is etched into removal together with the cap rock of connecting hole bottom.Other techniques
Step is consistent with first embodiment.
Referring to FIG. 6, from metal connecting layer 210, cap rock 220, low k dielectric 230, layer is sequentially formed on substrate 200
Between dielectric layer 240 and hard mask layer 250 to the effect of selection and each layer for forming the technical process of side wall 260, material etc.
Consistent with first embodiment, this will not be repeated here.
The low k dielectric 230 of 270 bottom-exposed of etching connection hole, the technical process of exposure cap rock 220, etching technics item
The selection of part is consistent with first embodiment, and therefore not to repeat here.
Referring to FIG. 7, etching removes hard mask layer, side wall and the cap rock 220 positioned at 270 bottom of connecting hole.
In embodiments of the present invention, after removing low k dielectric, the cap rock 220 of 270 bottom of hard mask layer and connecting hole exists
It is removed in same etching technics, and then exposing metal articulamentum 210.It in embodiments of the present invention, further include same in etching process
When remove side wall.
The technique for removing hard mask layer and cap rock 220 simultaneously is etched including the second chemical drying method.Second chemical drying method etching
Process conditions include: gas CF4、N2、O2, one of Ar or a variety of mixing, CF4Gas flow range be 10sccm~
50sccm, N2Gas flow range be 30sccm~100sccm, O2Gas flow range be 5sccm~30sccm, Ar's
Gas flow range be 10sccm~100sccm, range of reaction temperature be 20 DEG C~70 DEG C, reaction time range be 100s~
300s.Specifically, in embodiments of the present invention, the process conditions of the second chemical drying method etching are as follows: gas CF4、N2、O2, Ar
Mixing, CF4Gas flow be 50sccm, N2Gas flow be 100sccm, O2Gas flow be 30sccm, the gas of Ar
Flow is 80sccm, and reaction temperature is 65 DEG C, reaction time 150s.
Likewise, second chemical drying method is etched to hard mask layer and to inter-level dielectric when etching hard mask layer and cap rock 220
Layer 240, side wall have certain etching selection ratio.Second chemical drying method is etched to hard mask layer and to interlayer dielectric layer 240
Etching selection ratio is more than or equal to 100, and is more than or equal to 1 to hard mask layer and to the etching selection ratio of side wall.Specifically, in this hair
In bright embodiment, the second chemical drying method etching is 100 to hard mask layer and to the etching selection ratio of interlayer dielectric layer 240, and right
Hard mask layer and be 2 to the etching selection ratio of side wall.
In conclusion the forming method of semiconductor devices disclosed in second embodiment of the invention, after forming side wall, etching
Then low k dielectric removes hard mask layer and cap rock, when can guarantee to remove low k dielectric, will not destroy low k dielectric
Remaining structure avoids the generation of defect, guarantees the performance of semiconductor devices.
3rd embodiment.
3rd embodiment and previous embodiment the difference is that: 3rd embodiment removes the low of connecting hole bottom simultaneously
K dielectric layer and hard mask layer, then in removal cap rock.Other technical process are consistent with first embodiment.
Referring to FIG. 8, forming the side wall 360 of covering 370 inner wall of connecting hole after forming connecting hole 370.
From sequentially forming metal connecting layer 310, cap rock 320, low k dielectric 330, interlayer dielectric layer 340 on substrate 300
The selection of effect and material with hard mask layer 350 to the processing step, technique for forming connecting hole 370 is and first embodiment
Unanimously, details are not described herein.
Specifically, in embodiments of the present invention, the material for forming side wall 360 is organic matter.
Referring to FIG. 9, removing the low k dielectric 330 and hard mask layer for being located at 370 bottom of connecting hole simultaneously.
Removing low k dielectric 330 and the technique of hard mask layer simultaneously includes third chemical drying method etching technics.Third chemistry
The process conditions of dry etch process include: gas H2With gas CF4、N2、O2One of or a variety of mixing, H2Gas flow
Range is 200sccm~1000sccm, CF4Gas flow range be 10sccm~50sccm, N2Gas flow range be
30sccm~100sccm, O2Gas flow range be 5sccm~30sccm, range of reaction temperature be 20 DEG C~70 DEG C, reaction
Time range is 100s~300s.Specifically, in embodiments of the present invention, third chemical drying method etch technological condition are as follows: gas
H2With gas CF4、N2、O2In mixing, H2Gas flow be 800sccm, CF4Gas flow be 50sccm, N2Gas
Flow is 60sccm, O2Gas flow be 15sccm, reaction temperature be 70 DEG C, reaction time 200s.
After removing low k dielectric 330 and hard mask layer simultaneously, remaining 330 structural integrity of low k dielectric.
Since ablation removes hard mask layer and low k dielectric 330 in the same time, etch product is the compound containing Ti, Al, therefore
Need to clean removing.So in embodiments of the present invention, after removing hard mask layer, further includes: utilize deionized water etching
Product.The temperature range of deionized water is 50 DEG C~90 DEG C.Specifically, in embodiments of the present invention, the temperature of deionized water is
90℃。
Referring to FIG. 10, with after deionized water etching product, further includes: gone again using third chemical drying method etching
Except the cap rock 320 of 370 bottom of connecting hole.
The process conditions of third chemical drying method etching with it is consistent above, details are not described herein.
In conclusion the forming method of semiconductor devices disclosed in third embodiment of the invention is gone simultaneously after forming side wall
Except hard mask layer and low k dielectric, the stabilization of remaining low k dielectric structure is protected, structured size ensure that semiconductor devices
The stabilization of performance.
So far, the present invention is described in detail.In order to avoid covering design of the invention, it is public that this field institute is not described
The some details known.Those skilled in the art as described above, completely it can be appreciated how implementing technology disclosed herein
Scheme.
Although some specific embodiments of the invention are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to being illustrated, the range being not intended to be limiting of the invention.The skill of this field
Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above embodiments.This hair
Bright range is defined by the following claims.
Claims (24)
1. a kind of forming method of semiconductor devices characterized by comprising
Metal connecting layer is formed on a semiconductor substrate, and forms cap rock in the metal connecting layer；
Low k dielectric is formed, the low k dielectric is formed in the top of the cap rock, forms interlayer on the low k dielectric
Dielectric layer, and hard mask layer is formed on the interlayer dielectric layer；
Connecting hole, the exposure low k dielectric are formed as interlayer dielectric layer described in mask etching using the hard mask layer；
Form the side wall for covering the inner wall of the connecting hole；With
Remove the low k dielectric and the hard mask layer of exposure.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that form the material of the hard mask layer
Material includes: one of TiN, TaN, AlN or a variety of.
3. the forming method of semiconductor devices according to claim 2, which is characterized in that form the low k dielectric
Material includes: AlN and/or Al2O3。
4. the forming method of semiconductor devices according to claim 3, which is characterized in that form the low k dielectric
Technique is atom layer deposition process.
5. the forming method of semiconductor devices according to claim 3, which is characterized in that remove the exposed low k and be situated between
Electric layer and the technical process of the hard mask layer include: first to remove the low k dielectric, then remove the hard mask layer.
6. the forming method of semiconductor devices according to claim 5, which is characterized in that remove the low k dielectric
Technique includes atomic layer etching technics.
7. the forming method of semiconductor devices according to claim 6, which is characterized in that the atomic layer etching technics
Processing step includes: acetylacetone,2,4-pentanedione tin Sn (acac)2, Al in hydrogen fluoride HF and the low k dielectric2O3It is chemically reacted,
Generate the product Al (acac) easily removed3, the chemical reaction is constantly carried out, until the low k dielectric exposed is removed
It goes, the temperature of the chemical reaction is 150 DEG C~250 DEG C.
8. the forming method of semiconductor devices according to claim 5, which is characterized in that remove the work of the hard mask layer
Skill is dry etch process.
9. the forming method of semiconductor devices according to claim 8, which is characterized in that the dry etch process includes
First chemical drying method etching.
10. the forming method of semiconductor devices according to claim 9, which is characterized in that first chemical drying method is carved
The process conditions of erosion include: CF4、N2、O2The mixing of three kinds of gas, CF4Gas flow range be 10sccm~50sccm, N2's
Gas flow range is 30sccm~100sccm, O2Gas flow range be 5sccm~30sccm, range of reaction temperature is
20 DEG C~70 DEG C, reaction time range is 100s~300s.
11. the forming method of semiconductor devices according to claim 10, which is characterized in that first chemical drying method is carved
It loses to the hard mask layer and 100 is more than or equal to the etching selection ratio of the interlayer dielectric layer.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that first chemical drying method is carved
It loses to the hard mask layer and 20 is more than or equal to the etching selection ratio of the side wall.
13. the forming method of semiconductor devices according to claim 5, which is characterized in that further include: removal is described to be covered firmly
After film layer, the cap rock and the side wall are removed.
14. the forming method of semiconductor devices according to claim 3, which is characterized in that remove the exposed low k and be situated between
The technical process of electric layer and the hard mask layer further include: first remove the low k dielectric, then remove the hard mask layer simultaneously
With the cap rock.
15. the forming method of semiconductor devices according to claim 14, which is characterized in that while removing the hard exposure mask
The technique of layer and the cap rock is etched including the second chemical drying method.
16. the forming method of semiconductor devices according to claim 15, which is characterized in that second chemical drying method is carved
The process conditions of erosion include: gas CF4、N2、O2, one of Ar or a variety of mixing, CF4Gas flow range be 10sccm
~50sccm, N2Gas flow range be 30sccm~100sccm, O2Gas flow range be 5sccm~30sccm, Ar
Gas flow range be 10sccm~100sccm, range of reaction temperature be 20 DEG C~70 DEG C, reaction time range be 100s~
300s。
17. the forming method of semiconductor devices according to claim 16, which is characterized in that second chemical drying method is carved
It loses to the hard mask layer and 100 is more than or equal to the etching selection ratio of the interlayer dielectric layer.
18. the forming method of semiconductor devices according to claim 16, which is characterized in that second chemical drying method is carved
It loses to the hard mask layer and 1 is more than or equal to the etching selection ratio of the side wall.
19. the forming method of semiconductor devices according to claim 3, which is characterized in that further include: while described in removing
Low k dielectric and the hard mask layer.
20. the forming method of semiconductor devices according to claim 19, which is characterized in that while removing the low k and being situated between
Electric layer and the technique of the hard mask layer include third chemical drying method etching technics.
21. the forming method of semiconductor devices according to claim 20, which is characterized in that the third chemical drying method is carved
The process conditions of etching technique include: gas H2With gas CF4、N2、O2One of or a variety of mixing, H2Gas flow range be
200sccm~1000sccm, CF4Gas flow range be 10sccm~50sccm, N2Gas flow range be 30sccm~
100sccm, O2Gas flow range be 5sccm~30sccm, range of reaction temperature be 20 DEG C~70 DEG C, reaction time range
For 100s~300s.
22. the forming method of semiconductor devices according to claim 21, which is characterized in that further include: remove the low k
It is 50 DEG C~90 DEG C deionized water etching products using temperature range after dielectric layer and the hard mask layer.
23. the forming method of semiconductor devices according to claim 22, which is characterized in that further include: the deionization
After water cleans the etch product, the third chemical drying method etching is recycled to remove the cap rock.
24. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of the side wall includes
SiN and/or SiON.
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