CN110211536B

CN110211536B - Display panel and driving method thereof

Info

Publication number: CN110211536B
Application number: CN201910582500.3A
Authority: CN
Inventors: 吴桐; 钱栋
Original assignee: Hefei Shiya Technology Co ltd
Current assignee: Vision Technology Co ltd
Priority date: 2019-06-29
Filing date: 2019-06-29
Publication date: 2021-10-15
Anticipated expiration: 2039-06-29
Also published as: CN110211536A

Abstract

The embodiment of the invention discloses a display panel and a driving method of the display panel. The display panel includes: n scanning lines; n scanning drive circuits arranged corresponding to the N scanning lines; the device comprises a resolution control module, a first resolution control signal line and a first potential signal line; the resolution control module comprises M input ends, M output ends, a control signal end and a first potential signal input end; the control signal end is electrically connected with the first resolution control signal line, the first potential signal input end is electrically connected with the first potential signal line, the M input ends are respectively and electrically connected with the lower-level shift signal output ends of the corresponding scanning driving circuits, and the M output ends are respectively and electrically connected with the upper-level shift signal input ends of the corresponding scanning driving circuits. Compared with the prior art, the embodiment of the invention realizes the switching of the display resolution, thereby enriching the scanning mode of the scanning driving circuit.

Description

Display panel and driving method thereof

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a driving method of the display panel.

Background

With the continuous development of display technology and the continuous increase of requirements of people for display devices, Virtual Reality (VR) display devices are coming into the field of vision of people more and more widely.

In order to achieve a richer display effect, it is necessary that the display device is compatible with a plurality of display functions. However, the scanning mode of the existing display device is single, which results in a single display function of the display device, and the display device cannot be compatible with more and more display modes.

Disclosure of Invention

Embodiments of the present invention provide a display panel and a driving method of the display panel to enrich display modes of the display panel.

In a first aspect, an embodiment of the present invention provides a display panel. The display panel includes: n scanning lines;

the scanning driving circuits are connected in a cascade mode and comprise an upper-level shifting signal input end, a lower-level shifting signal output end and a scanning signal output end, and the scanning signal output end is electrically connected with the scanning lines;

the device comprises a resolution control module, a first resolution control signal line and a first potential signal line;

the resolution control module comprises M input ends, M output ends, a control signal end and a first potential signal input end; the control signal end is electrically connected with the first resolution control signal line, the first potential signal input end is electrically connected with the first potential signal line, the M input ends are respectively and electrically connected with the lower-level shift signal output ends of the corresponding scanning driving circuits, and the M output ends are respectively and electrically connected with the upper-level shift signal input ends of the corresponding scanning driving circuits; the resolution control module is used for conducting the corresponding input end and output end or conducting the first potential signal input end and output end according to the signal of the first resolution control signal line; wherein N is more than or equal to M, and M is a positive integer.

In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, where the driving method of the display panel is applicable to the display panel provided in any embodiment of the present invention. The driving method of the display panel comprises the following steps:

sending a resolution control signal to the first resolution control signal line, and sending a first potential signal to the first potential signal line;

controlling the resolution control module to conduct corresponding input ends and output ends according to the signals of the first resolution control signal line, driving the corresponding scanning driving circuits to shift sequentially to output scanning signals, and displaying the first display resolution on the display panel;

or, according to the signal of the first resolution control signal line, the resolution control module is controlled to conduct the first potential signal input end and the first potential signal output end, the corresponding scanning driving circuit is driven to stop working, and the display panel displays a second display resolution.

In the embodiment of the invention, the resolution control module is arranged to control the upper shift signal input end of the partial scanning drive circuit to be electrically connected with the lower shift signal output end of the upper scanning drive circuit, or control the upper shift signal input end of the partial scanning drive circuit to be electrically connected with the first potential signal line, so that the function of driving all or part of the scanning drive circuit to output scanning signals is realized. Therefore, the embodiment of the invention can be compatible with various display resolutions, thereby enriching the scanning modes of the scanning driving circuit. In addition, the embodiment of the invention can flexibly set the position of the scanning driving circuit electrically connected with the resolution control module according to the requirement, which is equivalent to adding a tap function in the display panel. In addition, in the embodiment of the present invention, when the first potential signal input terminal and the upper shift signal input terminal of the scan driving circuit are turned on, it is equivalent to that a fixed potential signal is input to the scan driving circuit, and the internal device of the scan driving circuit does not operate. Therefore, when the display resolution is reduced, the embodiment of the invention not only can reduce the power consumption of the pixel, but also can reduce the power consumption of the scanning driving circuit.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a cascade connection of scan driving circuits according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another cascade connection of scan driving circuits according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a cascade connection of another scan driving circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a driving timing sequence of a scan driving circuit according to an embodiment of the invention;

FIG. 9 is a schematic diagram of a driving timing sequence of another scan driving circuit according to an embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a driving timing sequence of another scan driving circuit according to an embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating a driving timing sequence of another scan driving circuit according to an embodiment of the present invention;

FIG. 12 is a schematic diagram illustrating a driving timing sequence of another scan driving circuit according to an embodiment of the present invention;

FIG. 13 is a schematic diagram illustrating a driving timing sequence of another scan driving circuit according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention;

FIG. 15 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention;

fig. 17 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to fig. 1, the display panel includes: the scanning circuit comprises N scanning lines 10, N scanning driving circuits 20 arranged corresponding to the N scanning lines 10, a resolution control module 30, a first resolution control signal line 40 and a first potential signal line 50.

The N scan driving circuits 20 are connected in cascade, each scan driving circuit 20 includes an upper shift signal input terminal, a lower shift signal output terminal, and a scan signal output terminal, and the scan signal output terminals are electrically connected to the scan lines 10.

The resolution control module 30 includes M input terminals, M output terminals (4 input terminals and 4 output terminals are exemplarily shown in fig. 1), a control signal terminal, and a first potential signal input terminal; the control signal terminal is electrically connected to the first resolution control signal line 40, the first potential signal input terminal is electrically connected to the first potential signal line 50, the M input terminals are electrically connected to the lower stage shift signal output terminals of the corresponding scan driving circuits 20, and the M output terminals are electrically connected to the upper stage shift signal input terminals of the corresponding scan driving circuits 20; the resolution control module 30 is configured to switch on corresponding input and output terminals or switch on a first potential signal input and output terminal according to a signal of the first resolution control signal line 40; wherein N is more than or equal to M, and M is a positive integer.

The M input terminals and the M output terminals of the resolution control module 30 are correspondingly arranged. When the corresponding input and output terminals of the first resolution control signal line 40 control the resolution control module 30 to be turned on, the lower shift signal output terminal of the previous scan driving circuit 20 and the upper shift signal input terminal of the next scan driving circuit 20 are turned on, and the scan driving circuit 20 electrically connected to the resolution control module 30 can normally output the scan signal. When the first potential signal input terminal and the output terminal of the first resolution control signal line 40 control the first potential signal input terminal and the output terminal of the resolution control module 30 to be conducted, the first potential signal input terminal and the upper shift signal input terminal of the scan driving circuit 20 are conducted, and the scan driving circuit 20 electrically connected to the resolution control module 30 outputs a signal of a fixed potential by receiving the fixed potential of the first potential signal line 50, that is, the scan driving circuit 20 stops outputting the scan signal. When the scanning driving circuit 20 outputs a signal of a fixed potential, the corresponding scanning line drives the electrically connected pixels not to emit light, thereby realizing displaying pictures with different resolutions.

Illustratively, the driving method of the display panel includes: sending a resolution control signal to the first resolution control signal line 40, and sending a first potential signal to the first potential signal line 50;

according to the signal of the first resolution control signal line 40, the resolution control module 30 is controlled to conduct the corresponding input end and output end, and drives the corresponding scan driving circuit 20 to sequentially shift and output the scan signal, so that the display panel displays the first display resolution;

or, according to the signal of the first resolution control signal line 40, the resolution control module 30 is controlled to turn on the first potential signal input end and the first potential signal output end, so as to drive the corresponding scan driving circuit 20 to stop working, and the display panel displays the second display resolution. Wherein the second display resolution is lower than the first display resolution.

In the embodiment of the present invention, by providing the resolution control module 30, the upper shift signal input terminal of the partial scan driving circuit 20 is controlled to be electrically connected to the lower shift signal output terminal of the upper scan driving circuit 20, or the upper shift signal input terminal of the partial scan driving circuit 20 is controlled to be electrically connected to the first potential signal line 50, so that the function of driving all or part of the scan driving circuit 20 to output the scan signal is realized. Therefore, the embodiment of the invention can be compatible with various display resolutions. In addition, the embodiment of the present invention can flexibly set the position of the scan driving circuit 20 electrically connected to the resolution control module 30 according to the requirement, which is equivalent to adding a tap function in the display panel. In addition, in the embodiment of the present invention, when the first potential signal input terminal and the upper shift signal input terminal of the scan driving circuit 20 are turned on, it is equivalent to that a fixed potential signal is input to the scan driving circuit 20, and the internal devices of the scan driving circuit 20 do not operate. Therefore, when the display resolution is reduced, the embodiment of the invention can reduce the power consumption of the pixel and also reduce the power consumption of the scan driving circuit 20.

On the basis of the above embodiments, alternatively, the scanning signal output terminal of the scanning drive circuit 20 is electrically connected to the pixel through the scanning line 10. Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 2, the pixel circuit optionally includes a data signal input terminal VDATA, a first scan signal input terminal WS _1, a second scan signal input terminal WS _2, a first reference signal terminal NCP, a second reference signal terminal VFB, a first power supply terminal ELVDD, a second power supply terminal ELVSS, a light emission control signal terminal EMIT, a driving transistor MD, an input block MS1, a reset block MS2, a light emission control block MS3, and a capacitor C1. The control terminal of the input module MS1 is electrically connected to the first scan signal input terminal WS _1, the first terminal of the input module MS1 is electrically connected to the data signal input terminal VDATA, and the second terminal of the input module MS1 is electrically connected to the control terminal of the driving transistor MD. A first terminal of the capacitor C1 is electrically connected to the first reference signal terminal NCP, and a second terminal of the capacitor C1 is electrically connected to the control terminal of the driving transistor MD. The first terminal of the driving transistor MD is electrically connected to the first power source terminal ELVDD. A control terminal of the reset module MS2 is electrically connected to the second scan signal input terminal WS _2, a first terminal of the reset module MS2 is electrically connected to the second reference signal terminal VFB, and a second terminal of the reset module MS2 is electrically connected to the second terminal of the driving transistor MD. The control terminal of the light emitting control module MS3 is electrically connected to the light emitting control signal terminal EMIT, the first terminal of the light emitting control module MS3 is electrically connected to the second terminal of the driving transistor MD, and the second terminal of the light emitting control module MS3 is electrically connected to the anode of the light emitting device OLED. The cathode of the light emitting device OLED is electrically connected to the second power source terminal ELVSS.

Illustratively, the scan driving circuit is a light emission control circuit, and the scan signal output terminal is electrically connected to a light emission control terminal EMIT of the pixel circuit. In a typical timing signal output mode, in a first high level pulse stage of an upper stage shift signal, a pixel circuit is in a reset stage, and each node and an anode of a light emitting device in the pixel circuit are reset. And in a second high-level pulse stage of the superior shift signal, the scanning signal output end outputs a high level, the pixel circuit is disconnected from the light emitting device OLED, the light emitting device OLED does not emit light, and the pixel circuit is in a data writing stage and writes the data signal into the driving transistor. Therefore, in a typical timing signal output mode, in one frame, only in the second high level pulse phase of the upper stage shift signal, the scan signal output terminal outputs a high level, the pixel circuit is disconnected from the light emitting device OLED, and the light emitting device OLED does not emit light.

Fig. 3 is a schematic structural diagram of a cascade connection of scan driving circuits according to an embodiment of the present invention. Referring to fig. 3, on the basis of the above embodiments, the resolution control module 30 optionally includes: the M first data selecting modules 31, the M first data selecting modules 31 are respectively and correspondingly connected between the M input ends and the M output ends of the resolution control module 30.

The first data selecting module 31 may be, for example, a data selector, a control terminal of the first data selecting module 31 is electrically connected to the control signal terminal CTRL of the resolution control module 30, a first input terminal of the first data selecting module 31 is electrically connected to the input terminal of the resolution control module 30, a second input terminal of the first data selecting module 31 is electrically connected to the first potential signal input terminal of the resolution control module 30, and an output terminal of the first data selecting module 31 is electrically connected to the output terminal of the resolution control module 30.

In the following, the scanning drive circuit 20 is an emission control circuit, taking M-5 shown in fig. 3 as an example. A first input end of the first-stage first data selection module 31 is electrically connected with the start signal line STV, and a second input end of the first-stage first data selection module 31 is electrically connected with the first potential signal input end VGH; a first input terminal of the second-stage first data selection module 31 is electrically connected to an input terminal of the resolution control module 30 (i.e., a lower shift signal output terminal of the first-stage scan driving circuit 20), and a second input terminal of the second-stage first data selection module 31 is electrically connected to the first potential signal input terminal VGH; a first input terminal of the third-stage first data selection block 31 is electrically connected to an input terminal of the resolution control block 30 (i.e., a lower-stage shift signal output terminal of the 2 nd-stage scan driving circuit 20), and a second input terminal of the third-stage first data selection block 31 is electrically connected to the start signal line STV; a first input terminal of the fourth-stage first data selection module 31 is electrically connected to an input terminal of the resolution control module 30 (i.e., a lower shift signal output terminal of the N-2 th-stage scan driving circuit 20), and a second input terminal of the fourth-stage first data selection module 31 is electrically connected to the first potential signal input terminal VGH; a first input terminal of the fifth-stage first data selection module 31 is electrically connected to an input terminal of the resolution control module 30 (i.e., a lower shift signal output terminal of the N-1 th-stage scan driving circuit 20), and a second input terminal of the fifth-stage first data selection module 31 is electrically connected to the first potential signal input terminal VGH.

When the control signal terminal CTRL is at a low level (0), the upper shift signal input terminal of the first-stage scan driving circuit 20 inputs a start signal, the upper shift signal input terminals of the second-stage to nth-stage scan driving circuits 20 all input the upper shift signal, the scan driving circuit 20 outputs a scan signal step by step, and each row of pixels of the display panel is displayed with a first display resolution.

When the control signal terminal CTRL is at a high level (1), the first potential signal is input to the upper shift signal input terminals of the first, second, N-1, and N-th scan driving circuits 20, the start signal is input to the upper shift signal input terminal of the third scan driving circuit 20, the upper shift signal input terminals of the fourth to N-th scan driving circuits 20 all input the lower shift signal of the upper stage, the fourth to N-th scan driving circuits 20 output the scan signal step by step, the first, second, N-1, and N-th scan driving circuits 20 output the high level, the pixels of the first, second, N-1, and N-th rows do not emit light, and the pixels of the fourth to N-th rows emit light and are displayed with the second display resolution.

The resolution control module 30 according to the embodiment of the present invention includes M first data selection modules 31, so that the switching between two display resolutions is realized.

Fig. 4 is a schematic structural diagram of another cascade connection of scan driving circuits according to an embodiment of the present invention. Referring to fig. 4, on the basis of the above embodiments, optionally, the resolution control module 30 further includes: and the second data selection module 32, wherein the second data selection module 32 is connected between the P-th stage input end of the resolution control module 30 and the P-th stage first data selection module 31.

The control signal terminals of the resolution control module 30 include a first control signal terminal CTRL1 and a second control signal terminal CTRL 2; the control terminal of the first data selection module 31 at the front P-1 level is electrically connected to the first control signal terminal CTRL 1; the control terminal of the first data selection module 31 of the P-th to (Q-1) th stage is electrically connected with the second control signal terminal CTRL 2; the control terminal of the second data selection module 32 is electrically connected to the first control signal terminal CTRL 1. Wherein, P is more than 1 and more than Q and less than or equal to M, and P and Q are positive integers.

Illustratively, fig. 4 shows that the overall resolution of the display panel is 1200 × 1920RGB, specifically, N is 1200, M is 480, P is 61, and Q is 89. The control terminal of the level 1 first data selection module 31 is electrically connected to the first control signal terminal CTRL1, the first input terminal is electrically connected to the start signal line, and the second input terminal is electrically connected to the first potential signal input terminal. The control terminal of the 2 nd to 60 th stage first data selection module 31 is electrically connected to the first control signal terminal CTRL1, the first input terminal is electrically connected to the lower shift signal output terminal of the previous stage scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal. The control terminal of the 61 st stage first data selecting module 31 is electrically connected to the second control signal terminal CTRL2, and the second input terminal is electrically connected to the first potential signal input terminal. The control terminal of the 62 th to 88 th stage first data selection module 31 is electrically connected to the second control signal terminal CTRL2, the first input terminal is electrically connected to the lower shift signal output terminal of the previous stage scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal. The control terminal of the second data selection module 32 is electrically connected to the first control signal terminal CTRL1, the first input terminal is electrically connected to the lower shift signal output terminal of the 60 th scan driving circuit 20, the second input terminal is electrically connected to the first potential signal input terminal, and the output terminal is electrically connected to the first input terminal of the 61 st first data selection module 31.

In the embodiment of the present invention, the resolution control module 30 includes the first data selection module 31 and the second data selection module 32, and the control signal terminal of the resolution control module 30 includes the first control signal terminal CTRL1 and the second control signal terminal CTRL2, so that the switching of three display resolutions is realized.

With continued reference to FIG. 4, based on the above embodiments, optionally, the control terminal of the (M-Q +1) th-to (M-P) th-stage first data selecting module 31 is electrically connected to the second control signal terminal CTRL 2; the control terminal of the (M-P +1) -M-th-level first data selection module 31 is electrically connected to the first control signal terminal CTRL 1. The display panel is arranged in such a way that the display picture is in the middle area of the whole display panel when the display panel displays with low display resolution.

With continued reference to fig. 4, on the basis of the foregoing embodiments, optionally, the resolution control module 30 further includes a third data selection module 33, and the third data selection module 33 is connected between the input end of the Q-th stage of the resolution control module 30 and the first data selection module 31 of the Q-th stage.

The control signal terminal of the resolution control module 30 further comprises a third control signal terminal CTRL 3; the control terminal of the Q-th to X-th stage first data selection module 31 is electrically connected to the third control signal terminal CTRL 3; the control terminal of the third data selection module 33 is electrically connected to the second control signal terminal CTRL 2. Wherein, Q is more than X and less than or equal to M, and X is a positive integer.

In fig. 4, X is 216, for example. The control terminal of the 89 th-stage first data selecting module 31 is electrically connected to the third control signal terminal CTRL3, and the second input terminal is electrically connected to the first potential signal input terminal. The control terminal of the 90 th to 216 th-stage first data selection module 31 is electrically connected to the third control signal terminal CTRL3, the first input terminal is electrically connected to the lower shift signal output terminal of the previous-stage scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal VGH. The control terminal of the third data selecting module 33 is electrically connected to the second control signal terminal CTRL2, the first input terminal is electrically connected to the lower shift signal output terminal of the 88 th scan driving circuit 20, the second input terminal is electrically connected to the first potential signal input terminal, and the output terminal is electrically connected to the first input terminal of the 89 th first data selecting module 31.

In the embodiment of the present invention, the resolution control module 30 includes a first data selection module 31, a second data selection module 32, and a third data selection module 33, and the control signal terminals of the resolution control module 30 include a first control signal terminal CTRL1, a second control signal terminal CTRL2, and a third control signal terminal CTRL3, so as to implement switching of four display resolutions.

It should be noted that, in the above embodiment, the resolution control module 30 includes three data selection modules exemplarily shown, and the control signal terminal of the resolution control module 30 includes three control signal terminals, so that the switching of the display resolution of four display modules can be realized, which is not limited to the present invention. In other embodiments, a greater number of data selection modules and control signal terminals may be provided as needed to implement switching of more display resolutions.

With continued reference to fig. 4, based on the above embodiments, optionally, the resolution control module 30 further includes a fourth data selection module 34, and the control signal terminal of the resolution control module 30 further includes a fourth control signal terminal CTRL 4. The control terminal of the 217 th-stage first data selecting module 31 is electrically connected to the fourth control signal terminal CTRL4, and the second input terminal is electrically connected to the first potential signal input terminal. The control terminal of the 218-241 th stage first data selection module 31 is electrically connected to the fourth control signal terminal CTRL4, the first input terminal is electrically connected to the lower shift signal output terminal of the previous stage scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal VGH. The control terminal of the fourth data selecting module 34 is electrically connected to the third control signal terminal CTRL3, the first input terminal is electrically connected to the lower shift signal output terminal of the 216 th scan driving circuit 20, the second input terminal is electrically connected to the first potential signal input terminal, and the output terminal is electrically connected to the first input terminal of the 217 th first data selecting module 31.

In the embodiment of the present invention, the resolution control module 30 includes a first data selection module 31, a second data selection module 32, a third data selection module 33, and a fourth data selection module 34, and the control signal terminals of the resolution control module 30 include a first control signal terminal CTRL1, a second control signal terminal CTRL2, a third control signal terminal CTRL3, and a fourth control signal terminal CTRL4, so that five kinds of display resolutions can be switched.

With reference to fig. 4, based on the above embodiments, optionally, the control terminal of the first data selecting module 31 of the 961-984 stages is electrically connected to the fourth control signal terminal CTRL4, the first input terminal is electrically connected to the lower shift signal output terminal of the previous stage scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal VGH. The control terminal of the 985-1112 level first data selecting module 31 is electrically connected to the third control signal terminal CTRL3, the first input terminal is electrically connected to the next shift signal output terminal of the previous level scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal VGH. The control terminal of the first data selection module 31 of the 1113 th to 1140 th stages is electrically connected to the second control signal terminal CTRL2, the first input terminal is electrically connected to the lower shift signal output terminal of the previous stage scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal VGH. The control terminal of the first data selecting module 31 of the 1141-1200 th stages is electrically connected to the first control signal terminal CTRL1, the first input terminal is electrically connected to the next shift signal output terminal of the previous stage scan driving circuit 20, and the second input terminal is electrically connected to the first potential signal input terminal VGH.

The embodiment of the invention realizes the switching of five display resolutions, including a high display resolution of integral display and a low display resolution of four parts of display, and the images displayed by the four parts of low resolution are all positioned in the middle area of the display panel.

The following describes five driving methods for display resolution achieved by the embodiment of the present invention.

For example, the driving method of the display panel is that when the first control signal terminal CTRL1 is at a low level (0), the second control signal terminal CTRL2 is at a low level (0), the third control signal terminal CTRL3 is at a low level (0), and the fourth control signal terminal CTRL4 is at a low level (0), the scanning driving circuits 20 of each stage output scanning signals step by step, and each row of pixels of the display panel are displayed with the first display resolution (1200 × 1920 RGB).

When the first control signal terminal CTRL1 is at a high level (1), the second control signal terminal CTRL2 is at a low level (0), the third control signal terminal CTRL3 is at a low level (0), and the fourth control signal terminal CTRL4 is at a low level (0), the 61 st to 1140 th stage scan driving circuits 20 output scan signals step by step, and pixels on the 61 st to 1140 th rows emit light to display at a second display resolution (1080 × 1920 RGB).

When the first control signal terminal CTRL1 is at a high level (1), the second control signal terminal CTRL2 is at a high level (1), the third control signal terminal CTRL3 is at a low level (0), and the fourth control signal terminal CTRL4 is at a low level (0), the 89 th to 1113 th scanning driving circuits 20 output scanning signals step by step, and pixels in the 89 th to 1113 th rows emit light to display at a third display resolution (1024 × 1920 RGB).

When the first control signal terminal CTRL1 is at a high level (1), the second control signal terminal CTRL2 is at a high level (1), the third control signal terminal CTRL3 is at a high level (1), and the fourth control signal terminal CTRL4 is at a low level (0), the 217-986 th stage scan driving circuit 20 outputs scan signals step by step, and the 217-986 th row pixels emit light and display the scan signals with a fourth display resolution (768 × 1920 RGB).

When the first control signal terminal CTRL1 is at a high level (1), the second control signal terminal CTRL2 is at a high level (1), the third control signal terminal CTRL3 is at a high level (1), and the fourth control signal terminal CTRL4 is at a high level (1), the 241-961 th stage scan driving circuit 20 outputs scan signals step by step, and the 241-961 th row pixels emit light and are displayed with a fifth display resolution (720 × 1920 RGB).

Therefore, the embodiment of the invention can realize the switching of five display resolutions. In the embodiment of the present invention, when the first potential signal input terminal and the upper shift signal input terminal of the scan driving circuit 20 are turned on, it is equivalent to that a fixed potential signal is input to the scan driving circuit 20, and the internal device of the scan driving circuit 20 does not operate. Therefore, when the display resolution is reduced, the embodiment of the invention can reduce the power consumption of the pixel and also reduce the power consumption of the scan driving circuit 20.

It should be noted that, the embodiment of the present invention exemplarily illustrates that the display panel can realize switching of five resolutions, and is not limited to the present invention, and in other embodiments, the position of the scan driving circuit 20 electrically connected to the resolution control module 30 can be flexibly set as needed, which is equivalent to adding a tap function in the display panel, so as to realize more display modes.

Fig. 5 is a schematic structural diagram of a cascade connection of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 5, on the basis of the foregoing embodiments, optionally, the display panel further includes data control signal lines (three data control signal lines, i.e., a data control signal line S <0>, a data control signal line S <1> and a data control signal line S <2>, are exemplarily shown in fig. 5) and a decoder 60, an input terminal of the decoder 60 is electrically connected to the data control signal lines, and an output terminal of the decoder 60 is electrically connected to the control signal terminals of the resolution control module (fig. 5 exemplarily shows that the control signal terminals include a first control signal terminal CTRL1, a second control signal terminal CTRL2, a third control signal terminal CTRL3 and a fourth control signal terminal CTRL 4).

The decoder 60 according to the embodiment of the present invention can implement a function of outputting more signals with fewer control lines, which is beneficial to implementing more control functions. Illustratively, the data transmission function of 4 control signal terminals can be realized by using 3-bit control signals, and five display resolutions are realized. Specifically, the display resolutions corresponding to the signals on the data control signal line S <0>, the data control signal line S <1>, and the data control signal line S <2> are shown in table 1.

TABLE 1

Resolution ratio	S<2>	S<1>	S<0>
				1200x1920RGB	0	0	0
1080x1920RGB	1	0	0
				1024x1920RGB	1	0	1
768x1920RGB	1	1	0
				720x1920RGB	1	1	1

On the basis of the above embodiments, optionally, the resolution control module 30 is electrically connected to the front M/2 stage scan driving circuit 20 and the rear M/2 stage scan driving circuit 20, respectively. The display panel is arranged in such a way that when the display panel displays with low display resolution, the non-luminous area is arranged at the edge of the display panel, and the display picture is arranged in the middle area of the whole display panel.

It should be noted that, in the above embodiments, the overall display resolution of the display panel is exemplarily shown to be 1200 × 1920, which is not a limitation of the present invention. In other embodiments, the resolution of the display panel may be set to be higher, or the resolution of the display panel may be set to be lower, which may be set as required in practical applications.

Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention. Referring to fig. 6 and 7, on the basis of the above embodiments, optionally, the display panel further includes: a first clock signal line 10 and a second clock signal line 11. A first clock signal input terminal CLK of the odd-numbered scanning driving circuit is electrically connected to the first clock signal line 10, and a second clock signal input terminal XCLK of the odd-numbered scanning driving circuit is electrically connected to the second clock signal line 11. The first clock signal input terminal CLK of the even-numbered scan driving circuit is electrically connected to the second clock signal line 11, and the second clock signal input terminal XCLK of the even-numbered scan driving circuit is electrically connected to the first clock signal line 10.

The scan driving circuit includes: a first clock signal input terminal CLK, a second clock signal input terminal XCLK, a display switching signal input terminal ENI, a superior shift signal input terminal STV, a inferior shift signal output terminal NEXT, a scan signal output terminal OUT, a latch module 110, a first display control module 210, a second display control module 220, and a display switching module 310.

The latch module 110 is electrically connected to the first clock signal input terminal CLK, the upper shift signal input terminal STV, and the lower shift signal output terminal NEXT, respectively, and the latch module 110 is configured to latch the upper shift signal input from the upper shift signal input terminal STV in response to the first clock signal input from the first clock signal input terminal CLK, and output the latched signal through the lower shift signal output terminal NEXT.

The first display control module 210 is electrically connected to the second clock signal input terminal XCLK and the NEXT shift signal output terminal NEXT, respectively; the first display control module 210 is configured to output the second clock signal inputted from the second clock signal input terminal XCLK in response to the NEXT shift signal outputted from the NEXT shift signal output terminal NEXT.

The second display control module 220 is electrically connected to the NEXT shift signal output terminal NEXT; the second display control module 220 is used for responding to and outputting the lower shift signal output by the lower shift signal output terminal NEXT.

The display switching module 310 is electrically connected to the display switching signal input end ENI, the first display control module 210, the second display control module 220, and the scan signal output end OUT, respectively; the display switching module 310 is configured to switch on the first display control module 210 and the scan signal output terminal OUT or switch on the second display control module 220 and the scan signal output terminal OUT in response to a display switching signal input by the display switching signal input terminal ENI.

The display switching signal input end ENI inputs a display switching signal, the upper shift signal input end STV inputs an upper shift signal, the lower shift signal output end NEXT outputs a lower shift signal, and the scanning signal output end OUT outputs a scanning signal.

The latch module 110 latches the upper shift signal, that is, the latch module 110 can maintain the level state of the previous stage when the latch module 110 is turned off by the first clock signal. The first display control module 210 outputs the second clock signal inputted from the second clock signal input terminal XCLK in response to the NEXT shift signal outputted from the NEXT shift signal output terminal NEXT, that is, when the NEXT shift signal is a valid signal, the signal outputted from the first display control module 210 is controlled by the second clock signal. The signal output by the first display control module 210 may be the original second clock signal or the inverted second clock signal. The second display control module 220 responds to and outputs the NEXT shift signal output by the NEXT shift signal output terminal NEXT, that is, the second display control module 220 is controlled by the NEXT shift signal, and the signal output by the second display control module 220 may be the original NEXT shift signal or the inverted NEXT shift signal.

In the embodiment of the present invention, the first display control module 210 and the second display control module 220 are both electrically connected to the display switching module 310, and the display switching module 310 is configured to connect the first display control module 210 and the scan signal output end OUT, so as to implement a first display mode; or, the second display control module 220 and the scan signal output terminal OUT are turned on, so as to implement the second display mode. Compared with the prior art, the embodiment of the invention can be compatible with more display modes, and can display a plurality of display modes in a switchable manner, thereby enriching the scanning mode of the scanning driving circuit.

Illustratively, the first display control module 210 controls the scan signal output terminal OUT of the scan driving circuit to output a typical timing signal (normal timing), and the second display control module 220 controls the scan signal output terminal OUT of the scan driving circuit to output one or more of a global timing signal (global timing), a Rolling timing signal (Rolling timing), a Rolling black timing signal, a bright timing signal (dimming) or an aging timing signal (aging timing).

If the display switching module 310 turns on the first display control module 210 and the scan signal output terminal OUT in response to the display switching signal input from the display switching signal input terminal ENI, the scan signal output terminal OUT of the scan driving circuit outputs a typical timing signal. Fig. 8 is a schematic diagram of a driving timing sequence of a scan driving circuit according to an embodiment of the invention, referring to fig. 8, the driving timing sequence of the scan driving circuit exemplarily includes a first stage T1, a second stage T2, a third stage T3, a fourth stage T4, and a fifth stage T5.

In the first phase T1, the upper shift signal is at a high level (first high pulse phase), and the second clock signal is at a low level. When the first clock signal is at a low level, the latch module 110 latches the previous stage of the shift signal and continues to output a low level at the NEXT output terminal NEXT. When the first clock signal is at a high level, the latch module 110 outputs the upper shift signal to the lower shift signal output terminal NEXT in response to the high level of the first clock signal, that is, the lower shift signal output at the lower shift signal output terminal NEXT is also at a high level. The first display control module 210 outputs the Low level of the second clock signal in response to the high level of the next shift signal, that is, when the next shift signal is at the high level, the level of the signal output by the first display control module 210 is the same as the level of the second clock signal, and is the Low level (Low).

In the second phase T2, the upper shift signal is high (the second high pulse phase), and the first clock signal is low. The latch module 110 latches the upper shift signal of the first stage T1 and continues to output a high level at the lower shift signal output terminal NEXT. When the second clock signal is at a low level, the first display control module 210 outputs the low level of the second clock signal in response to the high level of the next shift signal. When the second clock signal is at a High level, the first display control block 210 outputs the High level of the second clock signal in response to the High level of the next shift signal, that is, when the next shift signal is at a High level, the signal output by the first display control block 210 is at a High level (High) in accordance with the level of the second clock signal.

In the third stage T3, the upper shift signal is low, the first clock signal is low, and the second clock signal is low. The latch module 110 latches the upper shift signal of the second stage T2 and continues to output a high level at the lower shift signal output terminal NEXT. The first display control module 210 outputs the Low level of the second clock signal in response to the high level of the next shift signal, that is, when the next shift signal is at the high level, the level of the signal output by the first display control module 210 is the same as the level of the second clock signal, and is the Low level (Low).

In the fourth phase T4, the upper shift signal is at a low level, the first clock signal is at a high level, and the second clock signal is at a low level. The latch module 110 outputs an upper shift signal in response to a high level of the first clock signal, and a lower shift signal output at a lower shift signal output terminal NEXT is also low. The first display control module 210 outputs a Low level in response to the Low level of the next shift signal, that is, when the next shift signal is at a Low level, the signal output by the first display control module 210 is always at a Low level (Low) regardless of the second clock signal.

In the fifth phase T5, the upper shift signal is low, and the first clock signal is low. The latch module 110 latches the upper shift signal of the fourth stage T4 and continues to output a low level at the lower shift signal output terminal NEXT. The first display control module 210 outputs a Low level in response to the Low level of the next shift signal, that is, when the next shift signal is at a Low level, the signal output by the first display control module 210 is always at a Low level (Low) regardless of the second clock signal.

By analogy, after the fifth stage T5, the upper shift signal remains at the low level, and the scan signal output terminal OUT outputs the low level.

Therefore, the scanning driving circuit shifts and outputs the upper-level shifting signal, and outputs the high-level pulse of the second clock signal to the scanning signal output end OUT in the second high-level pulse stage of the upper-level shifting signal, thereby realizing typical timing signal output. The scanning signals are transmitted stage by stage at the scanning signal output end OUT of each stage of scanning driving circuit, and the display panel is driven to realize a typical display mode.

If the display switching module 310 switches on the second display control module 220 and the scan signal output terminal OUT in response to the display switching signal input by the display switching signal input terminal ENI, the scan signal output terminal OUT of the scan driving circuit may output the entire timing signal. Fig. 9 is a schematic diagram of a driving timing sequence of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 9, the driving timing of the scan driving circuit exemplarily includes a sixth stage T6, a seventh stage T7, an eighth stage T8, a ninth stage T9, a tenth stage T10, and an eleventh stage T11.

In the sixth phase T6, the enable signal is low. When the first clock signal is at a low level, the latch module 110 latches the enable signal of the previous stage and continues to output a low level at the NEXT-stage shift signal output terminal NEXT. When the first clock signal is at a high level, the latch module 110 outputs the enable signal to the NEXT-stage shifted signal output terminal NEXT in response to the high level of the first clock signal, that is, the first NEXT-stage signal output at the NEXT-stage shifted signal output terminal NEXT is also at a high level. The second display control module 220 outputs the low level in response to the low level of the first lower level signal, that is, the second display control module 220 directly outputs the first lower level signal, and the second display control module 220 outputs the low level, thereby outputting the low level at the scan signal output terminal.

In the seventh phase T7, the start signal is low, and the first clock signal is low. The latch module 110 latches the enable signal of the sixth stage T6 and continues to output a low level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the low level in response to the low level of the first lower level signal, that is, the second display control module 220 directly outputs the first lower level signal, and the second display control module 220 outputs the low level, thereby outputting the low level at the scan signal output terminal.

In the eighth phase T8, the enable signal is low and the first clock signal is high. The latch module 110 and the second display control module 220 operate in the same state and output signals as the sixth stage T6, and the second display control module 220 outputs a low level, thereby outputting a low level at the scan signal output terminal.

In the ninth phase T9, the first clock signal is low. The latch module 110 latches the enable signal of the eighth stage T8 and continues to output a low level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the low level in response to the low level of the first lower level signal, that is, the second display control module 220 directly outputs the first lower level signal, and the second display control module 220 outputs the low level, thereby outputting the low level at the scan signal output terminal.

In the tenth stage T10, the enable signal is high, and the first clock signal is high. The latch module 110 outputs the enable signal to the NEXT-stage shifted signal output terminal NEXT in response to the high level of the first clock signal, i.e., the first NEXT-stage signal output at the NEXT-stage shifted signal output terminal NEXT is also high level. The second display control module 220 outputs the high level in response to the high level of the first lower level signal, that is, the second display control module 220 directly outputs the first lower level signal, and the second display control module 220 outputs the high level, thereby outputting the high level at the scan signal output terminal.

In the eleventh phase T11, the enable signal is high and the first clock signal is low. The latch module 110 latches the enable signal of the tenth stage T10 and continues to output a high level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the high level in response to the high level of the first lower level signal, that is, the second display control module 220 directly outputs the first lower level signal, and the second display control module 220 outputs the high level, thereby outputting the high level at the scan signal output terminal.

By analogy, after the eleventh stage T11, the start signal remains at the high level, the second display control module 220 outputs the high level, and the scan signal output terminal outputs the high level.

Therefore, the scanning driving circuit outputs the starting signal to realize the output of the whole timing signal, and the pulse width of the whole timing signal is the same as that of the starting signal and is not influenced by the clock signal. The scanning signals are simultaneously output at the scanning signal output end of each stage of scanning driving circuit, and the display panel is driven to realize an integral display mode. In the integral display mode, the pixels of all the rows are simultaneously opened and closed, so that each frame has complete and independent picture display, and the problem of trailing is avoided.

Fig. 10 is a schematic diagram of a driving timing sequence of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 10, the driving timing of the scan driving circuit exemplarily includes a twelfth stage T12, a thirteenth stage T13, a fourteenth stage T14, a fifteenth stage T15, a sixteenth stage T16, and a seventeenth stage T17.

In the twelfth phase T12, the enable signal is low and the second clock signal is high. The latch module 110 outputs the enable signal in response to the high level of the second clock signal, and the NEXT-stage shift signal output at the NEXT-stage shift signal output terminal NEXT is also low. The second display control module 220 outputs the low level in response to the low level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the low level at the scan signal output terminal.

In the thirteenth phase T13, the enable signal is low, and the first clock signal is low. The latch module 110 latches the enable signal of the twelfth stage T12 and continues to output a low level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the low level in response to the low level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the low level at the scan signal output terminal.

In the fourteenth phase T14, the start signal is low, and the first clock signal is high. The operation states and output signals of the latch module 110 and the second display control module 220 are the same as those of the twelfth stage T12, and a low level is output at the scan signal output terminal.

In the fifteenth phase T15, the start signal is low, and the first clock signal is low. The latch module 110 and the second display control module 220 have the same operation state and output signal as the thirteenth stage T13, and output a low level at the scan signal output terminal.

In the sixteenth phase T16, the enable signal is high, and the first clock signal is high. The latch module 110 outputs the enable signal to the NEXT-stage shifted signal output terminal NEXT in response to the high level of the first clock signal, that is, the NEXT-stage shifted signal output at the NEXT-stage shifted signal output terminal NEXT is also high level. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal.

In the seventeenth phase T17, the enable signal is high and the first clock signal is low. The latch module 110 latches the enable signal of the sixteenth stage T16 and continues to output a high level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal.

By analogy, after the seventeenth stage T17, the start signal remains high, and a high is output at the scan signal output terminal.

Therefore, the scanning driving circuit shifts and outputs the starting signal to realize the output of the rolling time sequence signal, and the pulse width of the rolling time sequence signal is the same as that of the starting signal and is not influenced by the clock signal. The scanning signal is transmitted step by step at the scanning signal output end of each stage of scanning driving circuit to drive the display panel to realize a rolling display mode. In a display mode of outputting the rolling time sequence signal, the output pulse of the odd-level scanning driving circuit corresponds to the first clock signal, and the output pulse of the even-level scanning driving circuit corresponds to the first clock signal. The scanning driving signals are transmitted step by step.

Fig. 11 is a schematic diagram of a driving timing sequence of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 11, the driving timing of the scan driving circuit exemplarily includes an eighteenth stage T18, a nineteenth stage T19, a twentieth stage T20, a twenty-first stage T21, and a twenty-second stage T22.

In the eighteenth phase T18, the enable signal is low and the first clock signal is low. The latch module 110 latches the enable signal of the previous stage and continues to output a high level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal.

In the nineteenth phase T19, the enable signal is low and the first clock signal is high. The latch module 110 outputs the enable signal in response to a high level of the first clock signal, and the NEXT-stage shifted signal output at the NEXT-stage shifted signal output terminal NEXT is also high. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal.

In the twentieth phase T20, the enable signal is low. If the first clock signal is at a low level, the latch module 110 latches the start signal of the previous stage and continues to output a low level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the low level in response to the low level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the low level at the scan signal output terminal. If the first clock signal is at a high level, the latch module 110 outputs the enable signal in response to the high level of the first clock signal, and the NEXT-stage shift signal output at the NEXT-stage shift signal output terminal NEXT is also at a low level. The second display control module 220 outputs the low level in response to the low level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the low level at the scan signal output terminal.

In the twenty-first phase T21, the enable signal is high and the first clock signal is high. The latch module 110 outputs the enable signal to the NEXT-stage shifted signal output terminal NEXT in response to the high level of the first clock signal, that is, the NEXT-stage shifted signal output at the NEXT-stage shifted signal output terminal NEXT is also high level. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal.

In the twentieth phase T22, the enable signal is high, and the first clock signal is low. The latch module 110 latches the enable signal of the twenty-first stage T21 and continues to output a high level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal.

By analogy, after the twentieth phase T22, the start signal remains high, and a high is output at the scan signal output terminal.

Therefore, the scanning driving circuit shifts and outputs the starting signal to realize the output of the rolling black erasing time sequence signal, and the pulse width of the rolling black erasing time sequence signal is the same as that of the starting signal and is not influenced by the clock signal. The scanning signal is transmitted step by step at the scanning signal output end of each stage of scanning driving circuit to drive the display panel to realize the rolling black wiping display mode. Different from the scrolling mode, the timing signal output by the scrolling black erasing mode is controlled by the first clock signal, and the frequency of the first clock signal is higher than that of the first clock signal. In a display mode of outputting a rolling black sequence signal, output pulses of the odd-level scanning driving circuit correspond to a first clock signal, and output pulses of the even-level scanning driving circuit correspond to the first clock signal. The scanning driving signals are transmitted step by step. Because the clock frequency of the first clock signal is greater than that of the first clock signal, the interval between the outputs of the adjacent two stages of scanning driving signals is smaller, and the time for completing the scanning of the whole display panel is shorter.

On the basis of the above embodiments, optionally, in the rolling black display mode, in one frame, the data signal is written by the pixel circuit within 80% of the time, and the display of all rows of pixels is completed within 20% of the time, that is, each image is completely and independently displayed, and there is no overlap between the frames, so that there is no afterimage in the display.

Fig. 12 is a schematic diagram of a driving timing sequence of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 12, the driving timing of the scan driving circuit illustratively includes a twentieth stage T23, a twenty-fourth stage T24, and a twenty-fifth stage T25.

In the twentieth stage T23, the start signal is low and the first clock signal is high. The latch module 110 outputs the enable signal in response to a high level of the first clock signal, and the NEXT-stage shifted signal output at the NEXT-stage shifted signal output terminal NEXT is also low. The second display control module 220 outputs the low level in response to the low level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the low level at the scan signal output terminal.

In the twenty-fourth period T24, the first clock signal is low. The latch module 110 latches the enable signal of the previous stage and continues to output a low level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the low level in response to the low level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the low level at the scan signal output terminal.

In the twenty-fifth phase T25, the enable signal is high. If the first clock signal is at a high level, the latch module 110 outputs the enable signal in response to the high level of the first clock signal, and the NEXT-stage shift signal output at the NEXT-stage shift signal output terminal NEXT is also at a high level. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal. If the first clock signal is at a low level, the latch module 110 latches the start signal of the previous stage and continues to output a high level at the NEXT-stage shift signal output terminal NEXT. The second display control module 220 outputs the high level in response to the high level of the lower shift signal, i.e., the second display control module 220 directly outputs the lower shift signal to output the high level at the scan signal output terminal.

By analogy, after the twenty-fifth stage T25, the start signal repeatedly outputs a low level pulse, and the scan driving circuit repeats the operating states of the twenty-third to twenty-fifth stages T23 to T25.

Therefore, the scanning driving circuit shifts and outputs the starting signal to realize the output of the bright time sequence signal, and the pulse width of the bright time sequence signal is not influenced by the clock signal. If the scanning drive circuits are connected in cascade, the scanning signals are transmitted step by step at the scanning signal output ends of the scanning drive circuits at all levels, and the display panel is driven to realize a bright display mode. Unlike the scrolling mode and the scrolling black erasing mode, the timing signal outputted in the bright mode is outputted in a frame with a plurality of low level pulses. In a display mode of outputting a bright timing signal, output pulses of the odd-numbered scanning driving circuits correspond to a first clock signal, and output pulses of the even-numbered scanning driving circuits correspond to the first clock signal. The scanning driving signals are transmitted step by step. The bright mode can effectively adjust the display brightness and increase the display contrast.

Fig. 13 is a schematic diagram of a driving timing sequence of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 13, for example, the first and second upper signal input terminals STV and STVR are always at a low level, so the first clock signal input terminal CLKR writes the low level of the second upper signal input terminal STVR into the second latch and control module 200, so that the scan signal output terminal is at a low level state, and the state is maintained. Therefore, the scanning driving circuit shifts and outputs the starting signal, the aging time sequence signal is output, and the pulse width of the aging time sequence signal is not influenced by the clock signal. If the scanning drive circuits are connected in cascade, the scanning signals are transmitted step by step at the scanning signal output ends of the scanning drive circuits at all stages, and the display panel is driven to realize an aging display mode.

On the basis of switching resolution ratio display, the embodiment of the invention also realizes the integration of six display modes, namely a typical display mode, an integral display mode, a rolling black wiping display mode, a bright display mode and an aging display mode, thereby being beneficial to improving the display quality of the display panel.

With continued reference to fig. 6, on the basis of the above embodiments, optionally, the display panel further includes a forward direction scanning control signal line 61 and a reverse direction scanning control signal line 62. The scan driving circuit includes a forward scan control signal input terminal U2D and a reverse scan control signal input terminal D2U, the forward scan control signal input terminal U2D is electrically connected to the forward scan control signal line 61, and the reverse scan control signal input terminal D2U is electrically connected to the reverse scan control signal line 62. The embodiment of the invention realizes the forward scanning and the reverse scanning of the display panel, and further enriches the display modes of the display panel.

Fig. 14 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 14, on the basis of the above embodiments, optionally, the scan driving circuit 20 further includes a voltage domain expansion module 410. The voltage domain expansion module 410 is connected between the display switching module 310 and the scan signal output terminal OUT, and the voltage domain expansion module 410 is configured to respond to the output of the display switching module 310 to expand the voltage level output by the display switching module 310 from the first voltage level V1 to the second voltage level V2 to the third voltage level V3 to the fourth voltage level V4; wherein | V2-V1| < | V4-V3 |.

Illustratively, the devices in the latch module 110, the first display control module 210 and the second display control module 220 use 8V devices, and the voltage domains of the signals input from the first clock signal input terminal CLK, the second clock signal input terminal XCLK and the upper shift signal input terminal STV are 0-5V. The first voltage level output by the display switching module 310 is 0V, and the second voltage level is 5V. That is, when the signal output by the display switching module 310 is at a low level, the voltage level is 0V; when the signal output by the display switching module 310 is at a high level, the voltage level is 5V. The third voltage output by the voltage domain expansion module 410 is-5V, and the fourth voltage is 5V. When the signal output by the voltage domain expansion module 410 is at a low level, the potential thereof is-5V; when the signal output by the voltage domain expansion module 410 is high, the voltage domain expansion module has a potential of 5V. The voltage domain expansion module 410 expands the voltage domain of the scan signal output terminal OUT from 0V to 5V to-5V.

In the embodiment of the present invention, the voltage domain expansion module 410 is disposed between the display switching module 310 and the scan signal output terminal OUT, so that the voltage domain expansion of the scan signal output terminal OUT is realized under the condition that the voltage domain of the input signal is not changed. The voltage domain of the input signal is unchanged, so that the circuit power consumption is kept low. The expansion of the output voltage domain is beneficial to resetting the pixel circuit with lower potential, and the resetting effect is good, thereby being beneficial to improving the display effect.

With continued reference to fig. 14, on the basis of the above embodiments, optionally, the voltage domain expansion module 410 includes a potential conversion module 411 and a potential selection module 412. The potential conversion module 411 is electrically connected to the display switching module 310, and the potential conversion module 411 is configured to respond to the output potential of the display switching module 310, translate the output potential of the display switching module 310, and output the translated output potential; the potential output by the potential conversion module 411 is switched between the first potential V1 and the third potential V3. The potential selection module 412 is electrically connected to the display switching module 310, the potential conversion module 411 and the scan signal output terminal OUT, respectively, and the potential selection module 412 is configured to respond to the potentials output by the display switching module 310 and the potential conversion module 411, and output the second potential output by the display switching module 310 to the scan signal output terminal OUT, or output the third potential output by the potential conversion module 411 to the scan signal output terminal OUT.

Illustratively, the voltage domain output by the display switching module 310 is 0-5V, and the voltage domain output by the potential converting module 411 is-5-0V. When the display switching module 310 outputs 0V and the potential conversion module 411 outputs-5V, the potential selection module 412 outputs-5V; when the display switching module 310 outputs 5V and the potential conversion module 411 outputs 0V, the potential selection module 412 outputs 5V, thereby realizing a voltage range of-5V to 5V.

With continued reference to fig. 14, on the basis of the above embodiments, optionally, the potential conversion module 411 includes a second inverter 411A and a level shifter 411B, an input end of the second inverter 411A is electrically connected to the display switching module 310, and an output end of the second inverter 411A is electrically connected to an input end of the level shifter 411B. The output terminal of the level shifter 411B is electrically connected to the potential selection block 412. The second inverter 411A is used to invert the potential outputted by the display switching module 310, and the level shifter 411B is used to shift the potential of the signal outputted by the second inverter.

With continued reference to fig. 14, based on the above embodiments, optionally, the potential selection module 412 includes a buffer, a first power input terminal of the buffer is electrically connected to the first potential output module, a second power input terminal of the buffer is electrically connected to the potential conversion module 411, an input terminal of the buffer is grounded, and an output terminal of the buffer is electrically connected to the scan signal output terminal OUT. When the display switching module 310 outputs 0V and the potential conversion module 411 outputs-5V, the buffer outputs-5V voltage; when the display switching module 310 outputs 5V and the potential conversion module 411 outputs 0V, the buffer outputs 5V, thereby realizing a voltage range of-5V to 5V.

With continued reference to fig. 14, on the basis of the above embodiments, optionally, the scan driving circuit 20 further includes an aging control signal input terminal XAG, a second potential signal input terminal VGH1, a third transistor M3 and a fourth transistor M4.

A control terminal of the third transistor M3 and a control terminal of the fourth transistor M4 are both electrically connected to the aging control signal input terminal XAG, and the third transistor M3 is connected between the input terminal of the buffer and ground; a first terminal of the fourth transistor M4 is electrically connected to the second potential signal input terminal VGH1, and a second terminal of the fourth transistor M4 is electrically connected to the input terminal of the buffer.

When the third transistor M4 and the fourth transistor M4 respond to the signal at the aging control signal input terminal XAG and turn on the second voltage signal input terminal VGH1 and the voltage selection module 640, the output voltage of the voltage selection module 412 is pulled low, so as to output the aging timing signal.

With continued reference to fig. 14, on the basis of the above embodiments, optionally, the display panel further includes a second resolution control signal line. The scan driving circuit 20 further includes: a first resolution control signal input terminal XENBV, a first potential signal input terminal GND, and a resolution control block 510; the first resolution control signal input terminal XENBV is electrically connected to the second resolution control signal line.

The resolution control block 510 is electrically connected to the first resolution control signal input XENBV, the ground GND and the scan signal output GND, respectively, and the resolution control block 510 is configured to respond to the resolution control signal input by the first resolution control signal input XENBV and conduct the signal from the ground GND to the scan signal output OUT.

Illustratively, the scan driving circuit 20 is a light emission control circuit (EMIT circuit) that controls on and off of the pixel circuit and the light emitting device. For example, when the light emission control circuit outputs a high level, the pixel circuit is disconnected from the light emitting device. When the resolution control module 510 is turned on by the first resolution control signal, the high level of the inverted ground signal is transmitted to the scan signal output terminal OUT, the pixel circuit electrically connected to the scan driving circuit is disconnected from the light emitting device, and the light emitting device does not emit light. In one frame, the first resolution control signal may be switched between a high level and a low level, and when the first resolution control signal controls the resolution control module 510 to be turned on, the corresponding pixel does not display a picture; when the first resolution control signal controls the resolution control module 510 to turn off, the corresponding pixel displays a picture. Namely, the embodiment of the invention can select the position for starting display and the position for finishing display, thereby realizing the function of controlling the display area and enabling the display panel to output pictures with different resolutions. The embodiment of the present invention is different from the resolution switching scheme with the tap function in that in practical application, the input signal to the first resolution control signal input terminal XENBV cannot accurately control the position where the display starts and the position where the display ends, but the embodiment can realize the control signal for fine tuning the display position.

With continued reference to fig. 14, on the basis of the above embodiments, optionally, the scan driving circuit 20 further includes a second resolution control signal input terminal ENBV; the second resolution control signal at the second resolution control signal input ENBV is the inverse of the first resolution control signal at the first resolution control signal input XENBV.

The resolution control module 510 includes: a first transistor M1 and a first inverter 511. The control terminal of the first transistor M1 is electrically connected to the first resolution control signal input XENBV, the first terminal of the first transistor M1 is electrically connected to the first potential signal input terminal, and the second terminal of the first transistor M1 is electrically connected to the scan signal output terminal. A first power input terminal of the first inverter 511 is electrically connected to the first resolution control signal input terminal XENBV, a second power input terminal of the first inverter 511 is electrically connected to the second resolution control signal input terminal ENBV, an input terminal of the first inverter 511 is electrically connected to the display switching module, and an output terminal of the first inverter 511 is electrically connected to the scan signal output terminal.

Illustratively, when the first resolution control signal is low and the second resolution control signal is high, the first inverter 511 is turned off, thereby disconnecting the output portion from the preceding logic circuit, and the first transistor M1 pulls the output high.

With continued reference to fig. 14, based on the above embodiments, the first transistor M1 may also optionally implement a reset function.

It should be noted that, the embodiment of the present invention exemplarily shows that the first transistor M1 can also implement the reset function, and the present invention is not limited thereto. In other embodiments, a transistor having a reset function may be provided as needed, and may be set as needed in practical applications. Two of them will be described below, but the present invention is not limited thereto.

Fig. 15 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 15, on the basis of the above embodiments, optionally, the scan driving circuit 20 further includes a reset control signal input terminal RST, a second potential signal input terminal VGH1 and a second transistor M2. The control terminal of the second transistor M2 is electrically connected to the reset control signal input terminal RST, the first terminal of the second transistor M2 is electrically connected to the second potential signal input terminal VGH1, and the second terminal of the second transistor M2 is electrically connected to the scan signal output terminal. The embodiment of the invention is arranged in such a way, and the OUT signal at the scanning signal output end can be reset.

Fig. 16 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. Referring to fig. 16, on the basis of the above embodiments, optionally, the scan driving circuit 20 further includes a reset control signal input terminal RST and a second transistor M2. The control end of the second transistor M2 is electrically connected with the reset control signal input end RST; a first terminal of the second transistor M2 is electrically connected to a first terminal of the first transistor M1, and a second terminal of the second transistor M2 is electrically connected to a second terminal of the first transistor M1.

The second transistor M2 and the first transistor M1 are arranged and connected in parallel, so that the problem that the second transistor M2 is connected with the second potential signal input end VGH1, and the area of the second transistor M2 needs to be large is solved.

With continued reference to fig. 16, based on the above embodiments, the latch module 110 optionally includes: a fourth inverter 111, a fifth inverter 112, a sixth inverter 113, and a seventh inverter 114. An input terminal of the fourth inverter 111 is electrically connected to the first clock signal input terminal. A first power input terminal of the fifth inverter 112 is electrically connected to the output terminal of the fourth inverter 111, a second power input terminal of the fifth inverter 112 is electrically connected to the first clock signal input terminal, and an input terminal of the fifth inverter 112 is electrically connected to the upper shift signal input terminal. A first power input terminal of the sixth inverter 113 is electrically connected to the upper-stage shift signal input terminal, a second power input terminal of the sixth inverter 113 is electrically connected to the output terminal of the fourth inverter 111, an input terminal of the sixth inverter 113 is electrically connected to the lower-stage shift signal output terminal, and an output terminal of the sixth inverter 113 is electrically connected to the output terminal of the fifth inverter 112. An input terminal of the seventh inverter 114 is electrically connected to an output terminal of the sixth inverter 113, and an output terminal of the seventh inverter 114 is electrically connected to the next-stage shift signal output terminal.

It should be noted that, in practical applications, the number of inverters and buffers can be set as required to improve the loading capability of the scan driving circuit.

The embodiment of the invention also provides a driving method of the display panel. The driving method of the display panel can be applied to the display panel provided by any embodiment of the invention. Fig. 17 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present invention. Referring to fig. 17, the driving method of the display panel includes the steps of:

s110, sending a resolution control signal to a resolution control signal line, and sending a first potential signal to a first potential signal line;

s120, controlling the resolution control module to conduct the corresponding input end and output end according to the signal of the resolution control signal line, driving the corresponding scanning driving circuit to shift and output scanning signals in sequence, and displaying the scanning signals as a first display resolution on the display panel;

or, according to the signal of the resolution control signal line, the resolution control module is controlled to conduct the first potential signal input end and the first potential signal output end, the corresponding scanning driving circuit is driven to stop working, and the display panel displays the second display resolution.

The embodiment of the invention realizes the function of driving all or part of the scanning driving circuits to output scanning signals by controlling the resolution control module. Therefore, the embodiment of the invention can be compatible with various display resolutions. In addition, the embodiment of the invention can flexibly set the position of the scanning driving circuit electrically connected with the resolution control module according to the requirement, which is equivalent to adding a tap function in the display panel. In addition, in the embodiment of the present invention, when the first potential signal input terminal and the upper shift signal input terminal of the scan driving circuit are turned on, it is equivalent to that a fixed potential signal is input to the scan driving circuit, and the internal device of the scan driving circuit does not operate. Therefore, when the display resolution is reduced, the embodiment of the invention not only can reduce the power consumption of the pixel, but also can reduce the power consumption of the scanning driving circuit.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, comprising: n scanning lines;

2. The display panel of claim 1, wherein the resolution control module comprises: the M first data selection modules are respectively and correspondingly connected between the M input ends and the M output ends of the resolution control module.

3. The display panel of claim 2, wherein the resolution control module further comprises: the second data selection module is connected between the P-th-level input end of the resolution control module and the P-th-level first data selection module;

the control signal end of the resolution control module comprises a first control signal end and a second control signal end; the control end of the first data selection module of the front P-1 level is electrically connected with the first control signal end; the control end of the first data selection module at the No. P to No. Q-1 level is electrically connected with the second control signal end; the control end of the second data selection module is electrically connected with the first control signal end;

wherein, P is more than 1 and more than Q and less than or equal to M, and P and Q are positive integers.

4. The display panel of claim 3, wherein the resolution control module further comprises a third data selection module, and the third data selection module is connected between the input end of the Q stage of the resolution control module and the first data selection module of the Q stage;

the control signal end of the resolution control module also comprises a third control signal end; the control end of the Q-X stage first data selection module is electrically connected with the third control signal end; the control end of the third data selection module is electrically connected with the second control signal end;

wherein, Q is more than X and less than or equal to M, and X is a positive integer.

5. The display panel according to claim 3, further comprising a data control signal line and a decoder, wherein an input terminal of the decoder is electrically connected to the data control signal line, and an output terminal of the decoder is electrically connected to the control signal terminal of the resolution control module.

6. The display panel according to claim 3, wherein the control terminal of the (M-Q +1) th to (M-P) th stage first data selection module is electrically connected to the second control signal terminal; and the control end of the (M-P +1) -M-th-level first data selection module is electrically connected with the first control signal end.

7. The display panel according to claim 1, wherein the resolution control module is electrically connected to the front M/2 stage scan driving circuit and the rear M/2 stage scan driving circuit, respectively.

8. The display panel according to claim 1, wherein the scan driver circuit comprises: the display control device comprises a first clock signal input end, a second clock signal input end, a display switching signal input end, a latch module, a first display control module, a second display control module and a display switching module;

the latch module is electrically connected with the first clock signal input end, the upper shift signal input end and the lower shift signal output end respectively, and is used for responding to a first clock signal input by the first clock signal input end, latching the upper shift signal input by the upper shift signal input end and outputting the upper shift signal through the lower shift signal output end;

the first display control module is electrically connected with the second clock signal input end and the lower-level shift signal output end respectively; the first display control module is used for responding to a lower-level shift signal output by the lower-level shift signal output end and outputting a second clock signal input by the second clock signal input end;

the second display control module is electrically connected with the lower-level shift signal output end; the second display control module is used for responding and outputting the lower-level shift signal output by the lower-level shift signal output end;

the display switching module is respectively and electrically connected with the display switching signal input end, the first display control module, the second display control module and the scanning signal output end; the display switching module is used for responding to a display switching signal input by the display switching signal input end, and conducting the first display control module and the scanning signal output end, or conducting the second display control module and the scanning signal output end.

9. The display panel according to claim 8, wherein the scan driver circuit further comprises: a voltage domain expansion module connected between the display switching module and the scan signal output terminal, the voltage domain expansion module being configured to respond to the output of the display switching module to expand the potential output by the display switching module from being switched between a first potential V1 and a second potential V2 to be switched between a third potential V3 and a fourth potential V4; wherein | V2-V1| < | V4-V3 |.

10. The display panel of claim 9, wherein the voltage domain expansion module comprises: the device comprises a potential conversion module and a potential selection module;

the potential conversion module is electrically connected with the display switching module and is used for responding to the output potential of the display switching module, translating the output potential of the display switching module and outputting the translated output potential; the potential output by the potential conversion module is switched between a first potential V1 and a third potential V3;

the potential selection module is electrically connected with the display switching module, the potential conversion module and the scanning signal output end respectively, and the potential selection module is used for responding to potentials output by the display switching module and the potential conversion module, outputting a second potential output by the display switching module to the scanning signal output end, or outputting a third potential output by the potential conversion module to the scanning signal output end.

11. The display panel according to claim 10, wherein the potential selection module comprises: the first power input end of the buffer is electrically connected with the first potential output module, the second power input end of the buffer is electrically connected with the potential conversion module, the input end of the buffer is grounded, and the output end of the buffer is electrically connected with the scanning signal output end.

12. The display panel according to claim 11, wherein the scan driver circuit further comprises an aging control signal input terminal, a second potential signal input terminal, a third transistor, and a fourth transistor;

a control end of the third transistor and a control end of the fourth transistor are both electrically connected with the aging control signal input end, and the third transistor is connected between the input end of the buffer and the ground; and a first end of the fourth transistor is electrically connected with the second potential signal input end, and a second end of the fourth transistor is electrically connected with the input end of the buffer.

13. The display panel according to claim 11, further comprising a second resolution control signal line;

the scan driving circuit further includes: the device comprises a first resolution control signal input end, a first potential signal input end and a resolution control module; the first resolution control signal input end is electrically connected with the second resolution control signal line;

the resolution control module is electrically connected with the first resolution control signal input end, the ground and the scanning signal output end respectively, and is used for responding to a resolution control signal input by the first resolution control signal input end and conducting a signal input by the first potential signal input end to the scanning signal output end.

14. The display panel of claim 13, wherein the scan driving circuit further comprises a second resolution control signal input; the second resolution control signal at said second resolution control signal input terminal being opposite to the first resolution control signal at said first resolution control signal input terminal;

the resolution control module includes: a first transistor and a first inverter;

the control end of the first transistor is electrically connected with the first resolution control signal input end, the first end of the first transistor is electrically connected with the first potential signal input end, and the second end of the first transistor is electrically connected with the scanning signal output end;

the first power input end of the first phase inverter is electrically connected with the first resolution control signal input end, the second power input end of the first phase inverter is electrically connected with the second resolution control signal input end, the input end of the first phase inverter is electrically connected with the display switching module, and the output end of the first phase inverter is electrically connected with the scanning signal output end.

15. The display panel according to claim 14, wherein the scan driver circuit further comprises a reset control signal input terminal and a second transistor;

the control end of the second transistor is electrically connected with the reset control signal input end;

the first end of the second transistor is electrically connected with the first end of the first transistor, and the second end of the second transistor is electrically connected with the second end of the first transistor.

16. The display panel according to claim 8, wherein the scan driver circuit further comprises a reset control signal input terminal, a second potential signal input terminal, and a second transistor;

the control end of the second transistor is electrically connected with the reset control signal input end, the first end of the second transistor is electrically connected with the second potential signal input end, and the second end of the second transistor is electrically connected with the scanning signal output end.

17. A driving method of the display panel according to claim 1, comprising: