CN110209613A - A kind of NVMe SSD reading speed and optical fiber interface speed adaptive matching process - Google Patents
A kind of NVMe SSD reading speed and optical fiber interface speed adaptive matching process Download PDFInfo
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Abstract
A kind of NVMe SSD reading speed and optical fiber interface speed adaptive matching process, it is related to technical field of data storage, to solve the problems, such as that NVMe SSD reading speed control method is more to data buffer storage resource occupation in FPGA in the prior art, the following steps are included: FPGA first receives the data packet from the NVMe SSD reading data returned, RxReady signal is then dragged down into five clock cycle.The transmission speed of data packet when the present invention reads data by the RxReady signal control NVMe SSD of AXI-Stream data receiver interface on PCIe stone, NVMe SSD data reading speed is set to match with fiber data interface speed, it does not need a complete read command splitting into several subcommands, and enough time sequence allowances are left to receive and parsing the process of data packet, exploitation is simple.And this method can reduce demand of the data read process to cache resources, when logical block size for NVMe SSD is 512Byte and 4KByte, the Block Ram cache resources usage amount for saving 50% and 92% respectively, can be widely applied to technical field of data storage.
Description
Technical field
The present invention relates to technical field of data storage, specially a kind of NVMe SSD reading speed and optical fiber interface speed are certainly
Adapt to matching process.
Background technique
NVMe SSD is a new generation's storage equipment occurred in recent years, can be with by the high transmission speed of PCIe bus
Realize the data reading speed of 2GB/s or more.NVMe SSD's is small in size, low in energy consumption, and cooperation FPGA can form miniaturization, just
The fiber data for taking stores equipment.The data stored in equipment are transmitted to data processing equipment using optical fiber interface by equipment, this
The optical fiber interface of kind X4 reaches the overall data transmission rate of 12.5Gbps.
NVMe stores equipment when executing read command, and the speed ratio NVMe SSD of fiber data interface reads the speed of data
Slowly, it is therefore necessary to NVMe SSD reading speed and optical fiber interface speed are matched using some way.Usually control reading speed
Method it is as follows: reduce the size of each NVMe read command and between adjacent read command insertion wait interval.Due to NVMe
The logical block size of SSD is fixed (512Byte or 4KByte), and the size of each read command must be the integer of logical block
Times, therefore the size of read command has minimum limitation.In this case, the data buffer storage FIFO in FPGA must be sufficiently large, with
Guarantee by fiber data interface to the data that other equipment are sent be complete.
Summary of the invention
The purpose of the present invention is: for NVMe SSD reading speed control method in the prior art to data buffer storage in FPGA
The more problem of resource occupation proposes a kind of NVMe SSD reading speed and optical fiber interface speed adaptive matching process.
In order to solve the above-mentioned technical problem the present invention adopts the technical scheme that: a kind of NVMe SSD reading speed and optical fiber
Interface rate adaptive matching method, comprising the following steps: FPGA first receives the number from the NVMe SSD reading data returned
According to packet, RxReady signal is then dragged down into five clock cycle.
Further, the RxReady signal is dragged down by state machine.
Further, the state of the state machine includes: idle state, parsing packet header state, wait state and RxReady
Signal state of a control.
Further, the transformational relation between the state of the state machine are as follows:
When state machine is in idle condition, RxReady signal is 1, judges whether to receive data packet head, if so, jumping
Parsing packet header state is gone to, if it is not, resting on current state；
When state machine is in parsing packet header state, the header packet information of data packet is parsed, judges currently received data packet
Whether include the data read from NVMe SSD, if so, record parameter current ParamRdData is 1, joins if it is not, record is current
Number ParamRdData is 0, then jumps to wait state；
And judge whether currently received data packet includes the data read from NVMe SSD, then jump to state three；
When state machine is waited for, judge whether current data packet transmission is completed, if so, jumping to
RxReady signal state of a control, if it is not, resting on current state；
When state machine is in RxReady signal state of a control, according to the ParamRdData parameter pair in state two
RxReady is controlled, and judges whether RxReady signal control process is completed, if so, idle state is jumped to, if it is not,
Rest on current state.
Further, RxReady signal is dragged down by sub-state machine in the RxReady signal state of a control.
Further, in the sub-state machine optical fiber interface data transmission bauds are as follows:
Wherein, WaitCycle is the RxReady signal low level lasting clock cycle.
Further, the WaitCycle meets formula:
Further, the state of the sub-state machine includes: idle state, RxReady signal pull-down state, wait state
State is drawn high with RxReady signal.
Further, the transformational relation between the state of the sub-state machine are as follows:
When sub-state machine is in idle condition, judge whether state machine enters state four and ParamRdData parameter is
No is 1, if so, RxReady signal pull-down state is jumped to, if it is not, resting on current state；
When sub-state machine is in RxReady signal pull-down state, RxReady signal is dragged down, waiting is then jumped to
State；
When sub-state machine is waited for, judge that the current RxReady signal low level lasting clock cycle is
It is no equal with parameter WaitCycle, if so, jumping to RxReady signal draws high state, if it is not, resting on current state；
When sub-state machine, which is in RxReady signal, draws high state, RxReady signal is drawn high, and is sent to state machine
Signal is completed in the control of RxReady signal, then jumps to idle state.
The beneficial effects of the present invention are:
1, this method controls NVMe SSD by the RxReady signal of AXI-Stream data receiver interface on PCIe stone
The transmission speed of data packet, makes NVMe SSD data reading speed match with fiber data interface speed, no when reading data
It needs to split into a complete read command several subcommands, and leaves foot to receive and parsing the process of data packet
Enough time sequence allowances, exploitation are simple；
2, this method can reduce demand of the data read process to cache resources, for the logical block size of NVMe SSD
When for 512Byte and 4KByte, 50% and 92% Block Ram cache resources usage amount is saved respectively；
3, this method has scalability, for the optical fiber interface of friction speed, only need to modify one of parameter i.e.
The matching of NVMe SSD reading speed and friction speed optical fiber interface can be achieved.
Detailed description of the invention
Fig. 1 is AXI-Stream interface waveform figure in the specific embodiment of the invention one.
Fig. 2 is RxReady signal state of a control transition diagram when the present invention receives data.
Fig. 3 is the state transition graph that RxReady signal of the present invention controls sub-state machine.
Specific embodiment
Specific embodiment 1: present embodiment is illustrated referring to Fig.1, and in the present embodiment, a kind of NVMe SSD
Reading speed and optical fiber interface speed adaptive matching process, comprising the following steps: FPGA first is received to be returned from NVMe SSD
Reading data data packet, RxReady signal is then dragged down into five clock cycle.
NVMe stores equipment when executing read command, and the speed ratio NVMe SSD of fiber data interface reads the speed of data
Slowly, in order to realize the matching of NVMe SSD data reading speed Yu fiber data interface speed, it is necessary to reduce the number of NVMe SSD
According to reading speed.
Common method waits interval by reducing the size of each NVMe read command, being inserted between adjacent read command
To realize the control for reading data speed to NVMe SSD.This method by NVMe SSD logical block size (512Byte or
Limitation 4KByte) can only control the average speed that NVMe SSD reads data.In this case, the data in FPGA are slow
Depositing FIFO must be sufficiently large, to guarantee that there is no loss of data phenomenons in reading data and repeating process.
In fiber data storage equipment, FPGA and NVMe SSD is carried out data transmission by PCIe bus.Benefit of the invention
It is realized with the PCIe stone (being integrated in FPGA for realizing the logic circuit of PCIe function) of Xilinx FPGA to NVMe SSD
Read-write Catrol.PCIe stone in FPGA is received and is handled to received NVMe data packet first, and AXI- is then passed through
By treated, data packet is sent to user logic to Stream bus.AXI-Stream bus includes five baseband signal Ready,
Data, Keep, Valid and Last.Only when the Ready signal of user logic control is 1, the just meeting of AXI-Stream bus
Data transmission is initiated, user logic can just receive the data returned from PCIe bus.Meanwhile PCIe stone is according in its structure
The residual capacity of intrinsic data buffer storage resource is sent and pause to control the data packet of NVMe SSD.
The present invention utilizes the above-mentioned characteristic of RxReady signal, the transmission of AXI-Stream data flow is controlled, to reach control
The purpose of the data reading speed of NVMe SSD processed.
After FPGA is received from the data packet of the NVMe SSD reading data returned, when RxReady signal drags down five
In the clock period, the data in AXI-Stream bus are transmitted placed in a suspend state at this time, after RxReady is drawn high, AXI-Stream
Data transmission in bus just will continue to carry out, as shown in Figure 1.By controlling RxReady signal, set between different data packet
Idle clock cycles are set, the data transmission speed of NVMe SSD can be reduced, guarantee that the data buffer storage FIFO of receiving end does not overflow
Out；The idle clock cycle is reserved to parse and store the data packet received for receiving end simultaneously, holds that development process more
Easily.The efficiency of transmission that PCIe when reading NVMe SSD can be calculated according to the signal waveform of Fig. 1 is 57%, is compiled in conjunction with 8B/10B
The PCIe Gen2X4 bus maximum valid data transmission speed of code is 2GB/s, can calculate maximum valid data of the invention
Transmission speed is 1.14GB/s, may be implemented to match with optical fiber interface speed.
In conjunction with concrete application scene, the Block Ram cache resources quantity in the FPGA of saving is analyzed.Life is read using decomposing
It enables and the method for insertion latent period is come when controlling NVMe SSD reading data speed, it is assumed that NVMe SSD, which is sent, reads data
Data speed packet is 1.8GB/s, and optical fiber interface speed is 1.1GB/s, in order to guarantee that data are not lost, when the logic of NVMe SSD
When block size is respectively 512Byte and 4KByte, in FPGA the capacity of data buffer storage be greater than respectively 200Byte and
1.6KByte, it is contemplated that each PCIe data packet length is 128Byte, therefore the capacity of data buffer storage is greater than respectively
256Byte and 1664Byte.It is sent using the data packet of RxReady signal control NVMe SSD, it can be by data buffer storage capacity
It is reduced to 128Byte, saves 50% and 92% respectively when the logical block size of NVMe SSD is 512Byte and 4KByte
Block Ram cache resources usage amount.
Traditional fractionation read command method needs a NVMe read command splitting into a large amount of subcommand, to increase life
Enable the complexity of control module.This method does not need to split a complete read command, can reduce order control mould
The scale of block.In addition, method proposed by the present invention is to connect compared with traditional design for continuously receiving and parsing through multiple data packets
It receives and the process of parsing data packet leaves enough time sequence allowances, simplify the development process of relevant portion.
Specific embodiment 2: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment one
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment one is institute
RxReady signal is stated to be dragged down by state machine.
Specific embodiment 3: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment two
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment two is institute
The state for stating state machine includes: idle state, parsing packet header state, wait state and RxReady signal state of a control.
Specific embodiment 4: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment three
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment three is institute
State the transformational relation between the state of state machine are as follows:
When state machine is in idle condition, RxReady signal is 1, judges whether to receive data packet head, if so, jumping
Parsing packet header state is gone to, if it is not, resting on current state；
When state machine is in parsing packet header state, the header packet information of data packet is parsed, judges currently received data packet
Whether include the data read from NVMe SSD, if so, record parameter current ParamRdData is 1, joins if it is not, record is current
Number ParamRdData is 0, then jumps to wait state；
And judge whether currently received data packet includes the data read from NVMe SSD, then jump to state three；
When state machine is waited for, judge whether current data packet transmission is completed, if so, jumping to
RxReady signal state of a control, if it is not, resting on current state；
When state machine is in RxReady signal state of a control, according to the ParamRdData parameter pair in state two
RxReady is controlled, and judges whether RxReady signal control process is completed, if so, idle state is jumped to, if it is not,
Rest on current state.As shown in Figure 2.
Specific embodiment 5: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment four
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment four is institute
RxReady signal in RxReady signal state of a control is stated to be dragged down by sub-state machine.
In RxReady signal state of a control, the present invention devises a sub-state machine and controls to RxReady signal
System sends data speed packet to achieve the purpose that control NVMe SSD.
Specific embodiment 6: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment five
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment five be
The data transmission bauds formula of optical fiber interface in the sub-state machine are as follows:
Wherein, WaitCycle is the RxReady signal low level lasting clock cycle.
In sub-state machine introduce parameter WaitCycle, for judge RxReady signal the low level duration whether
It meets the requirements.
Specific embodiment 7: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment six
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment six is institute
State the formula of WaitCycle are as follows:
It must be integer in view of in FPGA, the parameter is corresponding with the counting of clock cycle, so being carried out to it upwards
It is rounded.
Specific embodiment 8: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment five
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment five is institute
The state for stating sub-state machine includes: idle state, RxReady signal pull-down state, wait state and RxReady signal draw high shape
State.
Specific embodiment 9: present embodiment is to a kind of NVMe SSD reading speed described in specific embodiment eight
With the further explanation of optical fiber interface speed adaptive matching process, the difference of present embodiment and specific embodiment eight is institute
State the transformational relation between the state of sub-state machine are as follows:
When sub-state machine is in idle condition, judge whether state machine enters state four and ParamRdData parameter is
No is 1, if so, RxReady signal pull-down state is jumped to, if it is not, resting on current state；
When sub-state machine is in RxReady signal pull-down state, RxReady signal is dragged down, waiting is then jumped to
State；
When sub-state machine is waited for, judge that the current RxReady signal low level lasting clock cycle is
It is no equal with parameter WaitCycle, if so, jumping to RxReady signal draws high state, if it is not, resting on current state；
When sub-state machine, which is in RxReady signal, draws high state, RxReady signal is drawn high, and is sent to state machine
Signal is completed in the control of RxReady signal, then jumps to idle state.As shown in figure 3, the state four of total state machine is in Fig. 3
The RxReady signal state of a control of state machine.
Above method method is not limited solely to the optical fiber interface that the present invention uses.For the optical fiber interface of friction speed,
It only needs to modify the RxReady=0 lasting clock cycle, of NVMe SSD reading speed Yu optical fiber interface speed can be realized
Match.
It should be noted that specific embodiment is only the explanation and illustration to technical solution of the present invention, it cannot be with this
Limit rights protection scope.What all claims according to the present invention and specification were made is only locally to change, Reng Yingluo
Enter in protection scope of the present invention.
Claims (9)
1. a kind of NVMe SSD reading speed and optical fiber interface speed adaptive matching process, it is characterised in that including following step
It is rapid: when FPGA is received from the data packet of the NVMe SSD reading data returned, RxReady signal being dragged down into five clock weeks
Phase.
2. a kind of NVMe SSD reading speed according to claim 1 and optical fiber interface speed adaptive matching process,
Be characterized in that: the RxReady signal is dragged down by state machine.
3. a kind of NVMe SSD reading speed according to claim 2 and optical fiber interface speed adaptive matching process,
It is characterized in that, the state of the state machine includes: idle state, parsing packet header state, wait state and the control of RxReady signal
State.
4. a kind of NVMe SSD reading speed according to claim 3 and optical fiber interface speed adaptive matching process,
The transformational relation being characterized in that between the state of the state machine are as follows:
When state machine is in idle condition, RxReady signal is 1, judges whether to receive data packet head, if so, jumping to
Packet header state is parsed, if it is not, resting on current state；
When state machine is in parsing packet header state, the header packet information of data packet is parsed, whether judges currently received data packet
Comprising the data read from NVMe SSD, if so, record parameter current ParamRdData is 1, if it is not, record parameter current
ParamRdData is 0, then jumps to wait state；
And judge whether currently received data packet includes the data read from NVMe SSD, then jump to state three；
When state machine is waited for, judge whether current data packet transmission is completed, if so, jumping to RxReady letter
Number state of a control, if it is not, resting on current state；
When state machine is in RxReady signal state of a control, according to the ParamRdData parameter in state two to RxReady
It is controlled, and judges whether RxReady signal control process is completed, if so, jumping to idle state, worked as if it is not, resting on
Preceding state.
5. a kind of NVMe SSD reading speed according to claim 4 and optical fiber interface speed adaptive matching process,
Be characterized in that: RxReady signal is dragged down by sub-state machine in the RxReady signal state of a control.
6. a kind of NVMe SSD reading speed according to claim 5 and optical fiber interface speed adaptive matching process,
It is characterized in that: the data transmission bauds of optical fiber interface in the sub-state machine are as follows:
Wherein, WaitCycle is the RxReady signal low level lasting clock cycle.
7. a kind of NVMe SSD reading speed according to claim 6 and optical fiber interface speed adaptive matching process,
Be characterized in that: the WaitCycle meets formula:
8. a kind of NVMe SSD reading speed according to claim 5 and optical fiber interface speed adaptive matching process,
Be characterized in that, the state of the sub-state machine includes: idle state, RxReady signal pull-down state, wait state and
RxReady signal draws high state.
9. a kind of NVMe SSD reading speed according to claim 8 and optical fiber interface speed adaptive matching process,
It is characterized in that, the transformational relation between the state of the sub-state machine are as follows:
When sub-state machine is in idle condition, judge state machine whether enter state four and ParamRdData parameter whether be
1, if so, RxReady signal pull-down state is jumped to, if it is not, resting on current state；
When sub-state machine is in RxReady signal pull-down state, RxReady signal is dragged down, wait state is then jumped to；
When sub-state machine is waited for, judge the current RxReady signal low level lasting clock cycle whether with
Parameter WaitCycle is equal, if so, jumping to RxReady signal draws high state, if it is not, resting on current state；
When sub-state machine, which is in RxReady signal, draws high state, RxReady signal is drawn high, and is sent to state machine
Signal is completed in the control of RxReady signal, then jumps to idle state.
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