CN110209547A - Refreshing frequency determines method and system when a kind of overturning of SRAM type FPGA single particle is fixed - Google Patents
Refreshing frequency determines method and system when a kind of overturning of SRAM type FPGA single particle is fixed Download PDFInfo
- Publication number
- CN110209547A CN110209547A CN201910368564.3A CN201910368564A CN110209547A CN 110209547 A CN110209547 A CN 110209547A CN 201910368564 A CN201910368564 A CN 201910368564A CN 110209547 A CN110209547 A CN 110209547A
- Authority
- CN
- China
- Prior art keywords
- fpga
- overturning
- refreshing frequency
- error rate
- rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
Abstract
Refreshing frequency determines method and system when a kind of overturning of SRAM type FPGA single particle is fixed, the reinforcement measure applied to SRAM type FPGA is needed to be verified and assessed, using direct fault location as verifying means, it is overturn by being injected to the configuring area of FPGA, the operating status for observing FPGA application determines that the single-particle inversion of application designs validity, solve the problems, such as that the prior art can not be quantitatively evaluated FPGA application and reinforce validity simultaneously, and it can determine the refreshing frequency value range of FPGA, calculate easy, method high reliablity.
Description
Technical field
The present invention relates to refreshing frequencys when a kind of overturning of SRAM type FPGA single particle is fixed to determine method and system, belongs to
FPGA application fault tolerance design field.
Background technique
In recent years, space mission proposes higher demand to onboard processing, to the volume, weight and function of electronic equipment
Consumption also has a stringenter limitation, while applied satellite develops to micromation, integrated direction, to low cost, quickly opens
The demand of hair is also more urgent.FPGA (the field programmable gate battle array of commercial SRAM (static random access memory type)
Column), have many advantages, such as integrated level is high, development cost is low, high-performance, low-power consumption and can on-line reorganization, become space application and lead
The focus of attention in domain, and be gradually applied in space industry.Single-particle inversion, i.e. SEU feelings easily occur for SRAM type FPGA simultaneously
Condition, therefore in space application SRAM type FPGA, it needs to carry out specific aim protection design for SEU problem, it is ensured that FPGA's answers
With the in-orbit stable operation demand that can meet task.
Redundancy, including error-detection error-correction, triplication redundancy technology are that common anti-single particle overturning is reinforced with periodic refreshing
Means.Engineering practice shows that redundancy is used alone or refreshes and can not need to combine the two up to ideal consolidation effect
Come.In space application, the reinforcing of SRAM type FPGA is generally also required to simultaneously using two kinds of reinforcing means of redundancy and refreshing.To FPGA
The reinforcing of application is effective not always necessarily, if reinforcing mode is inappropriate, is then also unable to reach while consuming system resource
It is expected that reinforcing target.Mature SRAM type FPGA single particle overturning there is no to reinforce verifying means, currently available means in engineering at present
Include:
Heavy ion irradiation test: heavy ion radiation is the means most directly, most accurately examined to reinforcing validity, but
Limited, experimental design, the relevant technologies are complicated when being irradiation bomb machine, and need to prepare special test circuit, therefore be chiefly used in grinding
Study carefully, technical identification, is not suitable as the curriculum test means in engineering to FPGA design.
Simulated fault injection: presently, there are a variety of emulation, analysis methods to carry out error rate, it is expected that its cost is small, but essence
Degree is insufficient.Simulated fault injection simultaneously needs specifically to design FPGA, and has certain probability domain knowledge, therefore this method is suitable
FPGA Design of Reinforcement is checked together in single machine designer, but is not ideal Assessment.
Direct fault location is a kind of direct and easy-to-use verifying means between radiation test and simulation analysis, pass through to
Injection overturning inside FPGA observes the operating status of FPGA application to determine the anti-single particle flip designs validity of application.Mesh
Prior fault injection can be divided into dynamic fault injection and inject two kinds with static failure, and dynamical fashion is relatively direct, but is
Design of uniting is complex, and static failure injection realizes that simply versatility is good, but test result not can be used directly and with brush
The circuit design of new strategy.
Summary of the invention
Technical problem solved by the present invention is being reinforced in currently available technology to FPGA application single-particle inversion
It is good to lack versatility when the qualitative assessment of effect property, in engineering, it is easy to accomplish method, the means based on static failure injection propose
A kind of wire examination method of SRAM type FPGA single particle overturning reinforcement measure, can quantitatively obtain the in-orbit overturning rate of FPGA application circuit,
And designer is helped to select the periodic refreshing frequency applied.
The present invention solves above-mentioned technical problem and is achieved by following technical solution:
Refreshing frequency determines method when a kind of overturning of SRAM type FPGA single particle is fixed, the specific steps are as follows:
(1) Design of Reinforcement is carried out to FPGA circuitry, according to space radiation environment, the static upset cross section curve of FPGA circuitry
In-orbit static overturning rate analysis is carried out to FPGA circuitry, obtains the in-orbit static overturning rate u of FPGA circuitry；
(2) configuration file of FPGA circuitry under original state is rewritten, random writing N bit flipping, operation FPGA electricity
Road records in M test, the test number (TN) of output error or function interruption occurs in different overturning digits, and calculate
The error rate λ of FPGA circuitry operationN；
(3) the digit N overturn in the configuration file of FPGA circuitry is incrementally increased, as the error rate λ of FPGA operationNIt is greater than
When 50%, stop direct fault location test, and misregistration ratio lambdaN；
(4) the average sensitivity position ratio r under data calculating N bit flipping is recorded according to step (3)N, judge when N increases, N
Average sensitivity position ratio r under bit flippingNWhether the increase multiple with overturning digit N is greater than change threshold K, if so, into
Step (5) carries out minimum in-orbit overturning rate judgement；Otherwise stop test, return step (1) reinforces FPGA circuitry again
Design；
(5) the in-orbit overturning rate E of minimum of current Design of Reinforcement is calculatedmin, and judge minimum in-orbit overturning rate EminIt is whether small
In the circuit error rate E of model task setting0If EminNot less than E0, then the FPGA circuitry radiation resistance after reinforcing is insufficient,
Return step (1) carries out Design of Reinforcement again to FPGA circuitry；If EminGreater than E0, then Design of Reinforcement is effective, enters step (6)；
(6) refreshing is timed to the effective FPGA circuitry of Design of Reinforcement, calculates FPGA circuitry error rate and periodic refreshing
The relationship of frequency f；
(7) refreshing frequency f is arbitrarily chosen in the tolerance band of model task, calculates FPGA electricity under current refreshing frequency
Road error rate Ef, and the circuit error rate E with model task setting0It is compared, if EfLess than E0, then current refreshing frequency can
With otherwise current refreshing frequency is too low, increases periodic refreshing frequency and recalculates FPGA circuitry error rate under the refreshing frequency；
Record meets in step (7) the periodic refreshing frequency of screening conditions with FPGA application error in corresponding refreshing frequency f
Lower error rate EfNumerical value, and repeat step (7) obtain model task license refreshing frequency within the scope of Ef- f curve, for
Family voluntarily selects refreshing frequency.
In the step (2), the digit N that overturning is injected under original state is equal to 1, the wrong ratio of the FPGA circuitry operation
Example λNFor, the ratio of FPGA circuitry output error or function are interrupted under observable state number and test total degree M, pilot scale
The setting condition for testing total degree M is as follows:
It is persistently tested, until the output error or function of observing 50 times or more are interrupted；Such as to test period
Restricted, then the output error or function interruption times that can be will be observed that are reduced to 20 times.
The initial digit of N bit flipping is 1, in M test, overturns digit and is incremented by with exponential form.
The generation that mistake is interrupted with function can not be observed when FPGA circuitry operation, then can pass through [16u/E0]
Terminate direct fault location test after secondary test, while with error rate upper limit E under 95% confidence level0Mistake of/the 4u as the secondary test
Accidentally ratio lambdaN。
Average sensitivity position ratio r in the step (5), under N bit flippingNCalculation method it is as follows:
The change threshold K is rNIncrease multiple, that is, take overturning digit N maximum value be NmaxWhen, average sensitivity position ratio
For rN_max:
K=rN_max/r1。
If change threshold K > 5, Design of Reinforcement is effective, otherwise assert that the FPGA circuitry radiation resistance after reinforcing is insufficient,
Return step (1) carries out Design of Reinforcement again to FPGA circuitry.
In the step (5), minimum in-orbit overturning rate EminCalculation formula are as follows:
Emin=λ1u。
In the step (6), error rate EfIt is as follows with the relational expression of periodic refreshing period f:
P (N)=uNf-Ne-u/f/N！
In formula, P (N) is the probability that N bit flipping occurs in a refresh cycle, and u is the in-orbit static overturning in the configuring area FPGA
Rate, EfBe using f as refreshing frequency under FPGA circuitry in-orbit error rate.
Refreshing frequency determines system when a kind of overturning of SRAM type FPGA anti-single particle is fixed, including direct fault location module,
Run-time error ratio judgment module, in-orbit overturning rate judgment module, circuit error rate computing module, refreshing frequency choose module,
Wherein:
Direct fault location module: rewriting the configuration file of FPGA circuitry under original state, random writing N bit flipping,
FPGA circuitry is run, is recorded in M test, occurs the test time of output error or function interruption in different overturning digits
Number；The digit N for incrementally increasing overturning simultaneously is carried out repeating test and is recorded experimental data；
Run-time error ratio judgment module: the test data recorded according to direct fault location module is calculated in different flip bits
In the case where number N, the error rate λ of FPGA circuitry operationN, as error rate λNWhen greater than 50%, sent to direct fault location module
Stop test instructions, misregistration ratio lambdaN；
In-orbit overturning rate judgment module: in the case where different overturnings digit N obtained by run-time error ratio judgment module
The error rate λ of recordN, calculate separately the average sensitivity position ratio r under N bit flippingN, judge when N increases, under N bit flipping
Average sensitivity position ratio rNWhether the increase multiple with overturning digit N is greater than change threshold K, if so, carrying out circuit error rate
Judgement；Otherwise stop test, Design of Reinforcement again is carried out to FPGA circuitry；
Circuit error rate computing module: the in-orbit overturning rate E of minimum of current Design of Reinforcement is calculatedmin, and judge minimum in-orbit
Overturning rate EminWhether the circuit error rate E of model task setting is less than0If EminNot less than E0, then reinforce after FPGA circuitry
Radiation resistance is insufficient, carries out Design of Reinforcement again to FPGA circuitry；If EminGreater than E0, then Design of Reinforcement is effective, is refreshed
Frequency selection purposes；
Refreshing frequency chooses module: being timed refreshing to the effective FPGA circuitry of Design of Reinforcement, it is wrong to calculate FPGA circuitry
The relational expression of rate and periodic refreshing frequency f is missed, refreshing frequency f is arbitrarily chosen in the tolerance band of model task, calculates current brush
FPGA circuitry error rate E under new frequencyf, and the circuit error rate E with model task setting0It is compared, if EfLess than E0, then
Current refreshing frequency is available, and otherwise current refreshing frequency is too low, increases periodic refreshing frequency and recalculates under the refreshing frequency
FPGA circuitry error rate is until meet model mission requirements.
The advantages of the present invention over the prior art are that:
(1) a kind of periodic refreshing frequency of the anti-list example overturning reinforcement measure of SRAM type FPGA provided by the invention determines
Method combines orbital environment analysis and fault filling method, can quantitative forecast to the in-orbit error rate of SRAM type FPGA,
It solves the problems, such as that FPGA application anti-single particle overturns reinforcement measure without quantitative appraisal in current engineering, while passing through measuring error ratio
Example λNWith overturning digit N curve, this method can go out whether circuit has there are redundancy with Direct Recognition, for irredundant/low redundancy
The circuit of degree, periodic refreshing strategies ineffective need to re-start Design of Reinforcement；
(2) present invention can instruct the determination of periodic refreshing frequency, consider that SEU event occurs meeting Poisson distribution, in conjunction with
The in-orbit static overturning rate of device and mission requirements, obtain refreshing frequency and FPGA using relationship between in-orbit error rate, help to set
Count teacher and select flushing policy, while using static failure method for implanting is used, only need to the configuration file to FPGA inject repair at random
Change, when examination does not need the specific design document of FPGA application, realizes easy, can be applicable in the SRAM type FPGA of different model.
Detailed description of the invention
Fig. 1 is the frequency determination methods flow chart that invention provides；
Fig. 2 is the average sensitivity position ratio r under the N bit flipping that invention providesNWith the trend chart of overturning digit N；
Relationship between the refreshing frequency and the in-orbit error rate indication result that Fig. 3 is the circuit B that invention provides；
Specific embodiment
Refreshing frequency determines method when a kind of overturning of SRAM type FPGA anti-single particle is fixed, specific to walk as shown in Fig. 1
It is rapid as follows:
(1) to FPGA circuitry carry out Design of Reinforcement, to the Design of Reinforcement of circuit generally comprise hardware integration Redundancy Design,
The parts such as program correction, periodic refreshing, wherein hardware design part, according to the used FPGA circuitry component model of application,
Task orbit parameter, mission requirements, and space radiation environment is combined, the FPGA circuitry after analysis is reinforced is quiet on space orbit
State overturning rate u；
Wherein, task orbit parameter need to provide task perigee of orbit, apogee and inclination angle, and model mission requirements are general
Including to the requirement of FPGA in-orbit function interruption rate, in the in-orbit error rate requirements of various types mistake.In the present invention, with mistake
Accidentally rate E0Instead of all kinds of mistakes of mission requirements.
(2) N failures are injected to the configuration file of the FPGA circuitry device configuring area under original state at random, is had
The FPGA circuitry of N bit flipping runs the circuit, and wherein fault filling method is as follows:
(2a) N number of mistake of random writing into the configuration file of application at random；
(2b) will be configured to application circuit with vicious configuration file；
(2c) runs circuit, and whether detection circuit has output error or function to interrupt, and records mistake and abnormal feelings
The test number (TN) that condition occurs；
(2d) stops this test if still failing to the exception of observation in the stipulated time, calculates the operation of FPGA circuit
Error rate λN, if it is desired, error configurations injection testing can be continued, start direct fault location next time, and repeat the above steps；
Wherein, it is specified that time setting need to be determined according to concrete application, need to guarantee the mistake that the time makes enough in FPGA application in principle
Accidentally it is observed；
Meanwhile M test is carried out, when observing enough error events, calculate separately in test every time with not
The error rate λ of the FPGA application design of same N bit flippingN, error rate is equal to the error number observed divided by examination here
Test number λN=#Error/#Test；
Wherein, in M test, the test number (TN) that error event goes wrong cannot be less than 50 times, persistently be tested,
Until the output error or function of observing 50 times or more are interrupted；It is such as restricted to test period, then it can will be observed that
Output error or function interruption times be reduced to 20 times；
And if circuit error ratio lambdaNIt is extremely low, the hair that mistake is interrupted with function can not be observed when FPGA circuitry operation
It is raw, then maximum test number (TN) can be set as test total degree M, then stops test, maximum examination after reaching maximum test number (TN)
Testing number will determine according to circuit reliability requirement, such as system requirements circuit error rate is not higher than E0, then corresponding circuits are wrong
Accidentally ratio is not greater than E0/ u requires Test to Failure precision to can achieve E here0/ 4u then recommends test number (TN) not less than [16u/
E0], in the case, even if not observing mistake, can also use under 95% confidence level circuit error ratio upper limit 4/M as
FPGA replaces circuit error ratio lambda using the error rate upper limit of designNIt uses；
(3) the overturning digit N injected to the configuring area FPGA is incrementally increased, error rate λ is obtainedNWith the pass of overturning digit N
System, in which:
When overturning digit is larger, circuit error ratio lambdaNWith N increase variation it is unobvious, it is proposed that with exponential form by
Step increases N, for example, injection overturning digit selection can be with are as follows: 1,2,4,6,10,20,40,60,100,200 ...
When error rate ratio lambdaNWhen reaching 50% or more, direct fault location test can be terminated；
(4) validity of decision circuitry Design of Reinforcement records average quick under data calculating N bit flipping according to step (3)
Feel position ratio rN, judge the average sensitivity position ratio r when N increases, under N bit flippingNIt is with the changing value that failure overturns digit N
It is no to be greater than change threshold K, if so, entering step (5) carries out minimum in-orbit overturning rate judgement；Otherwise stop test, to reinforcing
FPGA circuitry is redesigned afterwards, in which:
The calculation formula of average sensitive position ratio under the N bit flipping is as follows:
Describedization threshold k refers to rNIncrease multiple, that is, take overturning digit N maximum value be NmaxShi Pingjun sensitivity position ratio
rN_maxWith r1Ratio:
K=rN_max/r1
As K < 5, it may be considered that circuit redundancy is insufficient, periodic refreshing measure not can be reduced in-orbit overturning rate, can only
As a kind of abnormal restoring measure, which needs to re-start Design of Reinforcement；If change threshold K > 5, Design of Reinforcement have
Otherwise effect assert that the FPGA circuitry radiation resistance after reinforcing is insufficient, re-starts Design of Reinforcement；
(5) in the case of calculating current failure overturning digit, the in-orbit overturning rate E of minimum of FPGA circuitry after reinforcingmin, as
Judgement injection N bit flipping is to error rate λ1With the product of the in-orbit static overturning rate u of device, periodic refreshing strategy circuit will be passed through
The in-orbit overturning rate λ of minimum that can achieve1The circuit error rate of u and model task setting is E0It is compared, if λ1u≥E0,
Then illustrate that the anti-SEU performance of circuit is insufficient, no matter at much refreshing frequency f, is unable to satisfy the fault-tolerance requirement to SEU, needs
It redesigns；If λ1u<E0, then the circuit Design of Reinforcement is effective, can enter refreshing frequency analysis in next step；
Minimum in-orbit overturning rate EminCalculation formula are as follows:
Emin=λ1u；
(6) refreshing is timed to the effective FPGA circuitry of Design of Reinforcement, determines FPGA circuitry error rate and periodic refreshing
The relationship of frequency f overturns digit N according to in-orbit static overturning rate u, current failure obtained by step (1), and calculating with f is that timing is brushed
When new frequency, the relational expression of application error rate and periodic refreshing period f；
It is available to be brushed at one according to Poisson distribution according to overturning rate u in the configuring area FPGA is calculated in (1) step
In new period 1/f, N bit flipping probability P (N) calculation formula occurs for the configuring area FPGA are as follows:
P (N)=uNf-Ne-u/f/N！,
Then in a refresh cycle 1/f, there is error probability E calculation formula in FPGA application circuit are as follows:
It is corresponding, after taking using f as the periodic refreshing strategy of refreshing frequency, the application error rate E of FPGA circuitry after reinforcingf
It is as follows with the relational expression of periodic refreshing period f:
Circuit error probability E is a far smaller than 1 data in a usual refresh cycle, and above-mentioned formula can also approximate letter
Chemical conversion
At this point, choosing the refreshing frequency f in model task tolerance band, calculated according to above-mentioned formula, it is corresponding, with
The circuit error rate E of design requirement0It is compared, if EfLess than E0, then current refreshing frequency is available, otherwise current refreshing frequency
Deficiency is chosen periodic refreshing frequency again and is recalculated under the refreshing frequency, using Design of Reinforcement error rate, wants until meeting
It asks；
(8) record meet in step (7) the periodic refreshing frequency of screening conditions and FPGA application error corresponding refreshing frequently
Error rate E under rate ffNumerical value, and repeat step (7) obtain model task license refreshing frequency within the scope of Ef- f curve supplies
User voluntarily selects refreshing frequency.
Meanwhile cooperating the above method, it is true to devise refreshing frequency when a kind of overturning of SRAM type FPGA anti-single particle is fixed
Determine system, including direct fault location module, run-time error ratio judgment module, in-orbit overturning rate judgment module, circuit error rate meter
Calculate module, refreshing frequency chooses module, in which:
Direct fault location module: rewriting the configuration file of FPGA circuitry under original state, random writing N bit flipping,
FPGA circuitry is run, is recorded in M test, occurs the test time of output error or function interruption in different overturning digits
Number；The digit N for incrementally increasing overturning simultaneously is carried out repeating test and is recorded experimental data；
Run-time error ratio judgment module: the test data recorded according to direct fault location module is calculated in different flip bits
In the case where number N, the error rate λ of FPGA circuitry operationN, as error rate λNWhen greater than 50%, sent to direct fault location module
Stop test instructions, misregistration ratio lambdaN；
In-orbit overturning rate judgment module: in the case where different overturnings digit N obtained by run-time error ratio judgment module
The error rate λ of recordN, calculate separately the average sensitivity position ratio r under N bit flippingN, judge when N increases, under N bit flipping
Average sensitivity position ratio rNWhether the increase multiple with overturning digit N is greater than change threshold K, if so, carrying out circuit error
Rate judgement；Otherwise stop test, Design of Reinforcement again is carried out to FPGA circuitry；
Circuit error rate computing module: the in-orbit overturning rate E of minimum of current Design of Reinforcement is calculatedmin, and judge minimum in-orbit
Overturning rate EminWhether the circuit error rate E of model task setting is less than0If EminNot less than E0, then the FPGA circuitry after reinforcing is anti-
Radiance is insufficient, carries out Design of Reinforcement again to FPGA circuitry；If EminGreater than E0, then Design of Reinforcement is effective, carries out refreshing frequency
Rate is chosen；
Refreshing frequency chooses module: being timed refreshing to the effective FPGA circuitry of Design of Reinforcement, it is wrong to calculate FPGA circuitry
The relational expression of rate and periodic refreshing frequency f is missed, refreshing frequency f is arbitrarily chosen in the tolerance band of model task, calculates current brush
FPGA circuitry error rate E under new frequencyf, and the circuit error rate E with model task setting0It is compared, if EfLess than E0, then
Current refreshing frequency is available, and otherwise current refreshing frequency is too low, increases periodic refreshing frequency and recalculates under the refreshing frequency
FPGA circuitry error rate is until meet model mission requirements.
It is further described combined with specific embodiments below:
The invention proposes a kind of FPGA circuitry application periodic refreshing frequencies based on static failure injection in true method, can
For determining the in-orbit error rate of SRAM type FPGA periodic refreshing frequency and quantitative appraisal FPGA application.
The in-orbit overturning rate that the first step need to be constrained according to track, device static state section and space weather to indicate device,
Specific method can refer to document " the SEU rate analysis method of triplication redundancy technology safeguard structure " (the 11st anti-radiation electricity in the whole nation
Son is learned and electromagnetic pulse Annual Conference).By taking 3,000,000 FPGA of Xilinx V2 series as an example, in-orbit static state overturning rate is seen below
Shown in table.
Assuming that certain model requires the device to be able to bear most severe 1 day environment, and mission requirements are one day most severe
FPGA application error rate must not be higher than E under environment0=1 time/weekly.
According to device averagely overturning 1.94 × 10 per second-2It is secondary, then 11733 bit flippings can averagely occur within averagely one week, take three
Position effective digital is about 1.2 × 104Secondary overturning, then need to guarantee each bit bit flipping cause the probability of mistake less than 1/1.2 ×
104=8.3 × 10-5, it is noted here that 8.3 × 10-5And error rate when non-corresponding one bit flipping of direct fault location, generally
For, start to accumulate with number is overturn in the configuring area FPGA, when SEU, caused error probability can rise, in periodic refreshing strategy
Under, the average corresponding wrong probability of each overturning is related with refreshing frequency.
Second step carries out direct fault location, needs exist for observing not less than 50 times mistakes, if circuit reinforcement performance is managed
Think, has done progress 1.2 × 104× 16=19.2 × 104Mistake is also not observed in secondary test, then can stop testing, and press
According under 95% confidence level, the circuit error rate confidence interval upper limit 2.05 × 10-5In-orbit error rate is applied to assess/predict.
Third step, variation injection overturning digit N, obtains error rate λNWith overturning digit N curve, if circuit error rate
Higher than 50%, then it can stop testing, into next step.
Whether the 4th step, analysis circuit are reinforced effective.Assuming that two circuit A, B direct fault location test result such as following tables.
Here the error rate λ of circuitNIt closely calculates, it is corresponding also by rNIt calculates out, rNRelationship with N is as schemed
Shown in 2.
Circuit A corresponds to average sensitivity position ratio r under the N bit flipping of configuring area with the increase of NNIt is almost unchanged, this kind of circuit
It is the typical nonredundent circuit for not adding safeguard procedures, periodic refreshing can not reduce its in-orbit error rate.Its in-orbit error rate is u
λ1, taking most severe one day overturning rate u here is 1.94 × 10-2Secondary/s, circuit error ratio lambda1About 2.0 × 10-4, obtain circuit
The in-orbit minimal error rate E of AminFor 2.3 times/weekly, E must not be higher than by being unsatisfactory for error rate0=1 time/requirement weekly.
Circuit B corresponds to rNIncrease with the increase of N, this is that typical phenomenon after redundancy reinforcing is carried out to circuit, by fixed
When refresh can reduce the in-orbit error rate of this kind of circuit, minimum can be reduced to λ1u.If circuit B corresponds to a bit flipping mistake
The product λ of ratio and device overturning rate1U is greater than E0, E in the present example0=1 times/week, static overturning rate u is 1.94 × 10-2Secondary/
S can be calculated, if corresponding λ1>8.3×10-5, then no matter circuit refreshes how often, is unable to satisfy anti-single particle overturning
Performance requirement needs to re-start Design of Reinforcement；It is on the contrary then illustrate to can satisfy mission requirements using appropriate refreshing frequency.
5th step, the determination of periodic refreshing frequency.The purpose of periodic refreshing be to try to reduce SEU configuring area accumulation,
Reduce wrong occurrence frequency.Here it by taking circuit B as an example, is analyzed.
Rough estimation, refreshing frequency f, a refresh cycle can be carried out to refreshing frequency before being accurately calculated
Digit n=[u/f] (bracket indicates to be rounded) is inside averagely overturn, then can use rnU simply to judge wrong in a refresh cycle
Accidentally probability, and use Ef=rnU makees simple method of estimation to error probability, it is noted that the above method can only help fast according to a preliminary estimate
Speed determines substantially refreshing frequency range, is not suitable for as final analysis result.Preliminary Analysis Results see the table below.
According to upper table as a result, and error rate be not more than 1 times/week of requirement, can should be selected with the preliminary judgement refresh cycle
It selects between 5.2~8.6 minutes.
1. selecting the refresh cycle is 6 minutes, the requirement that error rate is not more than 1 times/week is met with lower refreshing frequency.Meter
Calculation process such as following table, it is very low to be greater than 20 probability for a cycle overturning digit in this example, is more than by overturning digit here
20 bit-errors ratios treat as 100%, with this estimating circuit error rate upper limit.
It is 5.68 × 10 that the total probability of mistake, which occurs, for circuit because SEU out of available in table a refresh cycle 360s-4, being converted to unit time error rate is Ef=E*f=1.578 × 10-6Secondary/second=0.95 times/week, can satisfy mission requirements.
2. selecting the refresh cycle is 60 seconds, to improve circuit optimized protection performance, a cycle overturns digit in this example
Greater than 10 probability are very low, are more than here 10 bit-errors ratios as 100% by overturning digit.Calculating process such as following table.
It is 3.35 × 10 that the probability of mistake, which occurs, for circuit because SEU out of available in table a refresh cycle 60s-5, turn
Being changed to unit time error rate is Ef=E*f=5.58 × 10-7Secondary/second=0.34 times/week, it is wrong under the refresh cycle compared with 360 seconds
Accidentally rate is only original 36%, and after improving refreshing frequency, circuit anti-single particle overturning performance improves 180%, is had more bright
Aobvious improvement.
3. the best anti-single particle of circuit overturns performance
Here circuit can reach optimal anti-SEU protective performance after we will discuss raising refreshing frequency.Periodic refreshing
It can reach the most ideal situation is that due to using flushing policy, the overturning of the configuring area FPGA is repaired quickly, can not accumulate.But
Flushing policy cannot prevent from individually configuring mistake caused by bit flipping simultaneously.Therefore when almost only single in a refresh cycle
Mean that circuit has had reached optimized protection effect when a bit bit flipping, circuit error rate is equal to u* λ at this time1.Theoretically
Add circuit B after periodic refreshing that can reach 0.211 times/week of minimum overturning rate.
In this example, we calculate circuit error rate, concrete outcome under multiple refreshing frequencys and see Fig. 3.It can be seen that with
The reduction of refresh cycle, the increase of refreshing frequency, circuit error rate Step wise approximation Circuit theory lowest error rate u* λ1。
Refreshing frequency is higher in practical application means that circuit resource consumption increases, therefore should not reach maximum to pursue
Protective performance and infinitely increase refreshing frequency, with for this example, mission requirements error rate is not more than 1 times/week, selects 6 minutes
Refresh cycle can satisfy requirement, and 6 minutes primary refreshing frequencys are to meet mission requirements minimum refreshing frequency；It examines
Consider and promote anti-SEU performance, select 1 minute refresh cycle, then error rate can be reduced to 0.34 times/week, more be suitable for；And 10 seconds
One time error rate can be further decreased to 0.22 times/week by refreshing frequency, and in comparison SEU reinforcement performance is promoted few, but
It pays a price higher, promotes SEU reinforcement performance not as good as considering to improve circuit Redundancy Design.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.
Claims (10)
1. refreshing frequency determines method when a kind of SRAM type FPGA single particle overturning is fixed, it is characterised in that steps are as follows:
(1) Design of Reinforcement is carried out to FPGA circuitry, according to space radiation environment, the static upset cross section curve pair of FPGA circuitry
FPGA circuitry carries out in-orbit static overturning rate analysis, obtains the in-orbit static overturning rate u of FPGA circuitry；
(2) configuration file of FPGA circuitry under original state is rewritten, random writing N bit flipping, runs FPGA circuitry, note
In M test of record, there is the test number (TN) of output error or function interruption in different overturning digits, and calculate FPGA electricity
The error rate λ of road transport rowN；
(3) the digit N overturn in the configuration file of FPGA circuitry is incrementally increased, as the error rate λ of FPGA operationNGreater than 50%
When, stop direct fault location test, and misregistration ratio lambdaN；
(4) the average sensitivity position ratio r under data calculating N bit flipping is recorded according to step (3)N, judge that N are turned over when N increases
Average sensitivity position ratio r under turningNWhether the increase multiple with overturning digit N is greater than change threshold K, if so, entering step
(5) minimum in-orbit overturning rate judgement is carried out；Otherwise stop test, return step (1) carries out Design of Reinforcement again to FPGA circuitry；
(5) the in-orbit overturning rate E of minimum of current Design of Reinforcement is calculatedmin, and judge minimum in-orbit overturning rate EminWhether type is less than
The circuit error rate E of number task setting0If EminNot less than E0, then the FPGA circuitry radiation resistance after reinforcing is insufficient, returns to step
Suddenly (1) carries out Design of Reinforcement again to FPGA circuitry；If EminGreater than E0, then Design of Reinforcement is effective, enters step (6)；
(6) refreshing is timed to the effective FPGA circuitry of Design of Reinforcement, calculates FPGA circuitry error rate and periodic refreshing frequency f
Relationship；
(7) refreshing frequency f is arbitrarily chosen in the tolerance band of model task, calculates FPGA circuitry mistake under current refreshing frequency
Rate Ef, and the circuit error rate E with model task setting0It is compared, if EfLess than E0, then current refreshing frequency is available, otherwise
Current refreshing frequency is too low, increases periodic refreshing frequency and recalculates FPGA circuitry error rate under the refreshing frequency.
Refreshing frequency determines method when 2. a kind of SRAM type FPGA single particle overturning according to claim 1 is fixed,
Be characterized in that: record meets in step (7) the periodic refreshing frequency of screening conditions with FPGA application error in corresponding refreshing frequency f
Lower error rate EfNumerical value, and repeat step (7) obtain model task license refreshing frequency within the scope of Ef- f curve, for
Family voluntarily selects refreshing frequency.
Refreshing frequency determines method when 3. a kind of SRAM type FPGA single particle overturning according to claim 1 is fixed,
It is characterized in that:
In the step (2), the digit N that overturning is injected under original state is equal to 1, the error rate λ of the FPGA circuitry operationN
For the ratio of FPGA circuitry output error or function are interrupted under observable state number and test total degree M, wherein test is total
The setting condition of number M is as follows:
It is persistently tested, until the output error or function of observing 50 times or more are interrupted；It is such as limited to test period
System, the then output error or function interruption times that can be will be observed that are reduced to 20 times.
Refreshing frequency determines method when 4. a kind of SRAM type FPGA single particle overturning according to claim 3 is fixed,
Be characterized in that: the initial digit of N bit flipping is 1, in M test, overturns digit and is incremented by with exponential form.
Refreshing frequency determines method when 5. a kind of SRAM type FPGA single particle overturning according to claim 3 is fixed,
It is characterized in that: can not observe the generation that mistake is interrupted with function when FPGA circuitry operation, then can pass through [16u/E0]
Terminate direct fault location test after secondary test, while with error rate upper limit E under 95% confidence level0Mistake of/the 4u as the secondary test
Accidentally ratio lambdaN。
Refreshing frequency determines method when 6. a kind of SRAM type FPGA single particle overturning according to claim 1 is fixed,
It is characterized in that: the average sensitivity position ratio r in the step (5), under N bit flippingNCalculation method it is as follows:
The change threshold K is rNIncrease multiple, that is, take overturning digit N maximum value be NmaxWhen, average sensitivity position ratio is
rN_max:
K=rN_max/r1。
Refreshing frequency determines method when 7. a kind of SRAM type FPGA single particle overturning according to claim 6 is fixed,
Be characterized in that: if change threshold K > 5, Design of Reinforcement is effective, otherwise assert that the FPGA circuitry radiation resistance after reinforcing is insufficient,
Return step (1) carries out Design of Reinforcement again to FPGA circuitry.
Refreshing frequency determines method when 8. a kind of SRAM type FPGA anti-single particle overturning according to claim 1 is fixed,
It is characterized by: in the step (5), minimum in-orbit overturning rate EminCalculation formula are as follows:
Emin=λ1u。
Refreshing frequency determines method when 9. a kind of SRAM type FPGA anti-single particle overturning according to claim 1 is fixed,
It is characterized by: in the step (6), error rate EfIt is as follows with the relational expression of periodic refreshing period f:
P (N)=uNf-Ne-u/f/N！
In formula, P (N) is the probability that N bit flipping occurs in a refresh cycle, and u is the in-orbit static overturning rate in the configuring area FPGA, Ef
Be using f as refreshing frequency under FPGA circuitry in-orbit error rate.
10. refreshing frequency determines system when a kind of SRAM type FPGA anti-single particle overturning is fixed, spy is: infusing including failure
Enter module, run-time error ratio judgment module, in-orbit overturning rate judgment module, circuit error rate computing module, refreshing frequency choosing
Modulus block, in which:
Direct fault location module: rewriting the configuration file of FPGA circuitry under original state, random writing N bit flipping, operation
FPGA circuitry records in M test, occurs the test number (TN) of output error or function interruption in different overturning digits；
The digit N for incrementally increasing overturning simultaneously is carried out repeating test and is recorded experimental data；
Run-time error ratio judgment module: the test data recorded according to direct fault location module is calculated different overturning digit N's
In the case of, the error rate λ of FPGA circuitry operationN, as error rate λNWhen greater than 50%, sends and stop to direct fault location module
Test instructions, misregistration ratio lambdaN；
In-orbit overturning rate judgment module: it is recorded in the case where according to different overturnings digit N obtained by run-time error ratio judgment module
Error rate λN, calculate separately the average sensitivity position ratio r under N bit flippingN, judge when N increases, being averaged under N bit flipping
Sensitive position ratio rNWhether the increase multiple with overturning digit N is greater than change threshold K, if so, carrying out the judgement of circuit error rate；
Otherwise stop test, Design of Reinforcement again is carried out to FPGA circuitry；
Circuit error rate computing module: the in-orbit overturning rate E of minimum of current Design of Reinforcement is calculatedmin, and judge minimum in-orbit overturning
Rate EminWhether the circuit error rate E of model task setting is less than0If EminNot less than E0, then reinforce after FPGA circuitry it is anti-radiation
Performance is insufficient, carries out Design of Reinforcement again to FPGA circuitry；If EminGreater than E0, then Design of Reinforcement is effective, carries out refreshing frequency choosing
It takes；
Refreshing frequency chooses module: being timed refreshing to the effective FPGA circuitry of Design of Reinforcement, calculates FPGA circuitry error rate
With the relational expression of periodic refreshing frequency f, refreshing frequency f is arbitrarily chosen in the tolerance band of model task, is calculated and current is refreshed frequency
FPGA circuitry error rate E under ratef, and the circuit error rate E with model task setting0It is compared, if EfLess than E0, then currently
Refreshing frequency is available, and otherwise current refreshing frequency is too low, increases periodic refreshing frequency and recalculates FPGA under the refreshing frequency
Circuit error is blunt to meeting model mission requirements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910368564.3A CN110209547B (en) | 2019-05-05 | 2019-05-05 | SRAM type FPGA single event upset reinforcement timing refresh frequency determination method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910368564.3A CN110209547B (en) | 2019-05-05 | 2019-05-05 | SRAM type FPGA single event upset reinforcement timing refresh frequency determination method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110209547A true CN110209547A (en) | 2019-09-06 |
| CN110209547B CN110209547B (en) | 2023-06-16 |
Family
ID=67786875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910368564.3A Active CN110209547B (en) | 2019-05-05 | 2019-05-05 | SRAM type FPGA single event upset reinforcement timing refresh frequency determination method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110209547B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113254288A (en) * | 2021-06-02 | 2021-08-13 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7764081B1 (en) * | 2005-08-05 | 2010-07-27 | Xilinx, Inc. | Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity |
| CN103840823A (en) * | 2014-02-14 | 2014-06-04 | 北京时代民芯科技有限公司 | Astronavigation FPGA universal refresh circuit based on JTAG interface and achieving method thereof |
| CN104051002A (en) * | 2014-06-06 | 2014-09-17 | 中国科学院长春光学精密机械与物理研究所 | Single event upset resistant SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refresh circuit and refresh method |
| CN106293991A (en) * | 2016-08-10 | 2017-01-04 | 上海无线电设备研究所 | FPGA anti-single particle based on ECC upset fast refresh circuitry and method |
| CN107817439A (en) * | 2016-09-13 | 2018-03-20 | 北京航空航天大学 | A kind of disabler time appraisal procedure based on SRAM type FPGA sensitive factors |
-
2019
- 2019-05-05 CN CN201910368564.3A patent/CN110209547B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7764081B1 (en) * | 2005-08-05 | 2010-07-27 | Xilinx, Inc. | Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity |
| CN103840823A (en) * | 2014-02-14 | 2014-06-04 | 北京时代民芯科技有限公司 | Astronavigation FPGA universal refresh circuit based on JTAG interface and achieving method thereof |
| CN104051002A (en) * | 2014-06-06 | 2014-09-17 | 中国科学院长春光学精密机械与物理研究所 | Single event upset resistant SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refresh circuit and refresh method |
| CN106293991A (en) * | 2016-08-10 | 2017-01-04 | 上海无线电设备研究所 | FPGA anti-single particle based on ECC upset fast refresh circuitry and method |
| CN107817439A (en) * | 2016-09-13 | 2018-03-20 | 北京航空航天大学 | A kind of disabler time appraisal procedure based on SRAM type FPGA sensitive factors |
Non-Patent Citations (3)
| Title |
|---|
| 卢凌云等: "基于定向故障注入的SRAM型FPGA单粒子翻转效应评估方法", 《微电子学》 * |
| 朱启等: "基于SRAM型FPGA可重构技术的故障注入系统设计", 《空间电子技术》 * |
| 王月玲等: "一种用于评估抗辐射DSP单粒子翻转的试验方法", 《微电子学与计算机》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113254288A (en) * | 2021-06-02 | 2021-08-13 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
| CN113254288B (en) * | 2021-06-02 | 2021-09-21 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110209547B (en) | 2023-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5561762A (en) | Malicious fault list generation method | |
| US7324363B2 (en) | SPICE optimized for arrays | |
| US8073668B2 (en) | Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation | |
| Carmichael et al. | Proton testing of SEU mitigation methods for the Virtex FPGA | |
| CN101777749B (en) | Group-based bcu methods for on-line dynamical security assessments and energy margin calculations | |
| CN102054056B (en) | Rapid simulation method for anti-radiation property of field programmable gate array (FPGA) | |
| CN105893664A (en) | System level single event effect influence representation parameter and evaluation method | |
| US6571202B1 (en) | Method for applying design for reliability into design for six sigma | |
| CN105548866A (en) | SRAM type FPGA test method based on irradiation test environment simulation | |
| CN115310048B (en) | Method and system for calculating repair probability of equipment in expected time | |
| CN110209547A (en) | Refreshing frequency determines method and system when a kind of overturning of SRAM type FPGA single particle is fixed | |
| Park et al. | The total delay fault model and statistical delay fault coverage | |
| CN108181524B (en) | Method for evaluating sensitivity of single event effect of electronic system obtained by irradiating bottom device | |
| US7376918B2 (en) | Probabilistic noise analysis | |
| Boulghassoul et al. | System-level design hardening based on worst-case ASET simulations | |
| Contini et al. | A novel method to apply Importance and Sensitivity Analysis to multiple Fault-trees | |
| CN116822843A (en) | Spare part demand amount calculation method and system for electronic serial components | |
| Chen | Some recent advances in design of bayesian binomial reliability demonstration tests | |
| Ogden et al. | The impact of soft error event topography on the reliability of computer memories | |
| CN104820777A (en) | Method for identifying single-particle protective weak spots of spacecraft system | |
| Lojda et al. | Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs | |
| Kieckhafer et al. | On the sensitivity of NMR unreliability to non-exponential repair distributions | |
| Huang et al. | On the development of fault injection profiles | |
| CN107194090B (en) | Method for estimating single-particle error rate cross section of anti-irradiation complex integrated circuit | |
| Egorov | Simulation model of dependability of redundant computer systems with recurrent information recovery |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |