CN110209397A - A kind of data processing method, apparatus and system - Google Patents
A kind of data processing method, apparatus and system Download PDFInfo
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- CN110209397A CN110209397A CN201910393260.2A CN201910393260A CN110209397A CN 110209397 A CN110209397 A CN 110209397A CN 201910393260 A CN201910393260 A CN 201910393260A CN 110209397 A CN110209397 A CN 110209397A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
This specification embodiment is disclosed a kind of data processing method, apparatus and system and obtains initial LLVM intermediate code data the method includes being compiled based on LLVM compiler to key agreement algorithm source code data to be processed；The initial LLVM intermediate code data are carried out without the single assignment processing of static state jumped, the intermediate code data that obtain that treated；Conversion process is carried out to treated the intermediate code data, obtains R1CS data.It, can be with simpler efficient realization process of compilation of the cryptographic algorithm source code data to R1CS data using each embodiment of this specification.
Description
Technical field
The present invention relates to computer data processing technology fields, particularly, are related to a kind of data processing method, device and are
System.
Background technique
With the development of block chain technology in recent years, zero-knowledge proof and it can verify that be calculated and widely pay close attention to and make
With.The Zero Knowledge algorithm of mainstream generally can not be directly used in solution computational problem at present, it is necessary to first computational problem be converted into just
True " form " is handled, and this form is called QAP (quadratic arithmetic problem).When specific implementation, one
As need that calculating is first converted to logic circuit, being then then converted into R1CS, (rank-1constraint system, single order is about
Beam system), further QAP is generated using R1CS.
Calculating is usually converted into logic circuit using circuit compiler device at present, but circuit compiler device is generally all corresponding a kind of
Specific source code writes language, supports other high-level languages if necessary, can only develop new compiler again.And current electricity
Road compiler can only realize common grammer, and lack the operations such as error checking, compiling optimization.And advanced cryptography agreement is calculated
Method is usually extremely complex, and the meeting such as missing of grammer limitation and error checking, compiling optimization is so that the operation of total system is accurate
Property and efficiency cannot be guaranteed.Therefore, the art needs a kind of simpler efficient cryptographic data processing method.
Summary of the invention
This specification embodiment is designed to provide a kind of data processing method, apparatus and system, can be simpler
It is efficient to realize process of compilation of the cryptographic algorithm source code data to R1CS data.
This specification provides a kind of data processing method, apparatus and system includes under type realization such as:
A kind of data processing method, comprising:
Key agreement algorithm source code data to be processed are compiled based on LLVM compiler, are obtained among initial LLVM
Code data；
The initial LLVM intermediate code data are carried out without the single assignment processing of static state jumped, the intermediate code that obtains that treated
Data；
Conversion process is carried out to treated the intermediate code data, obtains R1CS data.
This specification provide the method another embodiment in, it is described to the initial LLVM intermediate code data into
Row is without the single assignment processing of static state jumped, comprising:
Function inline and static single assignment processing are carried out to the initial LLVM intermediate code data, obtain the first intermediate yardage
According to；
The first intermediate code data are carried out to eliminate control stream process, obtain treated intermediate code data.
It is described to disappear to the first intermediate code data in another embodiment of the method that this specification provides
Except control stream process, comprising:
Phi instruction in the first intermediate code data is converted into selection instruction, obtains the second intermediate code data；
Skip instruction in the second intermediate code data is removed, treated intermediate code data are obtained.
This specification provide the method another embodiment in, it is described to the initial LLVM intermediate code data into
Line function is inline and static single assignment processing, comprising:
It will be linked in principal function in the subfunction of the initial LLVM intermediate code data, and global variable be put into the master
In function；
Loop unrolling is carried out to the principal function and constant is folded and eliminated, and, by the class and structure in the principal function
The replacement of body variable uses scalar is eliminated；
Switch skip instruction in the principal function is converted into skip instruction, and a plurality of return statement is merged into one
Return statement；
The multiple assignment of same variable in the principal function is converted to the single assignment of multiple variables.
In another embodiment of the method that this specification provides, it is described to treated the intermediate code data into
Row conversion process, comprising:
Based on constraint generating algorithm, to treated, intermediate code data carry out conversion process, obtain R1CS data.
On the other hand, this specification embodiment also provides a kind of data processing equipment, and described device includes:
Data compilation module, for being compiled based on LLVM compiler to key agreement algorithm source code data to be processed
It translates, obtains initial LLVM intermediate code data；
Single assignment processing module, for carrying out the initial LLVM intermediate code data without at the single assignment of static state jumped
Reason obtains treated intermediate code data；
Data conversion module obtains R1CS data for carrying out conversion process to treated the intermediate code data.
In another embodiment for the described device that this specification provides, the list assignment processing module includes:
Single assignment processing unit, for being carried out at function inline and static single assignment to the initial LLVM intermediate code data
Reason obtains the first intermediate code data；
Control stream eliminates unit, control stream process is eliminated for carrying out to the first intermediate code data, after being handled
Intermediate code data.
In another embodiment for the described device that this specification provides, the conversion module includes:
Converting unit, for intermediate code data to carry out conversion process, acquisition to treated based on constraint generating algorithm
R1CS data.
On the other hand, this specification embodiment also provides a kind of data processing equipment, including processor and at storage
Manage device executable instruction memory, when described instruction is executed by the processor realization the following steps are included:
Key agreement algorithm source code data to be processed are compiled based on LLVM compiler, are obtained among initial LLVM
Code data；
The initial LLVM intermediate code data are carried out without the single assignment processing of static state jumped, the intermediate code that obtains that treated
Data；
Conversion process is carried out to treated the intermediate code data, obtains R1CS data.
On the other hand, this specification embodiment also provides a kind of data processing system, and the data compilation system includes extremely
A few processor and the memory for storing computer executable instructions, the processor is realized above-mentioned when executing described instruction
The step of any one embodiment the method.
The data processing method of this specification one or more embodiment offer, apparatus and system, can pass through utilization
LLVM compiler compiles key agreement algorithm source code data to be processed, then, the intermediate yardage that further compiling is obtained
It is handled according to optimizing, and then obtains R1CS data based on the intermediate code data after optimization processing.LLVM compiler can be supported
The algorithm of any language compiles, and the processing such as error checking and code optimization may be implemented, and calculates so as to increase substantially
The high efficiency of simplicity and process of compilation that sources of law code data are write.Meanwhile this specification embodiment is also further to LLVM
The intermediate code data that compiler compiling obtains advanced optimize processing, so that the intermediate code data after optimization are adapted to
R1CS form required for cryptographic algorithm efficient realizes complicated logic calculation at the conversion of R1CS thus simpler
Reason.
Detailed description of the invention
In order to illustrate more clearly of this specification embodiment or technical solution in the prior art, below will to embodiment or
Attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
The some embodiments recorded in this specification, for those of ordinary skill in the art, in not making the creative labor property
Under the premise of, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is a kind of flow diagram for data processing method embodiment that this specification provides；
Fig. 2 is the control flow diagram of the LLVM intermediate code data in one embodiment that this specification provides；
Fig. 3 is the flow diagram of the data processing in another embodiment that this specification provides；
Fig. 4 is a kind of modular structure schematic diagram for data processing equipment embodiment that this specification provides；
Fig. 5 is the schematic configuration diagram according to the server of an exemplary embodiment of this specification.
Specific embodiment
In order to make those skilled in the art more fully understand the technical solution in this specification, below in conjunction with this explanation
Attached drawing in book one or more embodiment carries out the technical solution in this specification one or more embodiment clear, complete
Site preparation description, it is clear that described embodiment is only specification a part of the embodiment, instead of all the embodiments.Based on saying
Bright book one or more embodiment, it is obtained by those of ordinary skill in the art without making creative efforts all
The range of this specification example scheme protection all should belong in other embodiments.
With the development of block chain technology in recent years, zero-knowledge proof and it can verify that be calculated and widely pay close attention to and make
With.The Zero Knowledge algorithm of mainstream generally can not be directly used in solution computational problem at present, it is necessary to first computational problem be converted into just
True " form " is handled, and this form is called QAP (quadratic arithmetic problem).When specific implementation, one
As need that calculating is first converted to logic circuit, being then then converted into R1CS, (rank-1constraint system, single order is about
Beam system), further QAP is generated using R1CS.R1CS is the sequence being made of three Vector Groups (a, b, c), and R1CS has a
Solution vector s, s must satisfy sa*sb-sc=0, and symbol " " indicates the inner product operation of vector.
The mode for being converted into logic circuit will be calculated by generalling use circuit compiler device at present.But the corresponding calculation of circuit compiler device
Method source code writes that language is more single, and the language syntax of support is limited, is not able to satisfy complicated logic calculation, and transfer efficiency compared with
It is low.
Correspondingly, this specification embodiment provides a kind of data processing method, can by using LLVM compiler come
Key agreement algorithm source code data to be processed are compiled, then, the intermediate code data further obtained to compiling optimize place
Reason, and then R1CS data are obtained based on the intermediate code data after optimization processing.LLVM compiler can support the calculation of any language
Method compiling, and the processing such as error checking and code optimization may be implemented, are compiled so as to increase substantially algorithm source code data
The high efficiency of the simplicity and process of compilation write.Meanwhile this specification embodiment also further obtains LLVM compiler compiling
The intermediate code data obtained advanced optimize processing, so that the intermediate code data after optimization are adapted to cryptographic algorithm institute
The logic circuit or R1CS form needed, so that is be simple and efficient realizes complicated logic calculation to logic circuit or turn of R1CS
Change processing.
Fig. 1 is a kind of data processing method embodiment flow diagram that this specification provides.Although this specification
It provides as the following examples or method operating procedure shown in the drawings or apparatus structure, but based on conventional or without creativeness
Labour may include more in the method or device or part merge after less operating procedure or modular unit.?
In the step of there is no necessary causalities in logicality or structure, the modular structure of the execution sequences of these steps or device is not
It is limited to this specification embodiment or execution shown in the drawings sequence or modular structure.The method or modular structure in reality
In device, server or end product in application, can according to embodiment or method shown in the drawings or modular structure into
Row sequence execute or it is parallel execute (such as parallel processor or multiple threads environment, even include distributed treatment,
The implementation environment of server cluster).
Specific one embodiment is as shown in Figure 1, in the one embodiment for the data processing method that this specification provides, institute
The method of stating may include:
S202: being compiled algorithm source code data to be processed based on LLVM compiler, obtains LLVM intermediate code data.
Available key agreement algorithm source code data to be processed.The key agreement algorithm source code data may include
Cryptographic algorithm source code data under arbitrary form, such as be based on zero-knowledge proof, can verify that the corresponding algorithm source code number of calculating
According to.Fig. 2 indicates to calculate the flow diagram for being converted to final zero-knowledge proof in zk-SNARK.Computation table in Fig. 2
Show that calculating, Algebraic Circuit indicate that logic circuit, R1CS indicate single order restraint system, QAP indicates that secondary algorithm is asked
Topic.
The generation language of key agreement algorithm source code data in this specification embodiment is unrestricted, can be according to reality
Need the language form for selecting to generate source code.High-level language C, C++, Java of a variety of mainstreams can such as be used.
It is then possible to based on LLVM (Low Level Virtual Machine, underlying virtual machine) compiler to algorithm source
Code data are compiled.LLVM compiler can be excellent to the morphological analysis of algorithm source code data, syntactic analysis, semantic analysis, execution
The operation such as change, generates initial LLVM intermediate code (LLVM IR) data.
S204: to the initial LLVM intermediate code data progress without the single assignment processing of static state jumped, treated for acquisition
Intermediate code data.
Further initial LLVM intermediate code data can be carried out without the single assignment processing of static state jumped, so that after processing
Intermediate code data format meet the requirement of cryptography form.The single assignment processing of the static state that the nothing jumps may include eliminating just
Multiple assignment, function call in beginning LLVM intermediate code data, sentence such as jump at the operation, and to obtain, the static state that does not jump is single to be assigned
The intermediate code data of value form.
Although can be only by some algorithm source code data conversion at static single assignment form in LLVM compilation process
The single assignment form conversion of the static state of some simple algorithm source code data, the intermediate code data after conversion still contain the more of same variable
Secondary assignment, function call, sentence such as jump at the operation, and these operations are difficult to be converted to the circuit or R1CS of cryptographic algorithm needs
Form.In this specification embodiment, by further eliminate the same variable in initial LLVM intermediate code data multiple assignment,
Function call, sentence such as jump at the operation, and the intermediate code data format that can make that treated more meets the requirement of cryptography form,
Improve the efficiency of subsequent processing.
In one embodiment of this specification, function inline and static state can be carried out to the initial LLVM intermediate code data
Single assignment processing, obtains the first intermediate code data；The first intermediate code data are carried out to eliminate control stream process, are handled
Intermediate code data afterwards.
Function inline processing first can be carried out to initial LLVM intermediate code data, principal function will be linked in all subfunctions
In, to eliminate function call.It is then possible to static single assignment processing is carried out to function inline treated intermediate code data, it will
The multiple assignment of same variable is converted to single assignment, obtains the first intermediate code data.
By will first be linked in principal function in subfunction whole, acquisition only includes the intermediate code data of principal function, then,
On this basis single assignment is converted to the multiple assignment of the same variable in principal function again, can more efficiently and accurately disappeared
Except the multiple assignment of whole in intermediate code data.
It is described that the initial LLVM intermediate code data are carried out in function in one or more embodiment of this specification
Connection and static single assignment processing may include:
It will be linked in principal function in the subfunction of the initial LLVM intermediate code data, and global variable be put into the master
In function；
Loop unrolling is carried out to the principal function and constant is folded and eliminated, and, by the class and structure in the principal function
The replacement of body variable uses scalar is eliminated；
Switch skip instruction in the principal function is converted into skip instruction, and a plurality of return statement is merged into one
Return statement；
The multiple assignment of same variable in the principal function is converted to the single assignment of multiple variables.
It will first can be linked in principal function, be eliminated in intermediate code data in the subfunction of the initial LLVM intermediate code data
Function call.It is then possible to which further all global variables are put into principal function, the multiple assignment of global variable is converted
For the single assignment of multiple variables.
Further, circulation can be unfolded, and constant is folded and is eliminated, preliminary eliminate jumps.The constant folding
It is folded to eliminate as constant is calculated evaluation, expression formula is replaced with value, is put into constant table.Mark can be used to class and structural body variable
Amount replacement is eliminated.Switch sentence further can be converted into skip instruction (Br sentence), by a plurality of return statement (Return
Sentence) merge into a Return sentence.Later, memory read-write instruction further can also be also converted into static single assignment shape
Formula.
By above-mentioned processing, more accurate can thoroughly realize to the single assignment processing of the static state of intermediate code data.Simultaneously
It can also tentatively eliminate and jump processing.Further, it is jumped by the way that the switch sentence that control node circulates tentatively is converted to Br
GO TO statement can further facilitate and subsequent jump Processing for removing.
After completing above-mentioned processing, intermediate code data can be converted following form: only one principal function, be had in principal function
Multiple basic blocks.Correspondingly, the termination instruction of the last one basic block is Return sentence, the termination instruction of other basic blocks is
Br jump instruction, correspondingly, Br jump instruction can be have ready conditions jump instruction or unconditional jump instruction.Its in basic block
He, which instructs, only has arithmetical operation, digitwise operation, comparison operation, selection instruction (Select instruction) and Phi instruction.
The Br instruction may include have ready conditions jump instruction or unconditional jump instruction, and the jump instruction of having ready conditions can
To refer to the instruction for jumping to default node by present node under the conditions of meeting certain predetermined, the unconditional jump, which instructs, is
Refer to the instruction for jumping to default node by present node in the case where no strings attached.
Phi instruction for static single assignment form for data in for determining the node executed before present node
Instruction, with utilize before execute node value carry out present node processing.The multiple assignment of same variable is converted
After the single assignment form of multiple variables, multiple nodes may be corresponding with before a node, it can be by Phi instruction come really
The corresponding previous node of present node in fixed control stream, to carry out the processing of present node using the value of the previous node.
It is then possible to further carry out eliminating control stream process to the first intermediate code data, the first intermediate code is eliminated
Phi sentence and skip instruction in data are converted to the single assignment form of the static state not jumped, so that yardage among treated
According to the circuit or R1CS form for being used directly for cryptography agreement needs.
In one embodiment of this specification, the Phi in the first intermediate code data further can be instructed into conversion
For selection instruction, the second intermediate code data are obtained；
Skip instruction in the second intermediate code data is removed, treated intermediate code data are obtained.
For any one Phi instruction in the first intermediate code data, several Select instructions can be converted into,
To eliminate Phi instruction, after eliminating Phi instruction, execution sequence and mode between each node can be instructed directly by Select
It is attached.Correspondingly, no longer need to determine execution sequence and mode by jump instruction in entire intermediate code data implementation procedure,
Jump instruction between each node is removed.To which using the scheme of above-described embodiment, what is be simple and efficient realizes centre
The Processing for removing of jump instruction in code data, obtains the intermediate code data of the single assignment form of the static state not jumped.
This specification provide an application scenarios example in, can by following step to initial LLVM intermediate code data into
Row processing, to obtain the intermediate code data for the single assignment form of static state not jumped:
1) function call: all function inlines into principal function；
2) global variable: after all function inlines, all global variables are put into principal function；
3) it recycles: being folded and eliminated using loop unrolling and constant；
4) it class and structural body variable: is eliminated using scalar replacement；
5) switch skip instruction: it is degraded to Br skip instruction；
6) a plurality of Return sentence: a Return sentence is merged into；
7) memory read-write: SSA form is converted to；
8) all basic blocks control stream: are merged into a basic block.
Step 1) -7) it can implement with reference to above scheme, it is not described herein.Fig. 2 indicates to pass through above-mentioned steps 1) -7) at
The corresponding control flow diagram of intermediate code data after reason is described further control stream Processing for removing with reference to Fig. 2.It is assumed that
By step 1) -7) obtain the first intermediate code data are as follows:
As shown in Figure 2, by taking basic block bb4 as an example, the basic block before bb4 can have bb2 and bb3, correspondingly, bb4 pairs
Include Phi instruction in the control flow data answered:: %r4=phi i32 [42, %bb2], [43, %bb3].If control stream
Bb4 is jumped to from basic block bb2, %r4 is assigned 42, if control stream jumps to bb4 from bb3, %r4 is assigned position 43.
So that the pending value of bb4 is determined by Phi instruction, if the value of %r4 is number of 42, the bb4 based on basic block bb2
According to subsequent processing is carried out, if the value of %r4 is data progress subsequent processing of 43, the bb4 based on basic block bb3.
Similarly, the basic block before basic block bb6 also includes multiple, is also corresponding with Phi instruction, the %r6 in Phi instruction
1,2, %r4 or 5 can be assigned according to previous basic block.
For above-mentioned control stream, can carry out eliminating Br instruction and Phi instruction by following manner:
Step 1: each Phi instruction is converted to several Select instructions.
It is illustrated by taking the basic block bb4 instructed containing Phi as an example:
Firstly, finding the basic block bb4 containing Phi instruction, and control node (preceding obligatory nodes) bb0 of bb4 is found, from
Bb4 starts reversely to traverse, and finds basic block bb0, bb1, bb2, bb3 of all reachable bb4.
It executes operations described below and the corresponding Phi instruction of bb4 is converted into Select instruction:
Phi instruction is substituted for S, and removes phi instruction
In above-mentioned operational process:
InsertSelect (bb3, phi) returns to the respective value 43 of bb3 in phi sentence,
InsertSelect (bb2, phi) returns to 42,
InsertSelect (bb1, phi) calls InsertSelect (bb2, phi), returns to 42,
InsertSelect (bb0, phi) calls InsertSelect (bb1, phi) to obtain 42, calls InsertSelect
(bb3, phi) obtains 43, creates Select sentence Select (%cond0,42,43), and replace phi sentence.
After the completion of processing, the corresponding phi sentence of bb4 " %r4=phi i32 [42, %bb2], [43, %bb3] " is replaced
For Select sentence " %r4.bb0=select i1%cond0, i32 42, i32 43 ".
Basic block bb6 is also handled according to aforesaid way, after the completion of execution, corresponding intermediate code data are as follows:
Finally, all Br sentences are removed, and other sentences are moved on in a basic block, is completed at control stream elimination
Reason.Correspondingly, the intermediate code data completed after control stream Processing for removing become following form:
In this specification above-described embodiment, by advanced optimizing processing to LLVM intermediate code data, it can make
The intermediate code data finally obtained are more suitable for the needs of cryptography protocol data processing, meanwhile, by above-mentioned optimization processing, also
It can be further improved the simplicity and efficiency of subsequent processing.
S206: conversion process is carried out to treated the intermediate code data, obtains R1CS data.
Treated intermediate code data conversion can be based further on and obtain logic circuit data or R1CS form
Data.In some embodiments, can first by treated, intermediate code data are converted to logic circuit data, then, then into one
Step is converted to the data of R1CS form.
Fig. 3 indicates that the scheme that above-mentioned each embodiment provides is based on LLVM compiler to cryptography computational algorithm source code data
Be converted to the flow chart of R1CS data.As shown in Figure 3, it is preferred that, can be based on constraint life in one embodiment of this specification
Conversion process is carried out to treated the intermediate code data at algorithm, obtains R1CS data.
It is described that carry out conversion process to treated the intermediate code data based on constraint generating algorithm may include: by
Between each operational order in code data handled by way of increasing constraint, to be configured to only with addition and multiplication table
The form shown.By way of being directly configured to only be indicated with addition and multiplication by the instruction in intermediate code data, R1CS is obtained
The data of form, can be to avoid the tedious steps for utilizing logic circuit data to obtain R1CS data, and then improve data processing
Efficiency and simplicity.
Below by taking some basic LLVM instructions as an example, illustrate how to be converted to LLVM IR only with addition and multiplication table
The R1CS shown:
1.Packing constraint
In order to handle digitwise operation, the variable a multidigit is needed to be launched into multiple one variable, or multiple
One variable is merged into the variable of multidigit, can guarantee that multiple variables are the step-by-step exhibitions an of variable using Packing constraint
It opens, it may be assumed that
2iIt can be indicated with multiplication or directly with addition, in addition constrain each ciAll it is 1 or 0, then can guarantees c and every
A ciRelationship.
Wherein, the Packing is constrained to and one n numbers is splitted into n 1 number, or by n 1 array
Synthesize the constraint processing mode of one n numbers.
Compare 2. being greater than
%c=icmp sgt i32%a, %b
B-a is calculated, the sign bit (highest order) of difference is obtained using Packing；
When a is greater than b, sign bit is equal to 1；
When a is not more than b, sign bit is equal to 0.
Compare 3. being more than or equal to
%c=icmp sge i32%a, %b
Compared using being greater than, result is stored in gt；
Compared using being equal to, result is stored in eq；
Along with constraint.
4.Add instruction
%c=add i32%a, i32%b
It can be expressed as following constraint:
C=(a+b) × 1.
5.Mul instruction
%c=mul i32%a, i32%b
It can be expressed as following constraint:
C=a × b.
6.Sub instruction
%c=sub i32%a, i32%b
It can be expressed as following constraint:
C=(a-b) × 1.
7.Div instruction
%c=div i32%a, i32%b
It can be expressed as following constraint:
Wherein, d is remainder, and c is quotient, is greater than and is more than or equal to constraint and carry out with reference to postorder content.
8.Rem instruction
%d=rem i32%a, i32%b
It can be expressed as following constraint:
Wherein, d is remainder, and c is quotient, is greater than and is more than or equal to constraint and carry out with reference to postorder content.
Compare 9. being equal to
%c=icmp eq i32%a, %b
It can be expressed as following constraint:
It as a=b, is constrained according to first, c can be arbitrary number, so Article 2 is needed to constrain, aux is set as
Arbitrary value can be constrained c and be necessary for 1；
It as a ≠ b, is constrained according to first, c is necessarily equal to the multiplicative inverse that 0, aux is set as a-b, enables the second treaty
Beam is also set up.
10. not equal to comparing
%c=icmp ne i32%a, %b
Addition constraint:
It as a=b, is constrained according to first, c can be any number, constrain according to Article 2, and aux can be set to appoint
Meaning value, c are necessary for 0；
It as a ≠ b, is constrained according to first, c is necessarily equal to the multiplicative inverse that 1, aux is set as a-b, enables the second treaty
Beam is also set up.
11.Select instruction
%c=select i1%cond, i32%a, i32%b
Wherein, %cond only has 1, and only 0 or 1 two kind of value；
Select instruction can be converted to following constraint type:
C=cond × a+ (1+ (- 1 × cond)) × b.
12.And instruction
%c=and i32%a, %b
And is step-by-step and operation, needs that 32 a and b are splitted into 32 variables respectively with Packing, to each pair of variable
Progress and operation, and constrain ai、bi、ciRelationship, then with Packing 32 ciIt is merged into c variable；
The constraint of each variable are as follows:
ci=ai+bi。
13.Or instruction
%c=or i32%a, %b
Or is step-by-step or operation, needs that 32 a and b are splitted into 32 variables respectively with Packing, to each pair of variable into
Capable and operation, and constrain ai、bi、ciRelationship, then with Packing 32 ciIt is merged into c variable；
The constraint of each variable are as follows:
ai×bi=ai+bi-ci。
14.xor instruction
%c=xor i32%a, %b
Xor is step-by-step XOR operation, needs that 32 a and b are splitted into 32 variables respectively with Packing, to each pair of change
Amount carries out and operation, and constrains ai、bi、ciRelationship, then with Packing 32 ciIt is merged into c variable；
Being constrained to using constraint is not equal to for each variable is realized.
The above-mentioned each embodiment of this specification, by the volume for carrying out cryptography computational algorithm source code based on LLVM compiler
It translates, language form is no longer limited when algorithm source code can be made to write, and developer can select a variety of mainstreams according to self-demand
Development language carry out respective algorithms and write, improve the simplicity that algorithm is write.
Meanwhile for the complexity because of cryptographic algorithm, the intermediate code data after LLVM compiler direct compilation may nothing
Method is directly changed into the problem of logic circuit or R1CS data, in this specification embodiment also further to intermediate code data into
Related optimization processing is gone.To, the scheme provided using each embodiment of this specification, the realization password that can be simple and efficient
Learn process of compilation of the algorithm source code data to R1CS data.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Specifically it is referred to
The description of aforementioned relevant treatment related embodiment, does not do repeat one by one herein.
It is above-mentioned that this specification specific embodiment is described.Other embodiments are in the scope of the appended claims
It is interior.In some cases, the movement recorded in detail in the claims or step can be come according to the sequence being different from embodiment
It executes and desired result still may be implemented.In addition, process depicted in the drawing not necessarily require show it is specific suitable
Sequence or consecutive order are just able to achieve desired result.In some embodiments, multitasking and parallel processing be also can
With or may be advantageous.
The data processing method that this specification one or more embodiment provides, can be by being compiled using LLVM compiler
Key agreement algorithm source code data to be processed are translated, then, the intermediate code data further obtained to compiling optimize processing,
And then R1CS data are obtained based on the intermediate code data after optimization processing.LLVM compiler can support the algorithm of any language to compile
It the processing such as translates, and error checking and code optimization may be implemented, write so as to increasing substantially algorithm source code data
The high efficiency of simplicity and process of compilation.Meanwhile this specification embodiment is also further to LLVM compiler compiling acquisition
Intermediate code data advanced optimize processing, so that the intermediate code data after optimization are adapted to required for cryptographic algorithm
R1CS form, thus conversion process of the complicated logic calculation of the realization being simple and efficient to R1CS.
Based on data processing method described above, this specification one or more embodiment also provides a kind of data processing
Device.The device may include the system for having used this specification embodiment the method, software (application), module, group
Part, server etc. simultaneously combine the necessary device for implementing hardware.Based on same innovation thinking, this specification embodiment provide one
Device in a or multiple embodiments is as described in the following examples.The implementation and method phase solved the problems, such as due to device
Seemingly, therefore the implementation of the specific device of this specification embodiment may refer to the implementation of preceding method, and overlaps will not be repeated.
Used below, the combination of the software and/or hardware of predetermined function may be implemented in term " unit " or " module ".Although with
Device described in lower embodiment is preferably realized with software, but the combined realization of hardware or software and hardware
It may and be contemplated.Specifically, Fig. 4 indicates that a kind of modular structure for data processing equipment embodiment that specification provides is shown
It is intended to, as shown in figure 4, the apparatus may include:
Data compilation module 102 can be used for based on LLVM compiler to key agreement algorithm source code data to be processed
It is compiled, obtains initial LLVM intermediate code data；
Single assignment processing module 104 can be used for carrying out the initial LLVM intermediate code data single without the static state jumped
Assignment processing, obtains treated intermediate code data；
Data conversion module 106 can be used for carrying out conversion process to treated the intermediate code data, obtain R1CS
Data.
In one embodiment of this specification, the list assignment processing module 104 may include:
Single assignment processing unit can be used for carrying out the initial LLVM intermediate code data function inline and static single tax
Value processing, obtains the first intermediate code data；
Control stream eliminates unit, can be used for carrying out the first intermediate code data eliminating control stream process, at acquisition
Intermediate code data after reason.
In one embodiment of this specification, the control stream eliminates unit and may include:
Conversion subunit is instructed, can be used for the Phi instruction in the first intermediate code data being converted to selection instruction,
Obtain the second intermediate code data；
Sentence merges subelement, can be used for removing the skip instruction in the second intermediate code data, be handled
Intermediate code data afterwards.
In one embodiment of this specification, the conversion module 106 may include:
Converting unit, can be used for being based on constraint generating algorithm, intermediate code data carry out conversion process to treated, obtain
Obtain R1CS data.
It should be noted that device described above can also include other embodiment party according to the description of embodiment of the method
Formula.Concrete implementation mode is referred to the description of related method embodiment, does not repeat one by one herein.
The data processing equipment that this specification one or more embodiment provides, can be by being compiled using LLVM compiler
Key agreement algorithm source code data to be processed are translated, then, the intermediate code data further obtained to compiling optimize processing,
And then R1CS data are obtained based on the intermediate code data after optimization processing.LLVM compiler can support the algorithm of any language to compile
It the processing such as translates, and error checking and code optimization may be implemented, write so as to increasing substantially algorithm source code data
The high efficiency of simplicity and process of compilation.Meanwhile this specification embodiment is also further to LLVM compiler compiling acquisition
Intermediate code data advanced optimize processing, so that the intermediate code data after optimization are adapted to required for cryptographic algorithm
R1CS form, thus conversion of the complicated logic calculation of the realization being simple and efficient to R1CS.
Method or apparatus described in above-described embodiment that this specification provides can realize that business is patrolled by computer program
It collects and records on a storage medium, the storage medium can be read and be executed with computer, realize this specification embodiment institute
The effect of description scheme.Therefore, this specification also provides a kind of data processing equipment, including processor and storage processor can be held
Row instruction memory, when described instruction is executed by the processor realization the following steps are included:
Key agreement algorithm source code data to be processed are compiled based on LLVM compiler, are obtained among initial LLVM
Code data；
The initial LLVM intermediate code data are carried out without the single assignment processing of static state jumped, the intermediate code that obtains that treated
Data；
Conversion process is carried out to treated the intermediate code data, obtains R1CS data.
The storage medium may include the physical unit for storing information, usually by after information digitalization again with benefit
The media of the modes such as electricity consumption, magnetic or optics are stored.It may include: that letter is stored in the way of electric energy that the storage medium, which has,
The device of breath such as, various memory, such as RAM, ROM；The device of information is stored in the way of magnetic energy such as, hard disk, floppy disk, magnetic
Band, core memory, magnetic bubble memory, USB flash disk；Using optical mode storage information device such as, CD or DVD.Certainly, there are also it
Readable storage medium storing program for executing of his mode, such as quantum memory, graphene memory etc..
It should be noted that equipment described above can also include other embodiment party according to the description of embodiment of the method
Formula.Concrete implementation mode is referred to the description of related method embodiment, does not repeat one by one herein.
Embodiment of the method provided by this specification embodiment can mobile terminal, terminal, server or
It is executed in similar arithmetic unit.For running on the server, Fig. 5 is taken using the data processing of this specification embodiment
The hardware block diagram of business device.As shown in figure 5, server 10 may include one or more (only showing one in figure) processors
20 (processing units that processor 20 can include but is not limited to Micro-processor MCV or programmable logic device FPGA etc.) are used for
The memory 30 of storing data and transmission module 40 for communication function.This neighborhood those of ordinary skill is appreciated that figure
Structure shown in 5 is only to illustrate, and does not cause to limit to the structure of above-mentioned electronic device.For example, server 10 may also include
The more or less component than shown in Fig. 5, such as can also include other processing hardware, as database or multistage are slow
It deposits, GPU, or with the configuration different from shown in Fig. 5.
Memory 30 can be used for storing the software program and module of application software, such as the searcher in the embodiment of the present invention
Corresponding program instruction/the module of method, the software program and module that processor 20 is stored in memory 30 by operation, thus
Perform various functions application and data processing.Memory 30 may include high speed random access memory, may also include non-volatile deposit
Reservoir, such as one or more magnetic storage device, flash memory or other non-volatile solid state memories.In some instances,
Memory 30 can further comprise the memory remotely located relative to processor 20, these remote memories can pass through network
It is connected to terminal.The example of above-mentioned network includes but is not limited to internet, intranet, local area network, mobile communication
Net and combinations thereof.
Transmission module 40 is used to that data to be received or sent via a network.Above-mentioned network specific example may include meter
The wireless network that the communication providers of calculation machine terminal provide.In an example, transmission module 40 includes a network adapter
(Network Interface Controller, NIC), can be connected by base station with other network equipments so as to interconnection
Net is communicated.In an example, transmission module 40 can be radio frequency (Radio Frequency, RF) module, be used to lead to
Wireless mode is crossed to be communicated with internet.
Data processing equipment described in above-described embodiment, can be by compiling password to be processed using LLVM compiler
Protocol algorithm source code data, then, the intermediate code data further obtained to compiling optimize processing, and then based at optimization
Intermediate code data after reason obtain R1CS data.LLVM compiler can support the algorithm of any language to compile, and may be implemented
The processing such as error checking and code optimization, so as to increase substantially the simplicity and compiling that algorithm source code data are write
The high efficiency of processing.Meanwhile the intermediate code data that this specification embodiment also further obtains LLVM compiler compiling carry out
Processing is advanced optimized, so that the intermediate code data after optimization are adapted to R1CS form required for cryptographic algorithm, from
And what is be simple and efficient realizes conversion process of the complicated logic calculation to R1CS.
This specification also provides a kind of data processing system, and the system can be individual data processing system, can also
To apply in a variety of computer data processing systems.The system can be individual server, also may include using
The server cluster of one or more the methods of this specification or one or more embodiment devices, system (including point
Cloth system), software (application), practical operation device, logic gates device, quantum computer etc. and combine necessary implementation
The terminal installation of hardware.The data processing system may include at least one processor and storage computer executable instructions
Memory, the processor realizes the step of method described in above-mentioned any one or multiple embodiments when executing described instruction
Suddenly.
It should be noted that system described above can also include others according to the description of method or Installation practice
Embodiment, concrete implementation mode are referred to the description of related method embodiment, do not repeat one by one herein.
Data processing system described in above-described embodiment, can be by compiling password to be processed using LLVM compiler
Protocol algorithm source code data, then, the intermediate code data further obtained to compiling optimize processing, and then based at optimization
Intermediate code data after reason obtain R1CS data.LLVM compiler can support the algorithm of any language to compile, and may be implemented
The processing such as error checking and code optimization, so as to increase substantially the simplicity and compiling that algorithm source code data are write
The high efficiency of processing.Meanwhile the intermediate code data that this specification embodiment also further obtains LLVM compiler compiling carry out
Processing is advanced optimized, so that the intermediate code data after optimization are adapted to R1CS form required for cryptographic algorithm, from
And what is be simple and efficient realizes conversion process of the complicated logic calculation to R1CS.
It should be noted that this specification device or system described above according to the description of related method embodiment also
It may include other embodiments, concrete implementation mode is referred to the description of embodiment of the method, does not go to live in the household of one's in-laws on getting married one by one herein
It states.All the embodiments in this specification are described in a progressive manner, and same and similar part is mutual between each embodiment
Mutually referring to each embodiment focuses on the differences from other embodiments.Especially for hardware+program
For class, storage medium+program embodiment, since it is substantially similar to the method embodiment, so be described relatively simple, it is related
Place illustrates referring to the part of embodiment of the method.
Although the loop unrolling mentioned in this specification embodiment content, constant fold eliminate etc. obtain, definition, interaction,
The operations such as calculating, judgement and data description, still, this specification embodiment is not limited to comply with standard data mould
Situation described in type/template or this specification embodiment.Certain professional standards are retouched using customized mode or embodiment
On the practice processes stated embodiment modified slightly also may be implemented above-described embodiment it is identical, it is equivalent or it is close or deformation
Afterwards it is anticipated that implementation result.Using acquisitions such as these modifications or deformed data acquisition, storage, judgement, processing modes
Embodiment still may belong within the scope of the optional embodiment of this specification.
It is above-mentioned that this specification specific embodiment is described.Other embodiments are in the scope of the appended claims
It is interior.In some cases, the movement recorded in detail in the claims or step can be come according to the sequence being different from embodiment
It executes and desired result still may be implemented.In addition, process depicted in the drawing not necessarily require show it is specific suitable
Sequence or consecutive order are just able to achieve desired result.In some embodiments, multitasking and parallel processing be also can
With or may be advantageous.
System, device, module or the unit that above-described embodiment illustrates can specifically realize by computer chip or entity,
Or it is realized by the product with certain function.It is a kind of typically to realize that equipment is computer.Specifically, computer for example may be used
Think personal computer, laptop computer, vehicle-mounted human-computer interaction device, cellular phone, camera phone, smart phone, individual
Digital assistants, media player, navigation equipment, electronic mail equipment, game console, tablet computer, wearable device or
The combination of any equipment in these equipment of person.
For convenience of description, it is divided into various modules when description apparatus above with function to describe respectively.Certainly, implementing this
The function of each module can be realized in the same or multiple software and or hardware when specification one or more, it can also be with
The module for realizing same function is realized by the combination of multiple submodule or subelement etc..Installation practice described above is only
It is only illustrative, for example, in addition the division of the unit, only a kind of logical function partition can have in actual implementation
Division mode, such as multiple units or components can be combined or can be integrated into another system or some features can be with
Ignore, or does not execute.Another point, shown or discussed mutual coupling, direct-coupling or communication connection can be logical
Some interfaces are crossed, the indirect coupling or communication connection of device or unit can be electrical property, mechanical or other forms.
It is also known in the art that other than realizing controller in a manner of pure computer readable program code, it is complete
Entirely can by by method and step carry out programming in logic come so that controller with logic gate, switch, specific integrated circuit, programmable
Logic controller realizes identical function with the form for being embedded in microcontroller etc..Therefore this controller is considered one kind
Hardware component, and the structure that the device for realizing various functions that its inside includes can also be considered as in hardware component.Or
Person even, can will be considered as realizing the device of various functions either the software module of implementation method can be hardware again
Structure in component.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
In a typical configuration, calculating equipment includes one or more processors (CPU), input/output interface, net
Network interface and memory.
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
It include so that the process, method, commodity or the equipment that include a series of elements not only include those elements, but also to wrap
Include other elements that are not explicitly listed, or further include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including described want
There is also other identical elements in the process, method or equipment of element.
It will be understood by those skilled in the art that this specification one or more embodiment can provide as method, system or calculating
Machine program product.Therefore, this specification one or more embodiment can be used complete hardware embodiment, complete software embodiment or
The form of embodiment combining software and hardware aspects.Moreover, this specification one or more embodiment can be used at one or
It is multiple wherein include computer usable program code computer-usable storage medium (including but not limited to magnetic disk storage,
CD-ROM, optical memory etc.) on the form of computer program product implemented.
This specification one or more embodiment can computer executable instructions it is general on
It hereinafter describes, such as program module.Generally, program module includes executing particular task or realization particular abstract data type
Routine, programs, objects, component, data structure etc..This this specification one can also be practiced in a distributed computing environment
Or multiple embodiments, in these distributed computing environments, by being held by the connected remote processing devices of communication network
Row task.In a distributed computing environment, program module can be located at the local and remote computer including storage equipment
In storage medium.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for system reality
For applying example, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring to embodiment of the method
Part explanation.In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ",
The description of " specific example " or " some examples " etc. means specific features described in conjunction with this embodiment or example, structure, material
Or feature is contained at least one embodiment or example of this specification.In the present specification, to the signal of above-mentioned term
Property statement must not necessarily be directed to identical embodiment or example.Moreover, specific features, structure, material or the spy of description
Point may be combined in any suitable manner in any one or more of the embodiments or examples.In addition, without conflicting with each other,
Those skilled in the art can be by different embodiments or examples described in this specification and different embodiments or examples
Feature is combined.
The foregoing is merely the embodiments of this specification, are not limited to this specification.For art technology
For personnel, this specification can have various modifications and variations.It is all made any within the spirit and principle of this specification
Modification, equivalent replacement, improvement etc., should be included within the scope of the claims of this specification.
Claims (10)
1. a kind of data processing method characterized by comprising
Key agreement algorithm source code data to be processed are compiled based on LLVM compiler, obtain yardage among initial LLVM
According to；
The initial LLVM intermediate code data are carried out without the single assignment processing of static state jumped, the intermediate yardage that obtains that treated
According to；
Conversion process is carried out to treated the intermediate code data, obtains R1CS data.
2. the method according to claim 1, wherein described carry out without jump the initial LLVM intermediate code data
The single assignment processing of the static state turned, comprising:
Function inline and static single assignment processing are carried out to the initial LLVM intermediate code data, obtain the first intermediate code data；
The first intermediate code data are carried out to eliminate control stream process, obtain treated intermediate code data.
3. according to the method described in claim 2, it is characterized in that, described carry out elimination control to the first intermediate code data
Stream process, comprising:
Phi instruction in the first intermediate code data is converted into selection instruction, obtains the second intermediate code data；
Skip instruction in the second intermediate code data is removed, treated intermediate code data are obtained.
4. according to the method described in claim 2, it is characterized in that, described carry out function to the initial LLVM intermediate code data
Inline and static single assignment processing, comprising:
It will be linked in principal function in the subfunction of the initial LLVM intermediate code data, and global variable be put into the principal function
In；
Loop unrolling is carried out to the principal function and constant is folded and eliminated, and, by the class and structural body change in the principal function
Amount is eliminated using scalar replacement；
Switch skip instruction in the principal function is converted into skip instruction, and a plurality of return statement is merged into one and is returned
Return sentence；
The multiple assignment of same variable in the principal function is converted to the single assignment of multiple variables.
5. method according to claim 1-4, which is characterized in that described to treated the intermediate code data
Carry out conversion process, comprising:
Based on constraint generating algorithm, to treated, intermediate code data carry out conversion process, obtain R1CS data.
6. a kind of data processing equipment, which is characterized in that described device includes:
Data compilation module is obtained for being compiled based on LLVM compiler to key agreement algorithm source code data to be processed
Obtain initial LLVM intermediate code data；
Single assignment processing module, for obtain without the single assignment processing of static state jumped to the initial LLVM intermediate code data
Treated intermediate code data；
Data conversion module obtains R1CS data for carrying out conversion process to treated the intermediate code data.
7. device according to claim 6, which is characterized in that it is described list assignment processing module include:
Single assignment processing unit, for carrying out function inline and static single assignment processing to the initial LLVM intermediate code data,
Obtain the first intermediate code data；
Control stream eliminates unit, eliminates control stream process for carrying out to the first intermediate code data, obtains during treated
Between code data.
8. device according to claim 6, which is characterized in that the conversion module includes:
Converting unit, for intermediate code data to carry out conversion process, acquisition R1CS number to treated based on constraint generating algorithm
According to.
9. a kind of data processing equipment, which is characterized in that including processor and for the storage of storage processor executable instruction
Device, when described instruction is executed by the processor realize the following steps are included:
Key agreement algorithm source code data to be processed are compiled based on LLVM compiler, obtain yardage among initial LLVM
According to；
The initial LLVM intermediate code data are carried out without the single assignment processing of static state jumped, the intermediate yardage that obtains that treated
According to；
Conversion process is carried out to treated the intermediate code data, obtains R1CS data.
10. a kind of data processing system, which is characterized in that the data compilation system includes at least one processor and storage
The memory of computer executable instructions, the processor realize any one of the claim 1-5 institute when executing described instruction
The step of stating method.
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