CN110209065B - MMC power module level fault and protection logic dynamic simulation system and method - Google Patents
MMC power module level fault and protection logic dynamic simulation system and method Download PDFInfo
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- CN110209065B CN110209065B CN201910363630.8A CN201910363630A CN110209065B CN 110209065 B CN110209065 B CN 110209065B CN 201910363630 A CN201910363630 A CN 201910363630A CN 110209065 B CN110209065 B CN 110209065B
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Abstract
The invention discloses an MMC power module level fault and protection logic dynamic simulation system, which comprises a first simulation module, a second simulation module, an MMC valve control device and a control protection device, wherein the first simulation module is connected with the second simulation module through a pipeline; the first simulation module comprises a first logic processor and an MMC valve simulator, and the MMC valve simulator is used for simulating an MMC valve; the second simulation module comprises a second logic processor and an MMC external circuit simulator, and the MMC external circuit simulator is used for simulating an MMC external circuit; the first logic processor establishes a power module level fault and protection logic simulation rule; establishing a power module level fault and protection logic information base, establishing a processing logic information base and defining a fault control word grammar; the second logical processor establishes power module level fault and protection action trigger logic. The system disclosed by the invention can solve the problems that the prior art can only simply simulate, and has poor universality and precision. The embodiment of the invention also discloses an MMC power module level fault and protection logic simulation method and a storage medium.
Description
Technical Field
The invention relates to the technical field of real-time simulation, in particular to a dynamic simulation system and method for faults and protection logic of an MMC power module level.
Background
Modular Multilevel Converters (MMC) have the advantages of modular design, strong expansibility, flexible power four-quadrant operation, less alternating voltage harmonic waves, small occupied area and the like, and are widely researched and utilized in the fields of asynchronous interconnection of alternating current power grids, wind power plant access and the like in recent years. The established south-Australia multi-terminal flexible direct power transmission engineering, Yunnan asynchronous networking engineering, Shanghai south-Hui flexible direct engineering, Zhoushan five-terminal flexible direct engineering, Xiamen flexible direct engineering, and the constructed Udongde power station power transmission Guangdong-Guangxi extra-high voltage multi-terminal direct current demonstration engineering and Zhangbei flexible direct power grid engineering all adopt MMC topological structures.
The power module is a core composition unit of the MMC and comprises power transmission devices such as an IGBT, an anti-parallel diode and a capacitor, a bypass switch, a bypass thyristor, a self-energy-taking power supply, a voltage sensor, a control optical fiber and other control protection auxiliary devices. The state of the power module directly affects the safe and reliable operation of the modular multilevel converter and even the whole flexible direct current transmission device, so that the fault characteristics of the power module of the modular multilevel converter need to be modeled and analyzed, and the safe and reliable operation of the flexible direct current transmission device is guaranteed.
In the process of implementing the invention, the following technical problems are found in the prior art:
the simulated fault types are limited, the existing scheme can only simply simulate the power module level IGBT fault and the bypass switch fault, and can not simulate the capacitance voltage sampling abnormity, the uplink and downlink communication fault and the like; the universality is poor, the existing scheme is only suitable for certain specific working conditions, and the fault dynamic simulation logic cannot be built according to the actual control protection strategy of the power module level; the accuracy is poor.
Disclosure of Invention
The embodiment of the invention provides a dynamic simulation system, a dynamic simulation method and a dynamic simulation storage medium for MMC power module level faults and protection logic, which can effectively solve the problems of simple simulation, poor universality and poor precision in the prior art.
The embodiment of the invention provides an MMC power module level fault and protection logic dynamic simulation system, which comprises a first simulation module, a second simulation module, an MMC valve control device and a control protection device, wherein the first simulation module is connected with the second simulation module through a first pipeline;
the first simulation module comprises a first logic processor and an MMC valve simulator, and the MMC valve simulator is used for simulating an MMC valve;
the second simulation module comprises a second logic processor and an MMC external circuit simulator, and the MMC external circuit simulator is used for simulating an MMC external circuit;
the first logic processor establishes a power module level fault and protection logic simulation rule; establishing a power module level fault and protection logic simulation rule, specifically establishing a power module level fault and protection logic information base, establishing a processing logic information base and a mapping relation corresponding to the processing logic information base and the processing logic information base, and defining a fault control word grammar;
the second logic processor establishes power module level fault and protection action trigger logic;
in a simulation period, the second logic processor determines a fault module, generates a fault control word according to the syntax of the fault control word and sends the fault control word to the first logic processor;
the MMC valve control device generates a trigger pulse according to a received modulation wave signal for controlling the protection device and sends the trigger pulse to the first logic processor;
the first logic processor carries out comprehensive judgment and decoding on the received fault control word and the trigger pulse, and generates an actual trigger control word according to the power module level fault and protection logic simulation rule; generating a substitute network according to the actual trigger control word; obtaining MMC valve injection current, each bridge arm current, power module capacitance voltage and state information according to the substitution network, sending the MMC valve injection current to the MMC external circuit simulator, and sending each bridge arm current, power module capacitance voltage and state information to the MMC valve control device;
the MMC external circuit simulator obtains MMC external circuit injection current according to the received MMC valve injection current; the MMC valve control device receives the current of each bridge arm, the capacitance voltage of the power module and state information, and sequences the current of each bridge arm and the capacitance voltage of the power module;
and the MMC external circuit simulator sends the MMC external circuit injection current to the MMC valve simulator to enter the next simulation period.
As an improvement of the above scheme, the first simulation module is an FPGA, and the second simulation module is an RTDS.
The embodiment of the invention correspondingly provides an MMC power module level fault and protection logic simulation method, which is applied to an MMC power module level fault and protection dynamic simulation system, wherein the system comprises a first simulation module, a second simulation module, an MMC valve control device and a control protection device; the method comprises the following steps:
establishing a power module level fault and protection logic simulation rule in the first logic processor; establishing a power module level fault and protection logic simulation rule, specifically establishing a power module level fault and protection logic information base, establishing a processing logic information base and a mapping relation corresponding to the processing logic information base and the processing logic information base, and defining a fault control word grammar;
establishing power module level fault and protection action triggering logic in the second logical processor;
in a simulation period, the second logic processor determines a fault module, generates a fault control word according to the syntax of the fault control word and sends the fault control word to the first logic processor;
the MMC valve control device generates a trigger pulse according to a received modulation wave signal for controlling the protection device and sends the trigger pulse to the first logic processor;
the first logic processor carries out comprehensive judgment and decoding on the received fault control word and the trigger pulse, and generates an actual trigger control word according to the power module level fault and protection logic simulation rule; generating a substitute network according to the actual trigger control word; obtaining MMC valve injection current, each bridge arm current, power module capacitance voltage and state information according to the substitution network, sending the MMC valve injection current to the MMC external circuit simulator, and sending each bridge arm current, power module capacitance voltage and state information to the MMC valve control device;
the MMC external circuit simulator obtains MMC external circuit injection current according to the received MMC valve injection current; the MMC valve control device receives the current of each bridge arm, the capacitance voltage of the power module and state information, and sequences the current of each bridge arm and the capacitance voltage of the power module;
and the MMC external circuit simulator sends the MMC external circuit injection current to the MMC valve simulator to enter the next simulation period.
As an improvement of the above scheme, the power module level fault and protection logic information base includes the following fault types:
the sampling of the capacitor voltage is abnormal; an uplink communication failure; a bypass switch malfunction; the bypass switch refuses to operate; IGBT force block; IGBT force fire; IGBT set fire; a power module short circuit fault; a downlink communication failure; power module level protection;
the processing logic information base comprises the following processing logic:
sending the abnormal voltage value to a valve control; the power module feeds back a fault bit to the valve control; performing AND operation on the valve control FPW control bit and the fault control bit; carrying out AND operation on the result of the non-operation of the fault control bit and the valve control FPW control bit; carrying out OR operation on the valve control FPW control bit and the fault control bit; taking the fault control bit as a final IGBT conduction control bit; the second full-control switch device of the half-bridge is forced to be switched on, and the first full-control switch device of the half-bridge is forced to be switched off; the first full-bridge full-control switch device and the third full-bridge full-control switch device are forced to be conducted, and the second full-bridge full-control switch device and the fourth full-bridge full-control switch device are forced to be turned off; the power module seals the pulse or the power module is self-bypassed; the power module seals pulses;
the half-bridge second full-control switch device is a full-control switch device which is connected in parallel with two sides of a positive terminal and a negative terminal of a module in a half-bridge type power module, and the half-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a positive terminal of the module in the half-bridge type power module; the full-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a module positive terminal in the full-bridge power module, the full-bridge second full-control switch device is a full-control switch device of which a drain electrode or a collector electrode is connected with the module positive terminal in the full-bridge power module, the full-bridge third full-control switch device is a full-control switch device of which the emitting electrode is connected with a module negative terminal in the full-bridge power module, and the full-bridge fourth full-control switch device is a full-control switch device of which the drain electrode or the collector electrode is connected with the module negative terminal in the full-bridge power module;
the fault types in the power module level fault and protection logic information base and the processing logic in the processing logic information base are in a one-to-one mapping relation.
As an improvement of the above solution, the step of defining the syntax of the fault control word includes:
and enabling each bridge arm in the MMC to support 6 fault control words, wherein each fault control word is 32bit, bit 12-bit 0 represents that each fault trigger control bit corresponds to the fault type library, bit 21-bit 13 represents reserved fault trigger control bits, and bit 31-bit 22 represents the serial number information of a fault power module.
As an improvement of the above solution, the step of comprehensive judgment decoding includes:
reading a fault control word of the fault module;
decoding the fault control word of the fault module to obtain the serial number and the fault control bit of the power module;
and generating an actual trigger control word according to the power module level fault and protection action trigger logic.
As an improvement of the above solution, the step of generating an actual trigger control word according to the power module level fault and protection action trigger logic comprises:
generating a trigger control word according to the serial number of the power module and the fault control bit;
judging whether the fault control bit of the power module is enabled;
if the fault control bit of the power module is not enabled, taking the trigger control bit issued by the MMC valve control device as an actual trigger control bit; judging whether the fault type corresponding to the fault control word is polled; if yes, generating the actual trigger control word;
if the fault control bit of the power module is enabled, judging whether the fault corresponding to the fault control bit changes a trigger pulse control bit; if yes, generating an actual trigger control bit according to the fault control bit and the trigger pulse control bit; if not, triggering the fault; judging whether the fault type corresponding to the fault control word is polled; and if so, generating the actual trigger control word.
As an improvement of the above scheme, the step of obtaining the MMC valve injection current, the bridge arm currents, the power module capacitance voltage and the state information according to the substitute network comprises:
determining a fault module according to the trigger control word;
obtaining the current of each bridge arm, the capacitance voltage and state information of the power module and the MMC valve injection current according to the fault module;
if the MMC valve is of a half-bridge type, the fault module comprises a locked power module, a power module which is being put into use and a power module which is bypassed; if the MMC valve is a full-bridge type, the fault module comprises a locked power module, a power module with positive input or negative input, a power module with short-circuit failure of a first full-bridge or second full-bridge full-control switch device, a power module with short-circuit failure of a third full-bridge or fourth full-bridge full-control switch device and a power module with a bypass.
The third embodiment of the invention provides an MMC power module level fault and protection logic dynamic simulation system, which comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, wherein the processor executes the program to realize the MMC power module level fault and protection logic dynamic simulation method.
The fourth embodiment of the present invention provides a computer-readable storage medium, where the computer-readable storage medium includes a stored computer program, and when the computer program runs, a device in which the computer-readable storage medium is located is controlled to execute the method for dynamically simulating the MMC power module level fault and the protection logic in the foregoing embodiment of the present invention.
Compared with the prior art, the MMC power module level fault and protection logic dynamic simulation system, the method and the storage medium provided by the embodiment of the invention have the following beneficial effects:
the MMC valve is simulated through the MMC valve simulator, the MMC external circuit simulator simulates an MMC external circuit, the first logic processor establishes a power module level fault and protection logic simulation rule, and the second logic processor establishes a power module level fault and protection action trigger logic, so that the system can dynamically simulate various types of faults in real time and output corresponding simulation results, and dynamic simulation of the faults in various types is realized; the fault processing logic and the fault control logic can be established according to the actual control protection strategy of the power module level, and the method can be suitable for various actual working conditions, so that the universality and the expansibility of the system are improved; the dynamic adjustment precision is in a mu s level (<2.5 mu s), and the fault simulation result of the system is more accurate.
Drawings
Fig. 1 is a schematic structural diagram of an MMC power module level fault and protection logic dynamic simulation system according to an embodiment of the present invention.
Fig. 2 is a schematic flowchart of a dynamic simulation method for MMC power module level fault and protection logic according to a second embodiment of the present invention.
Fig. 3 is a mapping schematic diagram of a power module level fault and protection logic information base and a processing logic information base in an MMC power module level fault and protection logic dynamic simulation method according to a second embodiment of the present invention.
Fig. 4 is a schematic diagram of a half-bridge power module topology structure of an MMC power module-level fault and protection logic dynamic simulation method according to a second embodiment of the present invention.
Fig. 5 is a schematic diagram of a full-bridge power module topology structure of an MMC power module-level fault and protection logic dynamic simulation method according to a second embodiment of the present invention.
Fig. 6 is a schematic diagram of a language structure of a fault control word of a dynamic simulation method for a power module level fault and protection logic of an MMC according to a second embodiment of the present invention.
Fig. 7 is a schematic diagram of a comprehensive judgment decoding process of the MMC power module level fault and protection logic dynamic simulation method according to the second embodiment of the present invention.
Fig. 8 is a power module level overvoltage protection segment 1 logic block diagram.
Fig. 9 is a power module level overvoltage protection 2-segment logic block diagram.
Fig. 10 is a simulation waveform at the first overvoltage of the field and simulation test.
FIG. 11 is a simulated waveform of field and simulated experimental soft and straight latch.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a schematic structural diagram of an MMC power module level fault and protection logic dynamic simulation system according to an embodiment of the present invention includes a first simulation module 101, a second simulation module 102, an MMC valve control device, and a control protection device;
the first simulation module 101 comprises a first logic processor 111 and an MMC valve simulator 121, the MMC valve simulator 121 being for simulating an MMC valve;
the second emulation module 102 comprises a second logical processor 112 and an MMC external circuit emulator 122, the MMC external circuit emulator 122 being configured to emulate an MMC external circuit;
the first logic processor 111 establishes power module level fault and protection logic simulation rules; establishing a power module level fault and protection logic simulation rule, specifically establishing a power module level fault and protection logic information base, establishing a processing logic information base and a mapping relation corresponding to the processing logic information base and the processing logic information base, and defining a fault control word grammar;
the second logical processor 112 establishes power module level fault and protection action trigger logic;
in a simulation cycle, the second logic processor 112 determines a fault module, generates a fault control word according to a fault control word grammar, and sends the fault control word to the first logic processor 111;
the MMC valve control device generates a trigger pulse according to the received modulation wave signal for controlling the protection device, and sends the trigger pulse to the first logic processor 111;
the first logic processor 111 comprehensively judges and decodes the received fault control word and trigger pulse, and generates an actual trigger control word according to the power module level fault and protection logic simulation rule; generating a substitute network according to the actual trigger control word; obtaining the MMC valve injection current, each bridge arm current, the power module capacitance voltage and the state information according to the substitution network, sending the MMC valve injection current to the MMC external circuit simulator 122, and sending each bridge arm current, the power module capacitance voltage and the state information to the MMC valve control device;
the MMC external circuit emulator 122 obtains an MMC external circuit injection current according to the received MMC valve injection current; the MMC valve control device receives the current of each bridge arm, the capacitance voltage of the power module and state information, and sequences the current of each bridge arm and the capacitance voltage of the power module;
the MMC external circuit emulator 122 sends the MMC external circuit injection current to the MMC valve emulator 121, and enters the next emulation cycle.
Further, the first simulation module 101 is an FPGA (Field-Programmable Gate Array), and the second simulation module 102 is an RTDS (Real Time Digital Simulator).
Preferably, the second simulation module 102 may also be an RT-LAB or Hypersim.
Specifically, each bridge arm is formed by connecting at least one submodule and a reactor in series;
further, the power module level fault and protection logic information base includes the following fault types:
the sampling of the capacitor voltage is abnormal; an uplink communication failure; a bypass switch malfunction; the bypass switch refuses to operate; IGBT force block; IGBT force fire; IGBT set fire; a power module short circuit fault; a downlink communication failure; power module level protection;
the processing logic information base comprises the following processing logic:
sending the abnormal voltage value to a valve control; the power module feeds back a fault bit to the valve control; performing AND operation on the valve control FPW control bit and the fault control bit; carrying out AND operation on the result of the non-operation of the fault control bit and the valve control FPW control bit; carrying out OR operation on the valve control FPW control bit and the fault control bit; taking the fault control bit as a final IGBT conduction control bit; the second full-control switch device of the half-bridge is forced to be switched on, and the first full-control switch device of the half-bridge is forced to be switched off; the first full-bridge full-control switch device and the third full-bridge full-control switch device are forced to be conducted, and the second full-bridge full-control switch device and the fourth full-bridge full-control switch device are forced to be turned off; the power module seals the pulse or the power module is self-bypassed; the power module seals pulses;
the half-bridge second full-control switch device is a full-control switch device which is connected in parallel with two sides of a positive terminal and a negative terminal of a module in a half-bridge type power module, and the half-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a positive terminal of the module in the half-bridge type power module; the full-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a module positive terminal in the full-bridge power module, the full-bridge second full-control switch device is a full-control switch device of which a drain electrode or a collector electrode is connected with the module positive terminal in the full-bridge power module, the full-bridge third full-control switch device is a full-control switch device of which the emitting electrode is connected with a module negative terminal in the full-bridge power module, and the full-bridge fourth full-control switch device is a full-control switch device of which the drain electrode or the collector electrode is connected with the module negative terminal in the full-bridge power module;
the fault type in the power module level fault and protection logic information base and the processing logic in the processing logic information base are in a one-to-one mapping relation.
Further, the step of defining the syntax of the fault control word comprises:
each bridge arm in the MMC supports 6 fault control words, each fault control word is 32bit, wherein bit 12-bit 0 represent fault type libraries corresponding to each fault trigger control bit, bit 21-bit 13 represent reserved fault trigger control bits, and bit 31-bit 22 represent fault power module number information.
Further, the step of comprehensive judgment decoding comprises:
reading a fault control word of a fault module;
decoding the fault control word of the fault module to obtain the serial number and the fault control bit of the power module;
and generating an actual trigger control word according to the power module level fault and protection action trigger logic.
Further, the step of generating the actual trigger control word according to the power module level fault and protection action trigger logic comprises:
generating a trigger control word according to the serial number of the power module and the fault control bit;
judging whether the fault control bit of the power module is enabled;
if the fault control bit of the power module is not enabled, taking the trigger control bit issued by the MMC valve control device as an actual trigger control bit; judging whether the fault type corresponding to the fault control word is polled; if yes, generating an actual trigger control word;
if the fault control bit of the power module is enabled, judging whether the fault corresponding to the fault control bit changes the trigger pulse control bit; if yes, generating an actual trigger control bit according to the fault control bit and the trigger pulse control bit; if not, triggering a fault; judging whether the fault type corresponding to the fault control word is polled; if so, an actual trigger control word is generated.
Further, the step of obtaining the MMC valve injection current, the bridge arm currents, the power module capacitance voltage and the state information according to the substitution network comprises the following steps:
judging the type of the fault module according to the trigger control word, and determining the fault module;
obtaining current of each bridge arm, capacitance voltage and state information of the power module and MMC valve injection current according to the fault module;
if the MMC valve is of a half-bridge type, the fault module comprises a locked power module, a power module which is being put into use and a power module which is bypassed; if the MMC valve is a full-bridge type, the fault module comprises a locked power module, a power module with positive input or negative input, a power module with short-circuit failure of a first full-bridge or second full-bridge full-control switch device, a power module with short-circuit failure of a third full-bridge or fourth full-bridge full-control switch device and a power module with a bypass.
The MMC valve is simulated through the MMC valve simulator, the MMC external circuit simulator simulates an MMC external circuit, the first logic processor establishes a power module level fault and protection logic simulation rule, and the second logic processor establishes power module level fault and protection action triggering logic, so that the system can trigger corresponding faults when various fault types exist and output corresponding simulation results, and fault type simulation under various types is realized; the fault processing logic and the fault control logic can be established according to the actual control protection strategy of the power module level, so that the system can be suitable for various working conditions, and the universality and the expansibility of the system are improved; the dynamic adjustment precision is in a mu s level (<2.5 mu s), so that the fault simulation result of the system is more accurate.
Referring to fig. 2, a schematic flow chart of an MMC power module level fault and protection logic simulation method according to a second embodiment of the present invention includes the following steps:
s201, establishing a power module level fault and protection logic simulation rule in a first logic processor; establishing a power module level fault and protection logic simulation rule, specifically establishing a power module level fault and protection logic information base, establishing a processing logic information base and defining a fault control word grammar;
s202, establishing power module level fault and protection action triggering logic in a second logic processor;
s203, in a simulation period, the second logic processor determines a fault module, generates a fault control word according to a fault control word grammar and sends the fault control word to the first logic processor;
s204, the MMC valve control device generates a trigger pulse according to the received modulating wave signal of the control protection device and sends the trigger pulse to the first logic processor;
s205, the first logic processor comprehensively judges and decodes the received fault control word and the trigger pulse, and generates an actual trigger control word according to the power module level fault and protection logic simulation rule; generating a substitute network according to the actual trigger control word; obtaining MMC valve injection current, each bridge arm current, power module capacitance voltage and state information according to a substitution network, sending the MMC valve injection current to an MMC external circuit simulator, and sending each bridge arm current, the power module capacitance voltage and the state information to an MMC valve control device;
s206, the MMC external circuit simulator obtains the MMC external circuit injection current according to the received MMC valve injection current; the MMC valve control device receives the current of each bridge arm, the capacitance voltage of the power module and state information, and sequences the current of each bridge arm and the capacitance voltage of the power module;
and S207, the MMC external circuit simulator sends the MMC external circuit injection current to the MMC valve simulator, and the next simulation period is started.
Further, for step S201, the power module level fault and protection logic information base includes the following fault types:
the sampling of the capacitor voltage is abnormal; an uplink communication failure; a bypass switch malfunction; the bypass switch refuses to operate; IGBT force block; IGBT force fire; IGBT set fire; a power module short circuit fault; a downlink communication failure; power module level protection;
the processing logic information base comprises the following processing logic:
sending the abnormal voltage value to a valve control; the power module feeds back a fault bit to the valve control; performing AND operation on the valve control FPW control bit and the fault control bit; carrying out AND operation on the result of the non-operation of the fault control bit and the valve control FPW control bit; carrying out OR operation on the valve control FPW control bit and the fault control bit; taking the fault control bit as a final IGBT conduction control bit; the second full-control switch device of the half-bridge is forced to be switched on, the first full-control switch device of the half-bridge is forced to be switched off, the first full-control switch device of the full-bridge and the third full-control switch device of the full-bridge are forced to be switched on, and the second full-control switch device of the full-bridge and the fourth full-control switch device of the full-bridge are forced to be switched off; the power module seals the pulse or the power module is self-bypassed; the power module seals pulses;
the half-bridge second full-control switch device is a full-control switch device which is connected in parallel with two sides of a positive terminal and a negative terminal of a module in a half-bridge type power module, and the half-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a positive terminal of the module in the half-bridge type power module; the full-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a module positive terminal in the full-bridge power module, the full-bridge second full-control switch device is a full-control switch device of which a drain electrode or a collector electrode is connected with the module positive terminal in the full-bridge power module, the full-bridge third full-control switch device is a full-control switch device of which the emitting electrode is connected with a module negative terminal in the full-bridge power module, and the full-bridge fourth full-control switch device is a full-control switch device of which the drain electrode or the collector electrode is connected with the module negative terminal in the full-bridge power module;
the fault type in the power module level fault and protection logic information base and the processing logic in the processing logic information base are in a one-to-one mapping relation.
Preferably, referring to fig. 3, a schematic diagram of mapping between a power module level fault and protection logic information base and a processing logic information base of an MMC power module level fault and protection simulation method according to a second embodiment of the present invention is provided.
Preferably, referring to fig. 4, a schematic diagram of a half-bridge power module topology structure of an MMC power module level fault and protection simulation method according to a second embodiment of the present invention is provided; fig. 5 is a schematic diagram of a full-bridge power module topology structure of an MMC power module level fault and protection simulation method according to the second embodiment of the present invention.
Wherein, S1, S2, S3, S4, S1 ', S2', S3 'and S4' are all-controlled switching devices in the sub-modules, respectively, and the all-controlled switching devices may be IGBTs; d1, D2, D3, D4, D1 ', D2', D3 'and D4' are diodes connected in anti-parallel on the fully-controlled switching device respectively; c and C' are capacitors in the sub-module; r and R' are discharge resistors connected in parallel on the capacitor; K. t, K 'and T' are bypass switches and thyristors for submodule protection, respectively.
At this time, the second fully-controlled switching device of the half-bridge is forced to be turned on, i.e., forced to be turned on at S2, the first fully-controlled switching device and the third fully-controlled switching device of the full-bridge are forced to be turned on, the second fully-controlled switching device and the fourth fully-controlled switching device of the full-bridge are forced to be turned off, i.e., forced to be turned on at S1 'and S3', and forced to be turned off at S2 'and S4'.
Further, for step S201, the step of defining the syntax of the fault control word includes:
each bridge arm in the MMC supports 6 fault control words, each fault control word is 32bit, wherein bit 12-bit 0 represent fault type libraries corresponding to each fault trigger control bit, bit 21-bit 13 represent reserved fault trigger control bits, and bit 31-bit 22 represent fault power module number information.
Preferably, referring to fig. 6, it is a schematic diagram of a syntax structure of a fault control word of the MMC power module level fault and protection simulation method according to the second embodiment of the present invention; the fault power module number information comprises group number information ppathi and an intra-group sequence number smnoi; wherein, group number information ppathi: setting 64 power modules into a group, wherein the group number is started from 0; the intra-group sequence number smnoi: the serial numbers of the power modules in the group are 0 to 63 respectively from 0 to 64.
The corresponding conversion relation is that if the number of power modules in each bridge arm is N, ppathi is INT ((N-1)/64), smnoi is MOD ((N-1)/64), wherein INT is an integer function, and MOD is a remainder function.
In the fault trigger control bits, bit12 and bit11 represent the type of IGBT fault, and when the type is 00, the type represents a force fire fault; when the value is 01, representing the force block fault; when it is 10, a set fire fault is indicated;
bits 10-7 represent IGBT failure modes, when each bit is 1, the corresponding IGBT is selected, and when the topological structure of the power module is a full-bridge type, bits 10-7 correspond to S4 'to S1' one by one respectively;
bit6 indicates a downstream communication fault, which is 1 indicating that the fault is enabled, and 0 indicating that the fault is not enabled;
bit5 indicates a bypass switch rejection fault, which is 1 indicating that the fault is enabled, and 0 indicating that the fault is not enabled;
bit4 indicates an upstream communication failure, which indicates that the failure is enabled when it is 1, and indicates that the failure is not enabled when it is 0;
bit3 indicates that the capacitor voltage adopts an abnormal fault, which is 1 to indicate that the fault is enabled, and 0 to indicate that the fault is not enabled;
bit2 indicates a bypass switch malfunction fault, which is 1 to indicate that the fault is enabled, and 0 to indicate that the fault is not enabled;
bit1 indicates IGBT fault enable, which when 1 indicates that the fault is enabled, and when 0 indicates that the fault is not enabled;
bit0 indicates power module short fault enable, which is 1 to indicate that the fault is enabled, and 0 to indicate that the fault is not enabled.
Preferably, bits 22 through bit13 are defined as reserved custom fault trigger control bits.
Further, for step 204, the MMC valve control device generates a trigger pulse by a nearest level approximation method according to the received modulated wave signal for controlling the protection device.
Further, as for step S205, the step of comprehensive judgment decoding includes:
reading a fault control word of a fault module;
decoding the fault control word of the fault module to obtain the serial number and the fault control bit of the power module;
and generating an actual trigger control word according to the power module level fault and protection action trigger logic.
Further, for step S205, the step of generating the actual trigger control word according to the power module level fault and protection action trigger logic includes:
generating a trigger control word according to the serial number of the power module and the fault control bit;
judging whether the fault control bit of the power module is enabled;
if the fault control bit of the power module is not enabled, taking the trigger control bit issued by the MMC valve control device as an actual trigger control bit; judging whether the fault type corresponding to the fault control word is polled; if yes, generating an actual trigger control word;
if the fault control bit of the power module is enabled, judging whether the fault corresponding to the fault control bit changes the trigger pulse control bit; if yes, generating an actual trigger control bit according to the fault control bit and the trigger pulse control bit; if not, triggering a fault; judging whether the fault type corresponding to the fault control word is polled; if so, an actual trigger control word is generated.
Preferably, referring to fig. 7, a schematic diagram of a comprehensive judgment decoding flow of the MMC power module level fault and protection logic simulation method according to the second embodiment of the present invention is shown, where J is 0, 1, …, and J is a total fault type number.
Further, for step 205, the step of obtaining the MMC valve injection current, the bridge arm currents, the power module capacitance voltage, and the state information according to the alternative network includes:
judging the type of the fault module according to the trigger control word, and determining the fault module;
obtaining current of each bridge arm, capacitance voltage and state information of the power module and MMC valve injection current according to the fault module;
if the MMC valve is of a half-bridge type, the fault module comprises a locked power module, a power module which is in a positive input state and a power module which is in a bypass state; if the MMC valve is of a full-bridge type, the fault module comprises a locked power module, a power module with positive input or negative input, a power module with short-circuit failure of a full-bridge first or second full-control switch device, a power module with short-circuit failure of a full-bridge third or fourth full-control switch device and a power module with a bypass.
Preferably, for step 206, the power module capacitor voltages of the same bridge arm are sorted in order of magnitude.
Preferably, the first logical processor and the second logical processor are previously communicated via a high-speed optical communication fiber.
In a specific embodiment, when a fault occurs in a power module and a bypass switch fails to operate in an upper bridge arm of a phase A of a flexible and straight engineering site, the power module undergoes the whole process of 'intermittent charging and self-discharging in a cycle, voltage rise → first overvoltage → IGBT down tube turn-on, continuous self-discharging, voltage drop → IGBT down tube turn-off → intermittent charging and self-discharging in a cycle, voltage rise → overvoltage again → tripping' under the action of module level overvoltage protection 1, 2 and valve control level overvoltage protection and the like.
Establishing a power module level fault and protection type and processing logic information base and defining a fault control word grammar in the FPGA;
establishing power module level overvoltage protection logic in the RTDS, referring to fig. 8, which is a logic block diagram of a power module level overvoltage protection 1 segment; referring to fig. 9, a power module level overvoltage protection 2-segment logic block diagram is shown. In the figure, the initial state Q of the SR flip-flop is 0;
enabling a 1-section and a 2-section overvoltage of a module level in an RTDS to mark a position 1;
the RTDS is converted to obtain the power module number information, which comprises the following steps: bit 31-bit 28 ═ 01102，bit27～bit22＝(001100)2；
Selecting a set fire fault: bit 12-bit 11 ═ 102；
Enabling bypass switch failure: bit5 ═ 1;
enabling an IGBT fault: bit1 ═ 1;
the system automatically dynamically adjusts the value of a fault control word according to the fault type and the control protection time sequence set in the early stage, changes the trigger pulse of a selected power module and dynamically simulates the whole process of an accident.
Referring to fig. 10, which is a simulation waveform of a field and simulation test at the first overvoltage, referring to fig. 11, which is a simulation waveform of a field and simulation test soft-direct latch, it can be seen that a simulation waveform generated by the MMC power module level fault and protection logic dynamic simulation system and method provided by the embodiment of the present invention is almost the same as a field waveform, i.e., simulation of multiple fault types can be realized, and a simulation result is better.
The third embodiment of the present invention further provides an MMC power module level fault and protection logic dynamic simulation system, which includes a memory, a processor, and a computer program stored in the memory and operable on the processor, wherein the processor implements a communication information protection method when executing the program.
The communication information protection device/terminal equipment can be computing equipment such as a desktop computer, a notebook computer, a palm computer and a cloud server. The communication information protection device/terminal equipment may include, but is not limited to, a processor, a memory. It will be understood by those skilled in the art that the schematic diagram is merely an example of a communication information protection apparatus/terminal device, and does not constitute a limitation of the communication information protection apparatus/terminal device, and may include more or less components than those shown, or combine some components, or different components, for example, the communication information protection apparatus/terminal device may further include an input-output device, a network access device, a bus, etc.
The Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the communication information protection apparatus/terminal device, various interfaces and lines connecting the various parts of the entire communication information protection apparatus/terminal device.
The memory may be used to store the computer programs and/or modules, and the processor may implement various functions of the communication information protection apparatus/terminal device by running or executing the computer programs and/or modules stored in the memory and calling data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating device, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
Wherein, the module/unit integrated with the communication information protection device/terminal equipment can be stored in a computer readable storage medium if it is realized in the form of software functional unit and sold or used as an independent product. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like.
The fourth embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, where the computer program, when executed by a processor, implements a communication information protection method.
Illustratively, the computer program may be partitioned into one or more modules/units that are stored in the memory and executed by the processor to implement the invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution process of the computer program in the communication information protection apparatus/terminal device.
The above embodiments are similar to the corresponding embodiments in the MMC power module level fault and protection logic dynamic simulation method of the present invention, and are not described herein again.
Compared with the prior art, the MMC power module level fault and protection logic dynamic simulation system, the method and the storage medium provided by the embodiment of the invention have the following beneficial effects:
the MMC valve is simulated through the MMC valve simulator, the MMC external circuit simulator simulates an MMC external circuit, the first logic processor establishes a power module level fault and protection logic simulation rule, and the second logic processor establishes power module level fault and protection action triggering logic, so that the system can trigger corresponding faults when various fault types exist and output corresponding simulation results, and fault type simulation under various types is realized; the fault processing logic and the fault control logic can be established according to the actual control protection strategy of the power module level, so that the system can be suitable for various working conditions, and the universality and the expansibility of the system are improved; the dynamic adjustment precision is in a mu s level (<2.5 mu s), so that the fault simulation result of the system is more accurate.
It should be noted that the above-described device embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A MMC power module level fault and protection logic dynamic simulation system is characterized by comprising a first simulation module, a second simulation module, an MMC valve control device and a control protection device;
the first simulation module comprises a first logic processor and an MMC valve simulator, and the MMC valve simulator is used for simulating an MMC valve;
the second simulation module comprises a second logic processor and an MMC external circuit simulator, and the MMC external circuit simulator is used for simulating an MMC external circuit;
the first logic processor establishes a power module level fault and protection logic simulation rule; establishing a power module level fault and protection logic simulation rule, specifically establishing a power module level fault and protection logic information base, establishing a processing logic information base and a mapping relation corresponding to the processing logic information base and the processing logic information base, and defining a fault control word grammar;
the second logic processor establishes power module level fault and protection action trigger logic;
in a simulation period, the second logic processor determines a fault module, generates a fault control word according to the syntax of the fault control word and sends the fault control word to the first logic processor;
the MMC valve control device generates a trigger pulse according to a received modulation wave signal for controlling the protection device and sends the trigger pulse to the first logic processor;
the first logic processor carries out comprehensive judgment and decoding on the received fault control word and the trigger pulse, and generates an actual trigger control word according to the power module level fault and protection logic simulation rule; generating a substitute network according to the actual trigger control word; obtaining MMC valve injection current, each bridge arm current, power module capacitance voltage and state information according to the substitution network, sending the MMC valve injection current to the MMC external circuit simulator, and sending each bridge arm current, power module capacitance voltage and state information to the MMC valve control device;
the MMC external circuit simulator obtains MMC external circuit injection current according to the received MMC valve injection current; the MMC valve control device receives the current of each bridge arm, the capacitance voltage of the power module and state information, and sequences the current of each bridge arm and the capacitance voltage of the power module;
and the MMC external circuit simulator sends the MMC external circuit injection current to the MMC valve simulator to enter the next simulation period.
2. The MMC power module level fault and protection logic dynamic simulation system of claim 1, wherein the first emulation module is an FPGA and the second emulation module is an RTDS.
3. A MMC power module level fault and protection logic dynamic simulation method is characterized by being applied to an MMC power module level fault and protection dynamic simulation system, wherein the system comprises a first simulation module, a second simulation module, an MMC valve control device and a control protection device; the first simulation module comprises a first logic processor and an MMC valve simulator, and the MMC valve simulator is used for simulating an MMC valve; the second simulation module comprises a second logic processor and an MMC external circuit simulator, and the MMC external circuit simulator is used for simulating an MMC external circuit; the method comprises the following steps:
establishing a power module level fault and protection logic simulation rule in the first logic processor; establishing a power module level fault and protection logic simulation rule, specifically establishing a power module level fault and protection logic information base, establishing a processing logic information base and a mapping relation corresponding to the processing logic information base and the processing logic information base, and defining a fault control word grammar;
establishing power module level fault and protection action triggering logic in the second logical processor;
in a simulation period, the second logic processor determines a fault module, generates a fault control word according to the syntax of the fault control word and sends the fault control word to the first logic processor;
the MMC valve control device generates a trigger pulse according to a received modulation wave signal for controlling the protection device and sends the trigger pulse to the first logic processor;
the first logic processor carries out comprehensive judgment and decoding on the received fault control word and the trigger pulse, and generates an actual trigger control word according to the power module level fault and protection logic simulation rule; generating a substitute network according to the actual trigger control word; obtaining MMC valve injection current, each bridge arm current, power module capacitance voltage and state information according to the substitution network, sending the MMC valve injection current to the MMC external circuit simulator, and sending each bridge arm current, power module capacitance voltage and state information to the MMC valve control device;
the MMC external circuit simulator obtains MMC external circuit injection current according to the received MMC valve injection current; the MMC valve control device receives the current of each bridge arm, the capacitance voltage of the power module and state information, and sequences the current of each bridge arm and the capacitance voltage of the power module;
and the MMC external circuit simulator sends the MMC external circuit injection current to the MMC valve simulator to enter the next simulation period.
4. The MMC power module level fault and protection logic dynamic simulation method of claim 3, wherein the power module level fault and protection logic information base comprises a fault type of:
the sampling of the capacitor voltage is abnormal; an uplink communication failure; a bypass switch malfunction; the bypass switch refuses to operate; IGBT force block; IGBT force fire; IGBT set fire; a power module short circuit fault; a downlink communication failure; power module level protection;
the processing logic information base comprises the following processing logic:
sending the abnormal voltage value to a valve control; the power module feeds back a fault bit to the valve control; performing AND operation on the valve control FPW control bit and the fault control bit; carrying out AND operation on the result of the non-operation of the fault control bit and the valve control FPW control bit; carrying out OR operation on the valve control FPW control bit and the fault control bit; taking the fault control bit as a final IGBT conduction control bit; the second full-control switch device of the half-bridge is forced to be switched on, and the first full-control switch device of the half-bridge is forced to be switched off; the first full-bridge full-control switch device and the third full-bridge full-control switch device are forced to be conducted, and the second full-bridge full-control switch device and the fourth full-bridge full-control switch device are forced to be turned off; the power module seals the pulse or the power module is self-bypassed; the power module seals pulses;
the half-bridge second full-control switch device is a full-control switch device which is connected in parallel with two sides of a positive terminal and a negative terminal of a module in a half-bridge type power module, and the half-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a positive terminal of the module in the half-bridge type power module; the full-bridge first full-control switch device is a full-control switch device of which an emitting electrode is connected with a module positive terminal in the full-bridge power module, the full-bridge second full-control switch device is a full-control switch device of which a drain electrode or a collector electrode is connected with the module positive terminal in the full-bridge power module, the full-bridge third full-control switch device is a full-control switch device of which the emitting electrode is connected with a module negative terminal in the full-bridge power module, and the full-bridge fourth full-control switch device is a full-control switch device of which the drain electrode or the collector electrode is connected with the module negative terminal in the full-bridge power module;
the fault types in the power module level fault and protection logic information base and the processing logic in the processing logic information base are in a one-to-one mapping relation.
5. The MMC power module level fault and protection logic dynamic simulation method of claim 4, wherein the step of defining a fault control word syntax comprises:
and enabling each bridge arm in the MMC to support 6 fault control words, wherein each fault control word is 32bit, bit 12-bit 0 represents that each fault trigger control bit corresponds to the fault type library, bit 21-bit 13 represents reserved fault trigger control bits, and bit 31-bit 22 represents the serial number information of a fault power module.
6. The MMC power module level fault and protection logic dynamic simulation method of claim 5, wherein the step of comprehensive decision decoding comprises:
reading a fault control word of the fault module;
decoding the fault control word of the fault module to obtain the serial number and the fault control bit of the power module;
and generating an actual trigger control word according to the power module level fault and protection action trigger logic.
7. The MMC power module level fault and protection logic dynamic simulation method of claim 6, wherein generating an actual trigger control word based on the power module level fault and protection action trigger logic comprises:
generating a trigger control word according to the serial number of the power module and the fault control bit;
judging whether the fault control bit of the power module is enabled;
if the fault control bit of the power module is not enabled, taking the trigger control bit issued by the MMC valve control device as an actual trigger control bit; judging whether the fault type corresponding to the fault control word is polled; if yes, generating the actual trigger control word;
if the fault control bit of the power module is enabled, judging whether the fault corresponding to the fault control bit changes a trigger pulse control bit; if yes, generating an actual trigger control bit according to the fault control bit and the trigger pulse control bit; if not, triggering the fault; judging whether the fault type corresponding to the fault control word is polled; and if so, generating the actual trigger control word.
8. The method according to claim 7, wherein the step of obtaining the MMC valve injection current, each bridge arm current, power module capacitance voltage and state information from the alternative network according to the alternative network comprises:
determining a fault module according to the trigger control word;
obtaining the current of each bridge arm, the capacitance voltage and state information of the power module and the MMC valve injection current according to the fault module;
if the MMC valve is of a half-bridge type, the fault module comprises a locked power module, a power module which is being put into use and a power module which is bypassed; if the MMC valve is of a full-bridge type, the fault module comprises a locked power module, a power module with positive input or negative input, a power module with short-circuit failure of a full-bridge first or second full-control switch device, a power module with short-circuit failure of a full-bridge third or fourth full-control switch device and a power module with a bypass.
9. An MMC power module level fault and protection logic dynamic simulation system comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, the processor when executing the computer program implementing an MMC power module level fault and protection logic dynamic simulation method as claimed in any one of claims 3 to 8.
10. A computer-readable storage medium, comprising a stored computer program, wherein the computer program, when executed, controls an apparatus in which the computer-readable storage medium is located to perform a MMC power module level fault and protection logic dynamic simulation method according to any one of claims 3 to 8.
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