CN110198161B

CN110198161B - On-chip time delay line based on selection network

Info

Publication number: CN110198161B
Application number: CN201910448354.5A
Authority: CN
Inventors: 徐志伟; 厉敏; 李娜雨; 王绍刚; 张梓江; 高会言; 宋春毅
Original assignee: Zhejiang University ZJU
Current assignee: Yantai Xin Yang Ju Array Microelectronics Co ltd
Priority date: 2019-05-28
Filing date: 2019-05-28
Publication date: 2021-03-05
Anticipated expiration: 2039-05-28
Also published as: CN110198161A

Abstract

The invention provides an on-chip delay line based on a selection network, which comprises a single-ended on-chip delay line and a corresponding single-ended delay selection network, and a differential on-chip delay line and a corresponding differential delay selection network. The invention can be controlled by electric signals to cause specific time delay to input radio frequency signals, and can realize the maximum time delay of about 1ns in the range of 2 GHz-20 GHz on a chip.

Description

On-chip time delay line based on selection network

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an on-chip delay line based on a selection network.

Background

Delay lines are widely used in different circuits, such as phased array systems, Delay Locked Loops (Delay Locked Loops), filters, and equalizers. The traditional narrow-band phased array generally adopts a phase shifter and a variable gain control element to form an array element, the phase shifter uses the nature of phase shifting approximate time delay to enable a broadband signal to generate distortion, the introduced error amount depends on the instantaneous bandwidth of the signal and the propagation delay difference of the signal between the array elements, and a time delay line is indispensable in the application of processing the ultra-wideband signal.

The existing published time delay line technology has the problems of small time delay range (less than 200ps time delay), inapplicability to large-scale time delay arrays, inflexible array, and the like.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides an on-chip delay line based on a selection network, which is controlled by an electric signal to cause time delay of a specific length to an input radio frequency signal.

The purpose of the invention is realized by the following technical scheme:

a time delay line on a chip based on a selection network is characterized by comprising a single-ended time delay line on the chip and a corresponding single-ended time delay selection network, a differential time delay line on the chip and a corresponding differential time delay selection network;

the single-ended on-chip time delay line structure comprises an on-chip adjustable capacitor CS₀，CS₁，CS₂，CS₃，CS₄，……CS_n-2，CS_n-1，CS_nOn-chip inductor LS₁，LS₂，LS₃，LS₄，……LS_n-2，LS_n-1，LS_nAnd on-chip resistor RS₀Inductance LS₁One terminal of and a capacitor CS₀Are connected at one end, an inductance LS₁Another terminal of (1) and a capacitor CS₁One terminal of and an inductor LS₂Are connected at one end, an inductance LS₂Another terminal of (1) and a capacitor CS₂One terminal of and an inductor LS₃One end of the inductor is connected, and so on, the inductor LS_n-1Another terminal of (1) and a capacitor CS_n-1One terminal of and an inductor LS_nAre connected to one end of, and a final inductor LS_nAnd capacitor CS_nOne end of the on-chip capacitors is connected, and the other ends of all the on-chip capacitors are connected with the ground of the circuit; each on-chip capacitor and an inductor with the same subscript form a time delay unit, each time delay unit IS connected into a single-ended low-pass filter form, an input end IS of a single-ended on-chip time delay line provides a radio frequency input signal, and an output signal of the single-ended on-chip time delay line comprises an OS₀、OS₁、OS₂、OS₃、OS₄、……OS_n-3、OS_n-2、OS_n-1、OS_nThe position of the output signal being at the port of the inductor, OS₀Located in the inductor LS₁One end of, OS₁Located in the inductor LS₁The other end of (1), OS₂Located in the inductor LS₂The other end of (1), and so on, OS_nLocated in the inductor LS_nAnother end of (3), on-chip resistance RS₀Connected to the end of the delay line and connected to the OS_nThe other end is grounded, the resistor RS₀The value of (A) is equal to the characteristic impedance value calculated according to the inductance and capacitance values of the delay line; wherein n represents the number of the single-ended delay line delay units, and n is more than or equal to 1;

the on-chip adjustable capacitor CS₀，CS₁，CS₂，CS₃，CS₄，……CS_n-2，CS_n-1，CS_nAre all switched capacitor arrays controlled by N-type metal-oxide-semiconductor field effect transistors, and the switched capacitor arrays comprise on-chip capacitors CSA₀、CSA₁、CSA₂、CSA₃、CSA₄、……、CSA_mNMOS transistor MS₁、MS₂、MS₃、MS₄、……、MS_mCapacitor CSA₁And transistor MS₁Of the transistor MS₁The source of the first switch is grounded to form a 1 st switch branch circuit and a capacitor CSA₂And transistor MS₂Of the transistor MS₂The source electrode of the capacitor is grounded to form a 2 nd switching branch circuit, and so on, and the capacitor CSA_mAnd transistor MS_mOf the transistor M_mThe source of the first switch is grounded to form an mth switch branch; fixed capacitor CSA₀Has one end grounded, and a capacitor CSA₀The other end of the capacitor is respectively connected with a capacitor CSA₁、CSA₂、CSA₃、CSA₄、……、CSA_mIs connected with the other end of the port, and the port is marked as an OS; transistor MS₁Is connected with the control signal GS₁Transistor MS₂Is connected with the control signal GS₂And so on, transistor MS_mIs connected with the control signal GS_mThe port OS corresponds to the OS of the single-ended delay line₀、OS₁、OS₂、……、OS_n(ii) a Wherein m represents the number of switch branches of the switched capacitor array of the single-ended delay line, and m is more than or equal to 1;

the on-chip inductor is an on-chip octagonal spiral inductor, the winding mode of the inductor is a regular octagon, the inductor main body uses the thickest layer of metal allowed by the process, the inductor adopts a left-in right-out structure to reduce the connection distance of two cascaded inductors, the number of turns of a coil and the number of turns of the coilThe inner diameter is adjusted step by step according to the required time delay; output signal OS on the left side of the inductor_k-1And the right side is the output signal OS_kWherein n is more than or equal to k and more than or equal to 1;

the differential on-chip time delay line structure comprises an on-chip capacitor CD₀、CD₁、CD₂、CD₃、CD₄、……CD_q-2、CD_q-1、CD_qOn-chip inductor LDP₁、LDP₂、LDP₃、LDP₄、……、LDP_q-2、LDP_q-1、LDP_q、LDN₁、LDN₂、LDN₃、LDN₄、……LDN_q-2、LDN_q-1、LDN_qAnd on-chip resistance RD₀(ii) a Inductor LDP₁One terminal of and capacitor CD₀One end of which is connected with an inductor LDP₁Another terminal of (1) and a capacitor CD₁And an inductor LDP₂One end of which is connected with an inductor LDP₂Another terminal of (1) and a capacitor CD₂And an inductor LDP₃One end of the inductor LDP is connected, and the like are repeated_q-1Another terminal of (1) and a capacitor CD_q-1And an inductor LDP_qOne end of the two ends are connected; inductor LDN₁One terminal of and capacitor CD₀Is connected with the other end of the inductor LDN₁Another terminal of (1) and a capacitor CD₁Another end of (1) and an inductor LDN₂One end of which is connected with an inductor LDN₂Another terminal of (1) and a capacitor CD₂Another end of (1) and an inductor LDN₃One end of the inductor LDN is connected, and the like are repeated_q-1Another terminal of (1) and a capacitor CD_q-1Another end of (1) and an inductor LDN_qAre connected at one end to a CD₁、LDP₁、LDN₁Forming a delay unit, analogizing in sequence, wherein the delay line structure on the differential chip comprises q delay units, each delay unit is connected into a differential low-pass filter form, the input ends IDP and IDN of the delay line on the differential chip provide differential radio frequency input signals, and the output signals of the delay line on the differential chip comprise (ODP)₀，ODN₀)、(ODP₁，ODN₁)、(ODP₂，ODN₂)、(ODP₃，ODN₃)、……、(ODP_q-2，ODN_q-2)、(ODP_q-1，ODN_q-1)、(ODP_q，ODN_q)，ODP₀Located in the inductor LDP₁One end of, ODN₀On the inductor LDN₁One end of, ODP₁Located in the inductor LDP₁The other end of (1), ODN₁On the inductor LDN₁The other end of (1), ODP₂Located in the inductor LDP₂The other end of (1), ODN₂On the inductor LDN₂The other end of (3), by analogy, ODP_qLocated in the inductor LDP_qThe other end of (1), ODN_qOn the inductor LDN_qAnother terminal of (3), on-chip resistance RD₀Connected to the end of the delay line and connected to the ODP_qAnd the other end is connected with the ODN_q(ii) a Resistance RD₀The value of (A) is equal to the characteristic impedance value calculated according to the inductance and capacitance values of the delay line; wherein q represents the number of delay units of the differential delay line, and q is more than or equal to 1;

the on-chip capacitor CD of the differential time delay line₀、CD₁、CD₂、CD₃、CD₄、……CD_q-2、CD_q-1、CD_qAre all controlled by N-type metal-oxide-semiconductor field effect transistor, and comprise on-chip capacitors CDA₀、CDA₁₁、CDA₁₂、CDA₂₁、CDA₂₂、CDA₃₁、CDA₃₂、CDA₄₁、CDA₄₂、……、CDA_p1、CDA_p2NMOS transistor MD₁₁、MD₁₂、MD₁₃、MD₂₁、MD₂₂、MD₂₃、MD₃₁、MD₃₂、MD₃₃、MD₄₁、MD₄₂、MD₄₃、……、MD_p1、MD_p2、MD_p3Capacitance CDA₁₁And transistor MD₁₁，MD₁₂Transistor MD₁₂The source of (2) is grounded; capacitor CDA₁₂And transistor MD₁₁Source electrode, MD₁₃Transistor MD₁₃The source electrode of the capacitor is grounded to form a 1 st switch branch circuit, and so on, and the capacitor CDA_p1And transistor MD_p1，MD_p2Transistor MD_p2The source of (2) is grounded; capacitor CDA_p2And transistor MD_p1Source electrode, MD_p3Transistor MD_p3The source of the first switch is grounded to form a pth switch branch; fixed capacitance CDA₀One terminal of each of which is connected to the capacitor CDA₁₁、CDA₂₁、CDA₃₁、CDA₄₁、……、CDA_p1Is connected with the other end of the port, and the port is marked as ODP; fixed capacitance CDA₀Respectively with the other end of the capacitor CDA₁₂、CDA₂₂、CDA₃₂、CDA₄₂、……、CDA_p2Is connected with the other end of the port, and the port is marked as ODN; transistor MD₁₁Is connected with a control signal GD₁₁，MD₁₂Is connected with a control signal GD₁₂，MD₁₃Is connected with a control signal GD₁₃By analogy, transistor MD_p1Is connected with a control signal GD_p1，MD_p2Is connected with a control signal GD_p2，MD_p3Is connected with a control signal GD_p3(ii) a ODP of port ODP corresponding to differential delay line₀、ODP₁、ODP₂、……、ODP_qODN with port ODN corresponding to differential delay line₀、ODN₁、ODN₂、……、ODN_q(ii) a The two capacitors in each switch branch have equal capacitance value, CDA₁₁And CDA₁₂Equal capacitance value, CDA₂₁And CDA₂₂Equal capacitance, and so on, CDA_p1And CDA_p2The capacitance values are equal; wherein p represents the number of switch branches of the switched capacitor array of the differential delay line, and p is more than or equal to 1;

the on-chip inductor LDP of the differential time delay line₁、LDP₂、LDP₃、LDP₄、……、LDP_q-2、LDP_q-1、LDP_q、LDN₁、LDN₂、LDN₃、LDN₄、……LDN_q-2、LDN_q-1、LDN_qThe inductor main bodies are all mutually coupled on-chip octagonal spiral inductors, and use the thickest layer of metal allowed by the process; the inductor adopts a left-in and right-out structure to shrinkThe wiring distance of the small two groups of cascade inductors; the number of turns and the inner diameter of the coil are adjusted step by step according to the required time delay, the LDP inductor and the LDN inductor with the same subscript number use a reverse coupling structure, the winding directions of the two inductors are opposite, and the left side of the inductor is an output signal (ODP)_k-1，ODN_k-1) The right side is the output signal (ODP)_k，ODN_k) Wherein, q is more than or equal to k and more than or equal to 1;

the single-ended delay selection network comprises an N-type metal-oxide-semiconductor field effect transistor (MSN)₀₁、MSN₀₂、MSN₁₁、MSN₁₂、MSN₂₁、MSN₂₂、MSN₃₁、MSN₃₂、……、MSN_(n-2)1、MSN_(n-2)2、MSN_(n-1)1、MSN_(n-1)2、MSN_n1、MSN_n2Wherein, MSN₀₁，MSN₀₂Grouped into one group, connected into cascode configuration, MSN₀₁As a common source, MSN₀₂As a common-gate tube, and so on, MSN_n1，MSN_n2Grouped into one group, connected into cascode configuration, MSN_n1As a common source, MSN_n2The NMOS tubes are used as common-gate tubes to form n +1 groups of common-source common-gate structure NMOS tubes; the NMOS tubes of the n +1 groups of cascode structures respectively correspond to n +1 OUTPUT signals of the single-ended delay line, the drains of the common-gate tubes of the n +1 groups of cascode NMOS tubes are connected together and are marked as an OUTPUT end OUTPUT, and the OUTPUT end is the OUTPUT end of the single-ended delay selection network; n +1 output signals OS of a single-ended delay line₀、OS₁、OS₂、……、OS_nThe grid electrodes are respectively connected with the common source tube of the n +1 group of NMOS tubes; the grid of the common grid tube of each group of NMOS tubes is connected with a control signal, and the common grid tube MSN₀₂Is connected with the control signal GSN₀₂Common gate tube MSN₁₂Is connected with the control signal GSN₁₂By analogy, common-gate tube MSN_n2Is connected with the control signal GSN_n2；

The differential time delay selection network comprises an N-type metal-oxide-semiconductor field effect transistor (MDN)₀₁、MDN₀₂、MDN₀₃、MDN₀₄、MDN₁₁、MDN₁₂、MDN₁₃、MDN₁₄、……、MDN_(q-1)1、MDN_(q-1)2、MDN_(q-1)3、MDN_(q-1)4、MDN_q1、MDN_q2、MDN_q3、MDN_q4Wherein, MDN₀₁，MDN₀₂，MDN₀₃，MDN₀₄Grouped into one group, MDN₀₁，MDN₀₂Connected in cascode configuration, MDN₀₃，MDN₀₄Connected in a cascode configuration, and so on, MDN_q1，MDN_q2，MDN_q3，MDN_q4Grouped into one group, MDN_q1，MDN_q2Connected in cascode configuration, MDN_q3，MDN_q4NMOS tubes connected into a cascode structure and having q +1 groups of differential cascode structures, corresponding to q +1 groups of output signals of the differential delay lines, respectively, and MDN₀₂、MDN₁₂、MDN₂₂、……、MDN_(q-2)2、MDN_(q-1)2、MDN_q2Are connected together and are denoted as OUTPUT, MDN₀₄、MDN₁₄、MDN₂₄、……、MDN_(q-2)4、MDN_(q-1)4、MDN_q4Are connected together and are denoted as OUTPUTN, OUTPUTP and OUTPUTN are differential output terminals of the differential delay selection network, the q +1 set of output signals (ODP) of the differential delay line₀，ODN₀)、(ODP₁，ODN₁)、(ODP₂，ODN₂)、……、(ODP_q，ODN_q) Respectively inputting the grid electrodes of each pair of common source tubes of the q +1 groups of NMOS tubes; a pair of common-gate transistors of each group of NMOS transistors are connected with control signals and MDN₀₂Is connected with a control signal GDN₀₂Common gate tube MDN₀₄Is connected with a control signal GDN₀₄Common gate tube MDN₁₂Is connected with a control signal GDN₁₂Common gate tube MDN₁₄Is connected with a control signal GDN₁₄By analogy, common-grid tube MDN_q2Is connected with a control signal GDN_q2Common gate tube MDN_q4Is connected with a control signal GDN_q4。

Furthermore, in each switched capacitor array in the single-ended on-chip delay line structure, the capacitance values of each switching branch are arranged in an equal ratio sequence with a common ratio of 2, and the size of the capacitance value accessed by the delay line is determined by a gate signal of a transistor of each capacitor array.

Furthermore, in each switched capacitor array in the delay line structure on the differential chip, the capacitance values of each switch branch are arranged in an equal ratio sequence with a common ratio of 2, and the size of the capacitance value accessed by the delay line is determined by the gate signal of the transistor of the capacitor array.

Further, in each switched capacitor array in the single-ended on-chip delay line structure, when the capacitance value of each switched branch is limited, the capacitance value of the switched branch exceeding the limit value is set to be equal to the maximum branch capacitance value not exceeding the limit value.

Further, in each switched capacitor array in the differential on-chip delay line structure, when the capacitance value of each switched branch is limited, the capacitance value of the switched branch exceeding the limit value is set to be equal to the maximum branch capacitance value not exceeding the limit value.

Further, in each switched capacitor array in the differential on-chip delay line structure, the 2 nd and 3 rd transistors MD of each branch circuit_k2、MD_k3Is not grounded but is connected to a fixed level value, wherein q ≧ k ≧ 1.

Further, in each switched capacitor array in the differential on-chip delay line structure, the 2 nd and 3 rd transistors MD of each branch circuit_k2、MD_k3Each being replaced by a resistor, MD_k1The drain and source potentials of the transistor are always pulled to the ground or a fixed level value through the resistor, wherein q is more than or equal to k and more than or equal to 1.

According to the invention, the delay length of each delay unit is adjusted by adjusting the control signals of the switch capacitor arrays of the single-ended delay line and the differential delay line; the number of the time delay units is determined by adjusting the control signals of the single-ended time delay selection network and the differential time delay selection network. The delay length can be flexibly adjusted by combining the two.

Compared with the prior art, the invention has the following beneficial effects: the invention can realize the maximum time delay of about 1ns in the range of 2 GHz-20 GHz on the chip, and the time delay range is obviously improved compared with the time delay range of the prior published time delay line technology; the invention can flexibly establish a large-scale time delay array in a combined mode and overcome the defects of the existing time delay line.

Drawings

FIG. 1 is a schematic diagram of a single-ended delay line;

FIG. 2 is a schematic structural diagram of a switched capacitor array corresponding to a single-ended delay line capacitor;

FIG. 3 is a diagram of a single-ended delay line inductor layout;

FIG. 4 is a schematic diagram of a differential delay line structure;

FIG. 5 is a schematic diagram of a switched capacitor array corresponding to differential delay line capacitors;

FIG. 6 is a schematic diagram of a layout structure of a differential delay line inductor;

FIG. 7 is a schematic diagram of a single-ended delay selection network;

fig. 8 is a schematic diagram of a differential delay selection network.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the objects and effects of the present invention will become more apparent, and the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

A time delay line on a chip based on a selection network comprises a single-ended time delay line on the chip and a corresponding single-ended time delay selection network, a differential time delay line on the chip and a corresponding differential time delay selection network;

fig. 1 shows a single-ended on-chip delay line structure according to the present invention. The single-ended on-chip time delay line structure comprises an on-chip adjustable capacitor CS₀，CS₁，CS₂，CS₃，CS₄，……CS_n-2，CS_n-1，CS_nOn-chip inductor LS₁，LS₂，LS₃，LS₄，……LS_n-2，LS_n-1，LS_nAnd on-chip resistor RS₀Inductance LS₁One terminal of and a capacitor CS₀Are connected at one end, an inductance LS₁Another terminal of (1) and a capacitor CS₁One terminal of and an inductor LS₂Are connected at one end, an inductance LS₂Another terminal of (1) and a capacitor CS₂One terminal of and an inductor LS₃One end of the inductor is connected, and so on, the inductor LS_n-1Another terminal of (1) and a capacitor CS_n-1One terminal of and an inductor LS_nAre connected to one end of, and a final inductor LS_nAnd capacitor CS_nOne end of the on-chip capacitors is connected, and the other ends of all the on-chip capacitors are connected with the ground of the circuit; and each on-chip capacitor and the inductor with the same subscript form a time delay unit, and each time delay unit is connected into a single-end low-pass filter form. According to actual requirements, the number of units of the on-chip delay line can be adjusted correspondingly. The input end IS of the single-ended on-chip time delay line provides a radio frequency input signal, and the output signal of the single-ended on-chip time delay line comprises OS₀、OS₁、OS₂、OS₃、OS₄、……OS_n-3、OS_n-2、OS_n-1、OS_nN +1 in total, the output signals are respectively an original input signal and a signal after n sections of time delay, the position of the output signal is positioned at a port of the inductor, and the OS₀Located in the inductor LS₁One end of, OS₁Located in the inductor LS₁The other end of (1), OS₂Located in the inductor LS₂The other end of (1), and so on, OS_nLocated in the inductor LS_nAnother end of (3), on-chip resistance RS₀Connected to the end of the delay line and connected to the OS_nAnd the other end is grounded. The resistance RS₀Is equal to the characteristic impedance value calculated from the delay line inductance and capacitance values. The parameter values of the inductor and the capacitor on the delay line are specifically adjusted according to the stepping parameters of the delay line. The output signal of a cell being delayed by a time interval TD in comparison with the input signal of the cell for each pass through the cell, e.g. OS₁Phase contrast OS₀Time delay TD, OS₂Phase contrast OS₁Time delay TD, OS₃Phase contrast OS₂Time delay TD, and so on, and finally OS_nPhase contrast OS₀Delay n TD. Wherein n represents the number of the single-ended delay line delay units, and n is more than or equal to 1.

Fig. 2 is a schematic diagram of a switched capacitor array structure used for the single-ended delay line. The on-chip adjustable capacitor CS₀，CS₁，CS₂，CS₃，CS₄，……CS_n-2，CS_n-1，CS_nAre all switched capacitor arrays controlled by N-type metal-oxide-semiconductor field effect transistors, and the switched capacitor arrays comprise on-chip capacitors CSA₀、CSA₁、CSA₂、CSA₃、CSA₄、……、CSA_mNMOS transistor MS₁、MS₂、MS₃、MS₄、……、MS_mM is determined by the capacitance resolution required for the actual circuit. Capacitor CSA₁And transistor MS₁Of the transistor MS₁The source of the first switch is grounded to form a 1 st switch branch circuit and a capacitor CSA₂And transistor MS₂Of the transistor MS₂The source electrode of the capacitor is grounded to form a 2 nd switching branch circuit, and so on, and the capacitor CSA_mAnd transistor MS_mOf the transistor M_mThe source of (b) is grounded to form an mth switch branch. Fixed capacitor CSA₀Has one end grounded, and a capacitor CSA₀The other end of the capacitor is respectively connected with a capacitor CSA₁、CSA₂、CSA₃、CSA₄、……、CSA_mIs connected to the other end of the port, the port is marked as OS. Transistor MS₁Is connected with the control signal GS₁Transistor MS₂Is connected with the control signal GS₂And so on, transistor MS_mIs connected with the control signal GS_mThe port OS corresponds to the OS of the single-ended delay line₀、OS₁、OS₂、……、OS_n. Wherein m represents the number of switch branches of the switched capacitor array of the single-ended delay line, and m is more than or equal to 1.

The capacitance values of each switch branch of the switch capacitor array controlled by the transistors are arranged in an equal ratio series with the common ratio of 2. Such as CSA₂A capacitance value of CSA ₁2 times of capacitance value, CSA₃A capacitance value of CSA ₂2 times of capacitance value, CSA₄A capacitance value of CSA ₃2 times of capacitance value, and so on. The capacitance value connected to the delay line is determined by the gate signal of the transistor of the capacitor array. In one possible design, the capacitance values of each switching branch of the switched capacitor array are the same. In one possible design, the capacitors of the switched capacitor array are arranged in a combination of capacitors arranged in an equal ratio array with a branch capacitance value of a common ratio of 2 and capacitors with equal branch capacitance values. Taking the first branch as an example, when GS is₁When high, the transistor is turned on and the transistor MS is turned off₁The drain is pulled to ground, MS₁In the linear region working state, the capacitor CSA₁Accessing a circuit; when GS is present₁When low level is connected, the transistor is turned off, MS₁In the working state of cut-off region, the capacitor CSA₁No circuit is switched in. The capacitance value of the access circuit can be controlled by selectively connecting the grid of the transistor of each switch branch to high level or low level.

Fig. 3 is a schematic diagram of a layout structure of an inductor used in the single-ended delay line. The on-chip inductor is an on-chip octagonal spiral inductor, the winding mode of the inductor is a regular octagon, the inductor main body uses the thickest layer of metal allowed by the process, the inductor adopts a left-in right-out structure to reduce the connection distance of two cascaded inductors, and the number of turns and the inner diameter of a coil are adjusted step by step according to the required time delay; output signal OS on the left side of the inductor_k-1And the right side is the output signal OS_kWherein n is more than or equal to k and more than or equal to 1.

Fig. 4 shows a differential on-chip delay line structure according to the present invention. The differential on-chip time delay line structure comprises an on-chip capacitor CD₀、CD₁、CD₂、CD₃、CD₄、……CD_q-2、CD_q-1、CD_qOn-chip inductor LDP₁、LDP₂、LDP₃、LDP₄、……、LDP_q-2、LDP_q-1、LDP_q、LDN₁、LDN₂、LDN₃、LDN₄、……LDN_q-2、LDN_q-1、LDN_qAnd on-chip resistance RD₀(ii) a Inductor LDP₁One end of (A) andcapacitor CD₀One end of which is connected with an inductor LDP₁Another terminal of (1) and a capacitor CD₁And an inductor LDP₂One end of which is connected with an inductor LDP₂Another terminal of (1) and a capacitor CD₂And an inductor LDP₃One end of the inductor LDP is connected, and the like are repeated_q-1Another terminal of (1) and a capacitor CD_q-1And an inductor LDP_qOne end of the two ends are connected; inductor LDN₁One terminal of and capacitor CD₀Is connected with the other end of the inductor LDN₁Another terminal of (1) and a capacitor CD₁Another end of (1) and an inductor LDN₂One end of which is connected with an inductor LDN₂Another terminal of (1) and a capacitor CD₂Another end of (1) and an inductor LDN₃One end of the inductor LDN is connected, and the like are repeated_q-1Another terminal of (1) and a capacitor CD_q-1Another end of (1) and an inductor LDN_qAre connected at one end to a CD₁、LDP₁、LDN₁Forming a time delay unit and so on. The delay line structure on the differential chip comprises q delay units, and each delay unit is connected into a differential low-pass filter form through a circuit. According to actual requirements, the number of units of the on-chip delay line can be adjusted correspondingly. The differential on-chip delay line inputs IDP, IDN provide differential RF input signals, and the differential on-chip delay line output signals include (ODP)₀，ODN₀)、(ODP₁，ODN₁)、(ODP₂，ODN₂)、(ODP₃，ODN₃)、……、(ODP_q-2，ODN_q-2)、(ODP_q-1，ODN_q-1)、(ODP_q，ODN_q)，ODP₀Located in the inductor LDP₁One end of, ODN₀On the inductor LDN₁One end of, ODP₁Located in the inductor LDP₁The other end of (1), ODN₁On the inductor LDN₁The other end of (1), ODP₂Located in the inductor LDP₂The other end of (1), ODN₂On the inductor LDN₂The other end of (3), by analogy, ODP_qLocated in the inductor LDP_qThe other end of (1), ODN_qOn the inductor LDN_qAnd the other end of the same. On-chip resistor RD₀Connected to the end of the delay line and connected to the ODP_qAnd the other end is connected with ODN_q. Resistance RD₀Is equal to the characteristic impedance value calculated from the delay line inductance and capacitance values. The parameter values of the inductor and the capacitor on the delay line are specifically adjusted according to the stepping parameters of the delay line. The output signal of a cell is delayed by a time interval TD in comparison with the input signal of the cell for each pass through the cell, e.g. (ODP)₁，ODN₁) Phase comparison (ODP)₀，ODN₀) Time delay TD, (ODP)₂，ODN₂) Phase comparison (ODP)₁，ODN₁) Time delay TD, (ODP)₃，ODN₃) Phase comparison (ODP)₂，ODN₂) Time delay TD, and so on, and finally (ODP)_q，ODN_q) Phase comparison (ODP)₀，ODN₀) Delay q TD. Wherein q represents the number of delay units of the differential delay line, and q is more than or equal to 1.

Fig. 5 is a schematic diagram of a switched capacitor array structure used for the differential delay line. The on-chip capacitor CD of the differential time delay line₀、CD₁、CD₂、CD₃、CD₄、……CD_q-2、CD_q-1、CD_qAre all controlled by N-type metal-oxide-semiconductor field effect transistor, and comprise on-chip capacitors CDA₀、CDA₁₁、CDA₁₂、CDA₂₁、CDA₂₂、CDA₃₁、CDA₃₂、CDA₄₁、CDA₄₂、……、CDA_p1、CDA_p2NMOS transistor MD₁₁、MD₁₂、MD₁₃、MD₂₁、MD₂₂、MD₂₃、MD₃₁、MD₃₂、MD₃₃、MD₄₁、MD₄₂、MD₄₃、……、MD_p1、MD_p2、MD_p3P is determined by the capacitance resolution required for the actual circuit. Capacitor CDA₁₁And transistor MD₁₁，MD₁₂Transistor MD₁₂The source of (2) is grounded; capacitor CDA₁₂And transistor MD₁₁Source electrode, MD₁₃Transistor MD₁₃The source electrode of the capacitor is grounded to form a 1 st switch branch circuit, and so on, and the capacitor CDA_p1And transistor MD_p1，MD_p2Transistor MD_p2The source of (2) is grounded; capacitor CDA_p2And transistor MD_p1Source electrode, MD_p3Transistor MD_p3The source of which is grounded to form the p-th switching branch. Fixed capacitance CDA₀One terminal of each of which is connected to the capacitor CDA₁₁、CDA₂₁、CDA₃₁、CDA₄₁、……、CDA_p1Is connected to the other end of the port, the port is labeled ODP. Fixed capacitance CDA₀Respectively with the other end of the capacitor CDA₁₂、CDA₂₂、CDA₃₂、CDA₄₂、……、CDA_p2Is connected to the other end of the port, which is labeled ODN. Transistor MD₁₁Is connected with a control signal GD₁₁，MD₁₂Is connected with a control signal GD₁₂，MD₁₃Is connected with a control signal GD₁₃By analogy, transistor MD_p1Is connected with a control signal GD_p1，MD_p2Is connected with a control signal GD_p2，MD_p3Is connected with a control signal GD_p3. ODP of port ODP corresponding to differential delay line₀、ODP₁、ODP₂、……、ODP_qODN with port ODN corresponding to differential delay line₀、ODN₁、ODN₂、……、ODN_q. The two capacitors in each switch branch have equal capacitance value, CDA₁₁And CDA₁₂Equal capacitance value, CDA₂₁And CDA₂₂Equal capacitance, and so on, CDA_p1And CDA_p2The capacitance values are equal. Wherein p represents the number of switch branches of the switched capacitor array of the differential delay line, and p is more than or equal to 1.

In one possible design, the capacitance values of each switch branch of the switch capacitor array controlled by the transistor are arranged in an equal ratio array with a common ratio of 2. Such as CDA₂₁、CDA₂₂A capacitance value of CDA₁₁、CDA ₁₂2 times the capacitance value, CDA₃₁、CDA₃₂A capacitance value of CDA₂₁、CDA ₂₂2 times the capacitance value, CDA₄₁、CDA₄₂A capacitance value of CDA₃₁、CDA ₃₂2 times of capacitance value, and so on. The capacitance value connected to the delay line is determined by the gate signal of the transistor of the capacitor array. In one possible design, the capacitance values of each switching branch of the switched capacitor array are the same. In one possible design, the capacitors of the switched capacitor array are arranged in a combination of capacitors arranged in an equal ratio array with a branch capacitance value of a common ratio of 2 and capacitors with equal branch capacitance values. Taking the first branch as an example, when GD₁₁、GD₁₂And GD₁₃When high level is connected, the transistor is conducted and the transistor MD is connected₁₁Drain electrode is MD₁₂Pulled to ground, transistor MD₁₁Source electrode quilt MD₁₃Pulled to the ground, MD₁₁In the linear region, the capacitor CDA₁₁And CDA₁₂Accessing a circuit; when GD is turned on₁₁、GD₁₂And GD₁₃When low level is connected, the transistor is turned off, MD₁₁In the off-region operating state, the capacitor CDA₁₁And CDA₁₂No circuit is switched in. The capacitance value of the access circuit can be controlled by selectively connecting the grid of each unit transistor to high level or low level.

In one possible design, the 2 nd and 3 rd transistors MD of each branch₁₂，MD₁₃，MD₂₂，MD₂₃，MD₃₂，MD₃₃Etc. are not grounded but are connected to a fixed level value. Using the first branch as an example, GD₁₂And GD₁₃Initial high level, MD₁₁Is pulled to a fixed level when GD is performed₁₁At high level, MD₁₁Operating in the linear region when GD₁₁At low level, MD₁₁Operating in the deep cut-off region. In one possible design, the 2 nd and 3 rd transistors MD of each branch₁₂，MD₁₃，MD₂₂，MD₂₃，MD₃₂，MD₃₃Each being replaced by a resistor, transistor MD₁₁，MD₂₁，MD₃₁The drain and source potentials of the etc. are always pulled to ground or a fixed level value through the resistor. In each possible design, the control of each branch of the switched capacitor arrayThe manufacturing mode is consistent with that of the 1 st branch.

Fig. 6 is a schematic diagram of a layout structure of an inductor used in the differential delay line. The on-chip inductor LDP of the differential time delay line₁、LDP₂、LDP₃、LDP₄、……、LDP_q-2、LDP_q-1、LDP_q、LDN₁、LDN₂、LDN₃、LDN₄、……LDN_q-2、LDN_q-1、LDN_qThe inductor is an on-chip octagonal spiral inductor which is mutually coupled, and the inductor main body uses the thickest layer of metal allowed by the process; the inductors adopt a structure of left-in and right-out to reduce the connection distance of the two groups of cascade inductors; the number of turns and the inner diameter of the coil are adjusted step by step according to the required time delay, the LDP inductor and the LDN inductor with the same subscript number use a reverse coupling structure, the winding directions of the two inductors are opposite, and the left side of the inductor is an output signal (ODP)_k-1，ODN_k-1) The right side is the output signal (ODP)_k，ODN_k) Wherein q is more than or equal to k and more than or equal to 1.

Fig. 7 is a schematic structural diagram of the single-ended delay selection network. The single-ended delay selection network comprises an N-type metal-oxide-semiconductor field effect transistor (MSN)₀₁、MSN₀₂、MSN₁₁、MSN₁₂、MSN₂₁、MSN₂₂、MSN₃₁、MSN₃₂、……、MSN_(n-2)1、MSN_(n-2)2、MSN_(n-1)1、MSN_(n-1)2、MSN_n1、MSN_n2Wherein, MSN₀₁，MSN₀₂Grouped into one group, connected into cascode configuration, MSN₀₁As a common source, MSN₀₂As a common-gate tube, and so on, MSN_n1，MSN_n2Grouped into one group, connected into cascode configuration, MSN_n1As a common source, MSN_n2And the NMOS tubes are used as common-gate tubes to form n +1 groups of common-source common-gate structure NMOS tubes. The n +1 groups of the cascode NMOS tubes respectively correspond to n +1 OUTPUT signals of the single-ended delay line, the drains of the common-gate tubes of the n +1 groups of the cascode NMOS tubes are connected together and are recorded as an OUTPUT end OUTPUT, and the OUTPUT end is an OUTPUT end of the single-ended delay selection network. When single end is openedExtended n +1 output signals OS₀、OS₁、OS₂、……、OS_nAnd the grid electrodes are respectively connected with the grid electrodes of the common source transistors of the n +1 groups of NMOS transistors. The grid of the common grid tube of each group of NMOS tubes is connected with a control signal, and the common grid tube MSN₀₂Is connected with the control signal GSN₀₂Common gate tube MSN₁₂Is connected with the control signal GSN₁₂By analogy, common-gate tube MSN_n2Is connected with the control signal GSN_n2. OS output when required₀When the signal is in, the grid electrode GSN of the common grid tube of the 0 th group NMOS tube₀₂Connect high level to MSN₀₂Conducting, common grid GSN of NMOS tubes of other groups₁₂、GSN₂₂、GSN₃₂、……、GSN_n2Grounding the MSN₁₂、MSN₂₂、MSN₃₂、……、MSN_n2Turning off; OS output when required₁When the signal is in (1), the grid electrode GSN of the common grid tube of the NMOS tube in the 1 st group₁₂Connect high level to MSN₁₂Conducting, common grid GSN of NMOS tubes of other groups₀₂、GSN₂₂、GSN₃₂、……、GSN_n2Grounding the MSN₀₂、MSN₂₂、MSN₃₂、……、MSN_n2Turning off; and so on, when the OS is required to be output_kWhen the signal is in the state of (1), the grid electrode GSN of the common grid tube of the kth group NMOS tube_k2Connect high level to MSN_k2And conducting, grounding the grid electrodes of the common grid tubes of the rest groups of NMOS tubes, and turning off the common grid tubes. Wherein n is more than or equal to k and more than or equal to 1.

Fig. 8 is a schematic structural diagram of the differential delay selection network. The differential time delay selection network comprises an N-type metal-oxide-semiconductor field effect transistor (MDN)₀₁、MDN₀₂、MDN₀₃、MDN₀₄、MDN₁₁、MDN₁₂、MDN₁₃、MDN₁₄、……、MDN_(q-1)1、MDN_(q-1)2、MDN_(q-1)3、MDN_(q-1)4、MDN_q1、MDN_q2、MDN_q3、MDN_q4Wherein, MDN₀₁，MDN₀₂，MDN₀₃，MDN₀₄Grouped into one group, MDN₀₁，MDN₀₂Connected in cascode configuration, MDN₀₃，MDN₀₄Connected in a cascode configuration, and so on, MDN_q1，MDN_q2，MDN_q3，MDN_q4Grouped into one group, MDN_q1，MDN_q2Connected in cascode configuration, MDN_q3，MDN_q4NMOS tubes connected into a cascode structure and having q +1 groups of differential cascode structures, corresponding to q +1 groups of output signals of the differential delay lines, respectively, and MDN₀₂、MDN₁₂、MDN₂₂、……、MDN_(q-2)2、MDN_(q-1)2、MDN_q2Are connected together and are denoted as OUTPUT, MDN₀₄、MDN₁₄、MDN₂₄、……、MDN_(q-2)4、MDN_(q-1)4、MDN_q4Are connected together and are denoted as OUTPUTN, OUTPUTP and OUTPUTN are differential output terminals of the differential delay selection network, the q +1 set of output signals (ODP) of the differential delay line₀，ODN₀)、(ODP₁，ODN₁)、(ODP₂，ODN₂)、……、(ODP_q，ODN_q) Respectively inputting the grid electrodes of each pair of common source tubes of the q +1 group of NMOS tubes. A pair of common-gate transistors of each group of NMOS transistors are connected with control signals and MDN₀₂Is connected with a control signal GDN₀₂Common gate tube MDN₀₄Is connected with a control signal GDN₀₄Common gate tube MDN₁₂Is connected with a control signal GDN₁₂Common gate tube MDN₁₄Is connected with a control signal GDN₁₄By analogy, common-grid tube MDN_q2Is connected with a control signal GDN_q2Common gate tube MDN_q4Is connected with a control signal GDN_q4. When output is required (ODP)₀，ODN₀) When the signal is in, the grid electrode GDN of the common grid tube of the 0 th group of NMOS tubes₀₂、GDN₀₄Connect high level to MDN₀₂、MDN₀₄Conducting, the grid GDN of the common grid tube of the other NMOS tubes₁₂、GDN₁₄、GDN₂₂、GDN₂₄、……、GDN_q2、GDN_q4Grounding the MDN₁₂、MDN₁₄、MDN₂₂、MDN₂₄、……、MDN_q2、MDN_q4Turning off; when output is required (ODP)₁，ODN₁) Is sent toDuring the process, the grid GDN of the common grid tube of the 1 st group of NMOS tubes₁₂、GDN₁₄Connect high level to MDN₁₂、MDN₁₄Conducting, the grid GDN of the common grid tube of the other NMOS tubes₀₂、GDN₀₄、GDN₂₂、GDN₂₄、……、GDN_q2、GDN_q4Grounding the MDN₀₂、MDN₀₄、MDN₂₂、MDN₂₄、……、MDN_q2、MDN_q4Turning off; analogize in turn, when the output is required (ODP)_k，ODN_k) When the signal is in, the grid electrode GDN of the common grid tube of the kth group of NMOS tubes_k2、GDN_k4Connect high level to MDN_k2、MDN_k4And conducting, grounding the grid electrodes of the common grid tubes of the rest groups of NMOS tubes, and turning off the common grid tubes. Wherein, q is more than or equal to k and more than or equal to 1.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and although the invention has been described in detail with reference to the foregoing examples, it will be apparent to those skilled in the art that various changes in the form and details of the embodiments may be made and equivalents may be substituted for elements thereof. All modifications, equivalents and the like which come within the spirit and principle of the invention are intended to be included within the scope of the invention.

Claims

1. A time delay line on a chip based on a selection network is characterized by comprising a single-ended time delay line on the chip and a corresponding single-ended time delay selection network, a differential time delay line on the chip and a corresponding differential time delay selection network;

the on-chip adjustable capacitor CS₀，CS₁，CS₂，CS₃，CS₄，……CS_n-2，CS_n-1，CS_nAre all switched capacitor arrays controlled by N-type metal-oxide-semiconductor field effect transistors, and the switched capacitor arrays comprise on-chip capacitors CSA₀、CSA₁、CSA₂、CSA₃、CSA₄、……、CSA_mNMOS transistor MS₁、MS₂、MS₃、MS₄、……、MS_mCapacitor CSA₁And transistor MS₁Of the transistor MS₁The source of the first switch is grounded to form a 1 st switch branch and a capacitor CSA₂And transistor MS₂Of the transistor MS₂The source electrode of the capacitor is grounded to form a 2 nd switching branch circuit, and so on, and the capacitor CSA_mAnd transistor MS_mOf the transistor M_mThe source of the first switch is grounded to form an mth switch branch; fixed capacitor CSA₀Has one end grounded, and a capacitor CSA₀The other end of the capacitor is respectively connected with a capacitor CSA₁、CSA₂、CSA₃、CSA₄、……、CSA_mIs connected with the other end of the port, and the port is marked as an OS; transistor MS₁Is connected with the control signal GS₁Transistor MS₂Is connected with the control signal GS₂And so on, transistor MS_mIs connected with the control signal GS_mThe port OS corresponds to the OS of the single-ended delay line₀、OS₁、OS₂、……、OS_n(ii) a Wherein m represents the number of switch branches of the switched capacitor array of the single-ended delay line, and m is more than or equal to 1;

the on-chip inductor is an on-chip octagonal spiral inductor, the winding mode of the inductor is a regular octagon, the inductor main body uses the thickest layer of metal allowed by the process, the inductor adopts a left-in right-out structure to reduce the connection distance of two cascaded inductors, and the number of turns and the inner diameter of a coil are adjusted step by step according to the required time delay; output signal OS on the left side of the inductor_k-1And the right side is the output signal OS_kWherein n is more than or equal to k and more than or equal to 1;

the on-chip inductor LDP of the differential time delay line₁、LDP₂、LDP₃、LDP₄、……、LDP_q-2、LDP_q-1、LDP_q、LDN₁、LDN₂、LDN₃、LDN₄、……LDN_q-2、LDN_q-1、LDN_qThe inductor main bodies are all mutually coupled on-chip octagonal spiral inductors, and use the thickest layer of metal allowed by the process; the inductors adopt a structure of left-in and right-out to reduce the connection distance of the two groups of cascade inductors; the number of turns and the inner diameter of the coil are adjusted step by step according to the required time delay, the LDP inductor and the LDN inductor with the same subscript number use a reverse coupling structure, the winding directions of the two inductors are opposite, and the left side of the inductor is an output signal (ODP)_k-1，ODN_k-1) The right side is the output signal (ODP)_k，ODN_k) Wherein, q is more than or equal to k and more than or equal to 1;

the single-ended delay selection network comprises an N-type metal-oxide-semiconductor field effect transistor (MSN)₀₁、MSN₀₂、MSN₁₁、MSN₁₂、MSN₂₁、MSN₂₂、MSN₃₁、MSN₃₂、……、MSN_(n-2)1、MSN_(n-2)2、MSN_(n-1)1、MSN_(n-1)2、MSN_n1、MSN_n2Wherein, MSN₀₁，MSN₀₂Are organized into a group and are connected into a common sourceGate structure, MSN₀₁As a common source, MSN₀₂As a common-gate tube, and so on, MSN_n1，MSN_n2Grouped into one group, connected into cascode configuration, MSN_n1As a common source, MSN_n2The NMOS tubes are used as common-gate tubes to form n +1 groups of common-source common-gate structure NMOS tubes; the NMOS tubes of the n +1 groups of cascode structures respectively correspond to n +1 OUTPUT signals of the single-ended delay line, the drains of the common-gate tubes of the n +1 groups of cascode NMOS tubes are connected together and are marked as an OUTPUT end OUTPUT, and the OUTPUT end is the OUTPUT end of the single-ended delay selection network; n +1 output signals OS of a single-ended delay line₀、OS₁、OS₂、……、OS_nThe grid electrodes are respectively connected with the common source tube of the n +1 group of NMOS tubes; the grid of the common grid tube of each group of NMOS tubes is connected with a control signal, and the common grid tube MSN₀₂Is connected with the control signal GSN₀₂Common gate tube MSN₁₂Is connected with the control signal GSN₁₂By analogy, common-gate tube MSN_n2Is connected with the control signal GSN_n2；

2. The select network based on-chip delay line of claim 1, wherein in each switched capacitor array of the single-ended on-chip delay line structure, the capacitance values of each switching branch are arranged in an equal-ratio sequence with a common ratio of 2, and the capacitance value accessed by the delay line is determined by the gate signal of the transistor of each capacitor array.

3. The select network based on-chip delay line of claim 1, wherein in each switched capacitor array of the differential on-chip delay line structure, the capacitance values of each switching branch are arranged in an equal ratio sequence with a common ratio of 2, and the capacitance value accessed by the delay line is determined by the gate signals of the transistors of the capacitor array.

4. The select network based on-chip delay line of claim 2, wherein in each switched capacitor array of the single-ended on-chip delay line structure, when the capacitance value of each switched branch has a limit, the capacitance value of the switched branch exceeding the limit is set to be equal to the maximum branch capacitance value not exceeding the limit.

5. The selection network based on-chip delay line of claim 3, wherein in each switched capacitor array of the differential on-chip delay line structure, when the capacitance value of each switched branch has a limit, the capacitance value of the switched branch exceeding the limit is set to be equal to the maximum branch capacitance value not exceeding the limit.

6. The selection network based on-chip delay line of claim 1, wherein in each switched capacitor array of the differential on-chip delay line structure, the 2 nd and 3 rd transistors MD of each branch circuit_k2、MD_k3Is not grounded but is connected to a fixed level value, wherein q ≧ k ≧ 1.

7. The selection network based on-chip delay line of claim 1, wherein in each switched capacitor array of the differential on-chip delay line structure, the 2 nd and 3 rd transistors MD of each branch circuit_k2、MD_k3Each being replaced by a resistor, MD_k1The drain and source potentials of the transistor are always pulled to the ground or a fixed level value through the resistor, wherein q is more than or equal to k and more than or equal to 1.