CN110189666A - GOA tests circuit, array substrate, display panel and GOA test method - Google Patents
GOA tests circuit, array substrate, display panel and GOA test method Download PDFInfo
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- CN110189666A CN110189666A CN201910462262.2A CN201910462262A CN110189666A CN 110189666 A CN110189666 A CN 110189666A CN 201910462262 A CN201910462262 A CN 201910462262A CN 110189666 A CN110189666 A CN 110189666A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
Abstract
The invention discloses a kind of GOA test circuit, array substrate, display panel and GOA test methods, GOA test circuit is used to test the GOA circuit for including cascade multiple GOA units, at least one in multiple GOA units is with test node, testing circuit includes: at least one test bus, and test bus is electrically connected with testing weld pad；With at least one one-to-one test cell of at least one GOA unit with test node, GOA unit with test node has at least one test node, its corresponding test cell include second level p-wire and with the one-to-one three-level p-wire of test node, two pole p-wires are electrically connected with test bus, three-level p-wire is electrically connected with corresponding test node, when the signal to test node is tested, being electrically connected between three-level p-wire and two pole p-wires is established.The test circuit, it is simple easily to realize, without increasing exposure mask, and display will not be impacted.
Description
Technical field
The present invention relates to GOA display fields, and in particular to a kind of GOA test circuit, array substrate, display panel and GOA
Test method
Background technique
TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor (TFT) display surface
Plate) because it has the characteristics that small size, low power consumption, no radiation, leading position is occupied in current flat panel display market.
With the development of technology, by Gate IC, (Integrated Circuit is integrated more and more TFT-LCD products
Circuit) shift register function it is integrated on a display panel by prior art, to replace original Gate Driver IC's
Effect, referred to as GOA (Gate driver On Array, the driving of array substrate row) technology.GOA product biggest advantage is due to saving
Gate Driver IC has been removed, has been reduced costs, and has reduced the frame of product.Some passes of the GOA product due to the region GOA
Key node signal (such as Input, Output, Reset signal) is there are cascade connection, when some or certain signals of certain a line
When occurring abnormal, the abnormal signal of other rows will lead to, multiple output occur or without output, thus lead to the whole of display panel
The display of body picture is abnormal.For the quick analysis of poor prognostic cause, the signal for testing some key nodes is generally required, including
Input, Output, Reset and PU, PD, PDCN etc. judge bad the reason of occurring with the relevant waveform of synthesis.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.For this purpose, of the invention
One purpose is to propose a kind of GOA test circuit simply easily realized, will not with while realizing to GOA circuit test
The display of display panel is impacted.
Second object of the present invention is to propose a kind of array substrate.
Third object of the present invention is to propose a kind of display panel.
Fourth object of the present invention is to propose a kind of GOA test method.
In order to achieve the above objectives, first aspect present invention embodiment proposes a kind of GOA test circuit, for display surface
GOA circuit in the array substrate of plate is tested, and the GOA circuit includes cascade multiple GOA units, the multiple GOA
At least one in unit is arranged in the multiple GOA unit region with test node, the GOA test circuit,
The GOA test circuit includes: at least one test bus, and the test bus is welded with the test that the display panel is arranged in
Disk electrical connection；It is described that there is survey at least one one-to-one test cell of at least one GOA unit with test node
The GOA unit for trying node has at least one test node, and the corresponding test cell of the GOA unit is surveyed including at least one second level
Try line and with the one-to-one at least one three-level p-wire of at least one described test node, two pole p-wire with it is described
Bus electrical connection is tested, the three-level p-wire is electrically connected with corresponding test node, wherein in the letter to the test node
When number being tested, being electrically connected between the three-level p-wire and two pole p-wire is established.
GOA according to an embodiment of the present invention tests circuit, total by the way that test is arranged in multiple GOA unit regions
Line, second level p-wire and three-level p-wire, and two pole p-wires are electrically connected with test bus, three-level p-wire and GOA unit
Test node electrical connection need to only establish the corresponding three-level test of the test node when the signal to test node is tested
Being electrically connected between line and two pole p-wires.The GOA tests circuit, simple easily to realize, without increasing exposure mask, and will not be right
Display impacts.
In addition, GOA test circuit according to the above embodiment of the present invention can also have following additional technical feature:
In one embodiment of the invention, the test bus and the three-level p-wire prolong first direction extension,
The second level p-wire prolongs second direction extension, wherein the first direction is the column direction of the multiple GOA unit, described
Second direction and the first direction are arranged in a crossed manner.
In one embodiment of the invention, each GOA unit includes: first film transistor, the first film
The grid of transistor and drain electrode are connected with signal input part, and source electrode is connected with first node；Second thin film transistor (TFT), described
The grid of two thin film transistor (TFT)s is connected with reset signal input terminal, and drain electrode is connected with the first node, and source electrode is straight with low level
Signal source is flowed to be connected；The grid of third thin film transistor (TFT), the third thin film transistor (TFT) is connected with the first node, drain electrode with
Clock signal input terminal is connected, and source electrode is connected with signal output end, wherein the signal output end is corresponding to effective display area
Scan line be connected；The grid of 5th thin film transistor (TFT), the 5th thin film transistor (TFT) is connected with second node, drain electrode and first
High level DC signal source is connected, and source electrode is connected with third node；6th thin film transistor (TFT), the grid of the 6th thin film transistor (TFT)
Pole is connect with the first node, and drain electrode is connect with the third node, and source electrode is connected with the low level DC signal source；The
The grid of eight thin film transistor (TFT)s, the 8th thin film transistor (TFT) is connect with the first node, drain electrode and the second node phase
Even, source electrode is connected with the low level DC signal source；9th thin film transistor (TFT), the grid of the 9th thin film transistor (TFT) and leakage
Extremely it is connected with the first high level DC signal source, source electrode is connected with the second node；Tenth thin film transistor (TFT), it is described
The grid of tenth thin film transistor (TFT) is connect with the third node, and drain electrode is connected with the first node, source electrode and the low electricity
Straight flow signal source is connected；11st thin film transistor (TFT), grid and the third node phase of the 11st thin film transistor (TFT)
Even, drain electrode is connected with the signal output end, and source electrode is connected with the low level DC signal source；12nd thin film transistor (TFT),
The grid of 12nd thin film transistor (TFT) is connected with fourth node, and drain electrode is connected with the second high level DC signal source, source electrode
It is connected with the 5th node；The grid of 13rd thin film transistor (TFT), the 13rd thin film transistor (TFT) is connect with the first node,
Drain electrode is connect with the 5th node, and source electrode is connected with the low level DC signal source；14th thin film transistor (TFT), described
The grid of 14 thin film transistor (TFT)s is connect with the first node, and drain electrode is connected with the fourth node, source electrode and the low electricity
Straight flow signal source is connected；15th thin film transistor (TFT), the grid of the 15th thin film transistor (TFT) and drain electrode are with described the
Two high level DC signal sources are connected, and source electrode is connected with the fourth node；16th thin film transistor (TFT), the 16th film
The grid of transistor is connect with the 5th node, and drain electrode is connected with the first node, and source electrode and the low level direct current are believed
Number source is connected；The grid of 17th thin film transistor (TFT), the 17th thin film transistor (TFT) is connected with the 5th node, drain electrode with
The signal output end is connected, and source electrode is connected with the low level DC signal source；Wherein, the test node of GOA unit includes
The signal input part, the signal output end, the first node, the second node, the third node, the described 4th
One or more of node and the 5th node.
In one embodiment of the invention, the item number of the test bus is two, and each test cell includes: four
Second level p-wire, every two second level p-wires form one group, and two groups of second level p-wires are separately positioned on corresponding GOA unit
Upper and lower two sides, and one in two second level p-wires being disposed over is electrically connected with two one tested in bus, if
Another set in two second level p-wires above is electrically connected with two another tested in bus, is arranged below
One in two second level p-wires is electrically connected with two one tested in bus, two be arranged below second level p-wire
In another with two test buses in another be electrically connected；Five three-level p-wires, the corresponding signal input part, institute
It states signal output end, the first node, the second node and the third node and a three-level p-wire is respectively set；Its
In, it is tested to any one test node in the signal input part, the signal output end, the first node
When, it establishes between the corresponding three-level p-wire of the test node and two second level p-wires being arranged in below the GOA unit
Electrical connection establish the survey when testing any one test node in the second node and the third node
Being electrically connected between the corresponding three-level p-wire of examination node and two second level p-wires being arranged in above the GOA unit.
In one embodiment of the invention, corresponding two test cells of two adjacent GOA units share one group two
Grade p-wire.
In one embodiment of the invention, the circuit board line of the GOA circuit and the test circuit passes through two layers
Metal layer is realized, wherein second level p-wire and test bus use same layer metal, are electrically connected between the two by connection cabling realization
It connects, the connection cabling and the second level p-wire and the test bus use different layers metal, the connection cabling difference
It is connect with the second level p-wire and the test bus by via hole, three-level p-wire and second level p-wire are using different layers gold
Belong to, three-level p-wire and test node use different layers metal, pass through between the three-level p-wire and corresponding test node
Via hole electrical connection.
In order to achieve the above objectives, second aspect of the present invention embodiment proposes a kind of array substrate, comprising: cascade multiple
GOA unit；And the GOA of above-described embodiment tests circuit.
The array substrate of the embodiment of the present invention tests circuit using above-mentioned GOA, can be realized the test to GOA circuit,
And simple easily realization, without increasing exposure mask, display will not be impacted.
In order to achieve the above objectives, third aspect present invention embodiment proposes a kind of display panel, comprising: color membrane substrates；
And the array substrate of above-described embodiment, the array substrate are oppositely arranged with the color membrane substrates.
The display panel of the embodiment of the present invention can be realized the test to GOA circuit using above-mentioned array substrate, and
It is simple easily to realize, without increasing exposure mask, display will not be impacted.
In order to achieve the above objectives, fourth aspect present invention embodiment proposes a kind of GOA test method, for display surface
GOA circuit in the array substrate of plate is tested, and the GOA circuit includes being arranged in array and cascade multiple GOA units,
At least one in the multiple GOA unit is with test node, and the GOA test method is the following steps are included: described more
A at least one test bus of GOA unit region setting, and establish the test bus and be arranged in the display panel
Testing weld pad between electrical connection；It is arranged in the multiple GOA unit region and at least one is with test node
At least one one-to-one test cell of GOA unit, and in survey corresponding with having the GOA unit of at least one test node
It tries in unit, at least one second level p-wire of setting and at least one corresponding described test node are arranged at least one three-level and test
Line, wherein two pole p-wire is electrically connected with the test bus, and the three-level p-wire is electrically connected with corresponding test node
It connects；When the signal to test node is tested, being electrically connected between the three-level p-wire and two pole p-wire is established
It connects.
GOA test method according to an embodiment of the present invention, it is total by the way that test is arranged in multiple GOA unit regions
Line, second level p-wire and three-level p-wire, and two pole p-wires are electrically connected with test bus, three-level p-wire and GOA unit
Test node electrical connection need to only establish the corresponding three-level test of the test node when the signal to test node is tested
Being electrically connected between line and two pole p-wires.The GOA test method, it is simple easily to realize, without increasing exposure mask, and will not be right
Display impacts.
In addition, GOA test method according to the above embodiment of the present invention can also have the following additional technical features:
In one embodiment of the invention, synchronization is only to the signal of a test node in the GOA circuit
It is tested, wherein after completing the signal testing of a test node, the signal of another test node is tested
When, after cutting off being electrically connected between the corresponding three-level p-wire of one test node and two pole p-wires, resettle described
Being electrically connected between the corresponding three-level p-wire of another test node and two pole p-wires.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the GOA test circuit of the embodiment of the present invention；
Fig. 2 is the structural schematic diagram of the GOA circuit of an example of the present invention；
Fig. 3 is the structural schematic diagram of the GOA test circuit of an example of the present invention；
Fig. 4 is the structural schematic diagram of another exemplary GOA test circuit of the present invention；
Fig. 5 is the structural block diagram of the array substrate of the embodiment of the present invention；
Fig. 6 is the structural block diagram of the display panel of the embodiment of the present invention；
Fig. 7 is the flow chart of the GOA test method of the embodiment of the present invention.
Specific embodiment
Due to liquid crystal display in the state of lighting due to there is CF (Color Lilter, colored filter) substrate,
It realizes the test of above-mentioned key node signal, need to generally pry open Local C F substrate, the region GOA for exposing TFT substrate can just carry out
Test, referred to as sled angle.But the region GOA is easily caused to cause to show extremely and can not divide to scuffing due to prying open CF substrate
Analysis is that GOA undesirable initial row occurs especially for the intermediate region of large scale display panel or display panel, is difficult to prize
It opens CF substrate and ensures not scratch and show normal.Based on this, the present invention proposes a kind of GOA test circuit, array substrate, display
Panel and GOA test method.
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
Below with reference to the accompanying drawings GOA test circuit, array substrate, display panel and the GOA test of the embodiment of the present invention are described
Method.
Fig. 1 is the structural schematic diagram of GOA test circuit according to an embodiment of the invention.
In this embodiment, GOA tests circuit for testing the GOA circuit in the array substrate of display panel.
As shown in Figure 1, GOA circuit includes cascade multiple GOA units, at least one in multiple GOA units with test node 1,
For example, it may be each GOA unit includes at least one test node 1.GOA tests circuit and is arranged in multiple GOA unit institutes
In the zone, it includes: at least one test bus 101 and mono- at least one GOA with test node 1 that GOA, which tests circuit,
At least one first one-to-one test cell.
Wherein, test bus 101 is electrically connected with the testing weld pad 104 that display panel is arranged in；With test node 1
GOA unit has at least one test node, and the corresponding test cell of the GOA unit includes at least one second level p-wire 102
With at least one one-to-one at least one three-level p-wire 103 of test node 1, two pole p-wires 102 and test bus
101 electrical connections, three-level p-wire 103 are electrically connected with corresponding test node.
Optionally, in circuit board wiring where testing circuit and GOA circuit to GOA, the starting of bus 101 will can be tested
The testing weld pad 104 being connected to outside the CF substrate of display panel is held, to facilitate wiring.Certainly, the starting point for testing bus 101 can
It is arranged close to testing weld pad 104.
In this embodiment, when the signal to test node is tested, three-level p-wire 103 can be established and second level is surveyed
The electrical connection between line 102 is tried, being electrically connected between three-level p-wire 103 and second level p-wire 102 is such as established by laser, into
And the signal of test node 1 can pass sequentially through the survey outside three-level p-wire, second level p-wire and test bus transfer to CF substrate
Test weld disk, in order to which the signal to test node is analyzed.
It should be noted that when the number of the test node 1 in the GOA unit with test node 1 is more than one, and
When the second level p-wire 102 tested in bus 101 or each test cell only has one, test is completed to a test node
Afterwards, the test node that when testing another test node, need to first disconnect the completion test (as disconnected by laser) is corresponding
Three-level p-wire 103 and second level p-wire 102 between be electrically connected, then test to be tested section is currently needed by laser foundation
Being electrically connected between the corresponding three-level p-wire 103 of point and second level p-wire 102.It is surveyed that is, test is only current every time
It is electrically connected between the corresponding three-level p-wire 103 of the test node of examination and second level p-wire 102.
The GOA tests circuit, simple easily to realize, without increasing exposure mask, and will not impact to display.
In one embodiment of the invention, as shown in Figure 1, test bus 101 and three-level p-wire 103 prolong first party
To extension, second level p-wire 102 prolong second direction extension, wherein first direction can be multiple GOA units column direction, second
Direction and first direction are (being such as vertically arranged) arranged in a crossed manner.Circuit board wiring can be facilitated as a result,.
Certainly, the set-up mode for testing bus 101, second level p-wire 102 and three-level p-wire 103 is not limited to above-mentioned side
The signal of test node is transmitted to testing weld pad 104 as long as being able to achieve by formula.
In the embodiment of invention, as shown in Fig. 2, each GOA unit may each comprise: first film transistor M1, first
The grid of thin film transistor (TFT) M1 and drain electrode are connected with signal input part Input, and source electrode is connected with first node PU；Second film
The grid of transistor M2, the second thin film transistor (TFT) M2 are connected with reset signal input terminal Reset, drain electrode and first node PU phase
Even, source electrode is connected with low level DC signal source VSS；Third thin film transistor (TFT) M3, the grid of third thin film transistor (TFT) M3 and
One node PU is connected, and drain electrode is connected with clock signal input terminal CLK, and source electrode is connected with signal output end Output, wherein signal
Output end Output is connected with scan line Scan corresponding in effective display area；5th thin film transistor (TFT) M5, the 5th film crystal
The grid of pipe M5 is connected with second node PDCN1, and drain electrode is connected with the first high level DC signal source VDD1, source electrode and third section
Point PD1 is connected；The grid of 6th thin film transistor (TFT) M6, the 6th thin film transistor (TFT) M6 are connect with first node PU, drain electrode and third
Node PD1 connection, source electrode are connected with low level DC signal source VSS；8th thin film transistor (TFT) M8, the 8th thin film transistor (TFT) M8's
Grid is connect with first node PU, and drain electrode is connected with second node PDCN1, and source electrode is connected with low level DC signal source VSS；The
The grid of nine thin film transistor (TFT) M9, the 9th thin film transistor (TFT) M9 and drain electrode are connected with the first high level DC signal source VDD1,
Source electrode is connected with second node PDCN1；The grid and third node of tenth thin film transistor (TFT) M10, the tenth thin film transistor (TFT) M10
PD1 connection, drain electrode are connected with first node PU, and source electrode is connected with low level DC signal source VSS；11st thin film transistor (TFT)
The grid of M11, the 11st thin film transistor (TFT) M11 are connected with third node PD1, and drain electrode is connected with signal output end Output, source
Pole is connected with low level DC signal source VSS；12nd thin film transistor (TFT) M12, the grid of the 12nd thin film transistor (TFT) M12 and
Four node PDCN2 are connected, and drain electrode is connected with the second high level DC signal source VDD2, and source electrode is connected with the 5th node PD2；Tenth
Three thin film transistor (TFT) M13, the grid of the 13rd thin film transistor (TFT) M13 are connect with first node PU, and drain electrode connects with the 5th node PD2
It connects, source electrode is connected with low level DC signal source VSS；14th thin film transistor (TFT) M14, the grid of the 14th thin film transistor (TFT) M14
Pole is connect with first node PU, and drain electrode is connected with fourth node PDCN2, and source electrode is connected with low level DC signal source VSS；Tenth
The grid of five thin film transistor (TFT) M15, the 15th thin film transistor (TFT) M15 and drain electrode with the second high level DC signal source VDD2 phase
Even, source electrode is connected with fourth node PDCN2；16th thin film transistor (TFT) M16, the grid of the 16th thin film transistor (TFT) M16 and
Five node PD2 connections, drain electrode are connected with first node PU, and source electrode is connected with low level DC signal source VSS；17th film is brilliant
Body pipe M17, the grid of the 17th thin film transistor (TFT) M17 are connected with the 5th node PD2, drain electrode and signal output end Output phase
Even, source electrode is connected with low level DC signal source VSS.Certainly, the source electrode and drain electrode of above-mentioned all thin film transistor (TFT)s is interchangeable
's.
Wherein, the test node 1 of GOA unit may include reset signal input terminal Reset, signal input part Input, signal
Output end Output, first node PU, second node PDCN1, third node PD1, fourth node PDCN2 and the 5th node PD2
One or more of, it may for example comprise signal input part Input, signal output end Output, first node PU, second node
PDCN1, third node PD1, fourth node PDCN2, the 5th node PD2.
In an example of the invention, as shown in figure 3, the item number of test bus 101 is one, each test cell is equal
It include: two second level p-wires 102 and five three-level p-wires 103, two second level p-wires 102 can be separately positioned on accordingly
The two sides up and down of GOA unit, two second level p-wires 102 are electrically connected with test bus 101, corresponding reset signal input terminal
Reset, signal input part Input, signal output end Output, first node PU, second node PDCN1 and third node PD1
A three-level p-wire 103 is respectively set.
Referring to Fig. 3, to reset signal input terminal Reset, signal input part Input, signal output end Output, first
When any one test node in node PU is tested, the corresponding three-level p-wire 103 of the test node is established by laser
Being electrically connected between the second level p-wire 102 being arranged in below GOA unit, to second node PDCN1 and third node PD1
In any one test node when being tested, the corresponding three-level p-wire 103 of the test node and setting are established by laser
The electrical connection between second level p-wire 102 above GOA unit.
Optionally, referring to Fig. 3, to reduce cabling, corresponding two test cells of two adjacent GOA units can share one
Second level p-wire 102.
In another example of the invention, as shown in figure 4, the item number of test bus 101 is two, each test cell
It include: four second level p-wires 102 and five three-level p-wires 103, every two second level p-wires 102 form one group, two groups
Second level p-wire 102 is separately positioned on the two sides up and down of corresponding GOA unit, and two second level p-wires being disposed over
One in 102 is electrically connected with two one tested in bus 101, in two be disposed over second level p-wire 102
Another is electrically connected with two another tested in bus 101, one in two be arranged below second level p-wire 102
Be electrically connected with two one tested in buses 101, another in two be arranged below second level p-wire 102 and two
Test another electrical connection in bus 101；Corresponding reset signal input terminal Reset, signal input part Input, signal output
A three-level p-wire 103 is respectively set in end Output, first node PU, second node PDCN1 and third node PD1；Wherein,
To any of reset signal input terminal Reset, signal input part Input, signal output end Output, first node PU
When test node is tested, establishes the corresponding three-level p-wire 103 of the test node by laser and be arranged under GOA unit
Electrical connection between two second level p-wires 102 of side is surveyed to any of second node PDCN1 and third node PD1
When examination node is tested, establishes the corresponding three-level p-wire 103 of the test node by laser and be arranged above GOA unit
Two second level p-wires 102 between electrical connection.In the example, tests bus 101 and every group of second level p-wire 102 is respectively provided with
Two, be that certain root p-wire occurs breaking and being unable to complete test in technique manufacturing process in order to prevent, and realizes two
The signal of test node is tested simultaneously.
Optionally, referring to fig. 4, to reduce cabling, corresponding two test cells of two adjacent GOA units can share one
Group second level p-wire 102.
It should be noted that Fig. 2 is the structure chart of GOA unit, Fig. 3, Fig. 4 are respectively the TFT plane connection in the region GOA
Figure.Wherein, the VDD1 in Fig. 2 and VDD2 can be used for alternately noise reduction, and be illustrated in Fig. 3, Fig. 4 using VDD, not draw respectively,
That is M12, M13, M14, M15 are the work when replacing noise reduction with M5, M6, M8, M9, Fig. 3,4 are shown using M5, M6, M8, M9
Meaning, is not drawn into M12, M13, M14, M15.In addition, the quantity of CLK generally can be used 4~8, Fig. 2~4 is illustrated using CLK, not
It draws respectively.
Certainly, the setting item number for testing bus 101, second level p-wire 102 and three-level p-wire 103 is not limited to above-mentioned show
Example, for example, it is also possible to be test bus 101 two, second level p-wire 102 4 and three-level p-wire 1,030, etc..
In one embodiment of invention, the circuit board line of GOA circuit and test circuit can pass through two metal layers reality
It is existing, wherein second level p-wire 102 and test bus 101 use same layer metal, are electrically connected between the two by connection cabling realization
It connects, connection cabling and second level p-wire 102 and test bus 101 use different layers metal, and connection cabling is tested with second level respectively
Line 102 is connected with test bus 101 by via hole；Three-level p-wire 103 and the use different layers metal of second level p-wire 102, three
Grade p-wire 103 and test node use different layers metal, pass through via hole between three-level p-wire 103 and corresponding test node
Electrical connection, although at this point, three-level p-wire 103 and second level p-wire 102 have overlapping region, but not generation is short-circuit, and it will not be right
Display impacts.
Certainly, it is not limited to the above example for the cabling mode of second level p-wire 102 and three-level p-wire 103, can basis
It needs to be adjusted.
For example, as shown in Fig. 2, when needing to test certain row PU signal, pass through the three-level p-wire of laser welding PU
It is electrically connected with row second level p-wire realization, PU signal rises by two, three-level p-wire and test bus finally by bus
Beginning is connected to testing weld pad, to realize that signal waveform is tested.
Further, if replacing the test of other node signals, such as need to test PD1 signal, it is only necessary to the PU bis- by before
Grade and three-level p-wire cross spider laser welding position front end laser cutting, again laser welding PD1 node signal second level and three
Grade p-wire crossover location, is connected to testing weld pad by bus starting point, to realize that signal waveform is tested.Other sections of the row
The node signal test method of point signal and other rows is as above, repeats no more.
In conclusion the embodiment of the present invention GOA test circuit, without increasing exposure mask, it is only necessary to Gate, SD, PVX and
Suitably increase p-wire and test via hole on the plates such as ITO, it is simple easily to realize, and display will not be impacted；GOA test electricity
Road has a wide range of application, and can be not only used for TFT-LCD GOA product can also be applied to the GOA product of OLED, can be accurate without prizing angle
Realize the test of whole GOA node signal.
Fig. 5 is the structural block diagram of the array substrate of the embodiment of the present invention.
As shown in figure 5, the array substrate 200 includes: cascade multiple GOA units 210；And as in above-described embodiment
GOA tests circuit 220.
Array substrate according to an embodiment of the present invention is tested circuit using above-mentioned GOA, be can be realized to GOA circuit
Test, and simple easily realization, without increasing exposure mask, will not impact display.
Fig. 6 is the structural block diagram of the display panel of the embodiment of the present invention.
As shown in fig. 6, the display panel 1000 includes: color membrane substrates 300；Such as the array substrate 200 in above-described embodiment,
Array substrate 200 is oppositely arranged with color membrane substrates 300, and the underface of color membrane substrates 300 is such as arranged in.
Display panel according to an embodiment of the present invention can be realized the survey to GOA circuit using above-mentioned array substrate
Examination, and simple easily realization, without increasing exposure mask, will not impact display.
Fig. 7 is the flow chart of GOA test method according to an embodiment of the present invention.
For testing the GOA circuit in the array substrate of display panel, GOA circuit includes the GOA test method
Cascade multiple GOA units, at least one in multiple GOA units is with test node.As shown in fig. 6, GOA test method packet
Include following steps:
S1, at least one test bus of setting in multiple GOA unit regions, and test bus and setting are established aobvious
Show the electrical connection between the testing weld pad of panel.
S2, in multiple GOA unit regions, setting and at least one GOA unit with test node are one-to-one
At least one test cell, and in test cell corresponding with having the GOA unit of at least one test node, setting is at least
At least one three-level p-wire is arranged in one second level p-wire and at least one corresponding test node, wherein two pole p-wires with
Bus electrical connection is tested, three-level p-wire is electrically connected with corresponding test node.
S3 establishes being electrically connected between three-level p-wire and two pole p-wires when the signal to test node is tested
It connects.
In one embodiment of invention, synchronization only surveys the signal of a test node in GOA circuit
Examination, wherein after completing the signal testing of a test node, when testing the signal of another test node, cutting
After being electrically connected between the corresponding three-level p-wire of one test node and two pole p-wires, another test node pair is resettled
Being electrically connected between the three-level p-wire answered and two pole p-wires.
It should be noted that the description of the above-mentioned specific embodiment to GOA test circuit, is equally applicable to of the invention real
Apply the GOA test method of example.
The GOA test method of the embodiment of the present invention, it is simple easily to realize, without increasing exposure mask, and shadow will not be caused to display
It rings.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiment or examples in can be combined in any suitable manner.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect
It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary
The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art
For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with
It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists
Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of
First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below "
One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of GOA tests circuit, tested for the GOA circuit in the array substrate to display panel, the GOA circuit
Including cascade multiple GOA units, at least one in the multiple GOA unit is with test node, which is characterized in that described
GOA tests circuit and is arranged in the multiple GOA unit region, and the GOA test circuit includes:
At least one test bus, the test bus are electrically connected with the testing weld pad that the display panel is arranged in；
It is described that there is test section at least one one-to-one test cell of at least one GOA unit with test node
The GOA unit of point has at least one test node, and the corresponding test cell of the GOA unit includes at least one second level p-wire
With with the one-to-one at least one three-level p-wire of at least one described test node, two pole p-wire and the test
Bus electrical connection, the three-level p-wire is electrically connected with corresponding test node, wherein the signal to the test node into
When row test, being electrically connected between the three-level p-wire and two pole p-wire is established.
2. GOA as described in claim 1 tests circuit, which is characterized in that the test bus and the three-level p-wire are equal
Prolong first direction extension, the second level p-wire prolongs second direction extension, wherein the first direction is that the multiple GOA is mono-
The column direction of member, the second direction and the first direction are arranged in a crossed manner.
3. GOA as described in claim 1 tests circuit, which is characterized in that each GOA unit includes:
First film transistor, the grid of the first film transistor and drain electrode are connected with signal input part, source electrode and the
One node is connected；
The grid of second thin film transistor (TFT), second thin film transistor (TFT) is connected with reset signal input terminal, drain electrode and described the
One node is connected, and source electrode is connected with low level DC signal source；
The grid of third thin film transistor (TFT), the third thin film transistor (TFT) is connected with the first node, drain electrode and clock signal
Input terminal is connected, and source electrode is connected with signal output end, wherein the signal output end and scan line corresponding in effective display area
It is connected；
The grid of 5th thin film transistor (TFT), the 5th thin film transistor (TFT) is connected with second node, drains straight with the first high level
It flows signal source to be connected, source electrode is connected with third node；
The grid of 6th thin film transistor (TFT), the 6th thin film transistor (TFT) is connect with the first node, drain electrode and the third
Node connection, source electrode are connected with the low level DC signal source；
The grid of 8th thin film transistor (TFT), the 8th thin film transistor (TFT) is connect with the first node, drain electrode and described second
Node is connected, and source electrode is connected with the low level DC signal source；
9th thin film transistor (TFT), the grid of the 9th thin film transistor (TFT) and drain electrode with the first high level DC signal source
It is connected, source electrode is connected with the second node；
The grid of tenth thin film transistor (TFT), the tenth thin film transistor (TFT) is connect with the third node, drain electrode and described first
Node is connected, and source electrode is connected with the low level DC signal source；
The grid of 11st thin film transistor (TFT), the 11st thin film transistor (TFT) is connected with the third node, drain electrode with it is described
Signal output end is connected, and source electrode is connected with the low level DC signal source；
The grid of 12nd thin film transistor (TFT), the 12nd thin film transistor (TFT) is connected with fourth node, drain electrode and the second high electricity
Straight flow signal source is connected, and source electrode is connected with the 5th node；
The grid of 13rd thin film transistor (TFT), the 13rd thin film transistor (TFT) is connect with the first node, drain electrode with it is described
The connection of 5th node, source electrode are connected with the low level DC signal source；
The grid of 14th thin film transistor (TFT), the 14th thin film transistor (TFT) is connect with the first node, drain electrode with it is described
Fourth node is connected, and source electrode is connected with the low level DC signal source；
15th thin film transistor (TFT), the grid of the 15th thin film transistor (TFT) and drain electrode are believed with the second high level direct current
Number source is connected, and source electrode is connected with the fourth node；
The grid of 16th thin film transistor (TFT), the 16th thin film transistor (TFT) is connect with the 5th node, drain electrode with it is described
First node is connected, and source electrode is connected with the low level DC signal source；
The grid of 17th thin film transistor (TFT), the 17th thin film transistor (TFT) is connected with the 5th node, drain electrode with it is described
Signal output end is connected, and source electrode is connected with the low level DC signal source；
Wherein, the test node of GOA unit include the signal input part, it is the signal output end, the first node, described
One or more of second node, the third node, the fourth node and described 5th node.
4. GOA as claimed in claim 3 tests circuit, which is characterized in that the item number of the test bus is two, each survey
Trying unit includes:
Four second level p-wires, every two second level p-wires form one group, and two groups of second level p-wires are separately positioned on corresponding GOA
The two sides up and down of unit, and one in two second level p-wires being disposed over is electrically connected with two one tested in bus
It connects, another in two be disposed over second level p-wire is electrically connected with two another tested in bus, and setting exists
One in two second level p-wires of lower section is electrically connected with two one tested in bus, two be arranged below second level
Another in p-wire is electrically connected with two another tested in bus；
Five three-level p-wires, the corresponding signal input part, the signal output end, the first node, second section
A three-level p-wire is respectively set in point and the third node；
Wherein, it is carried out to any one test node in the signal input part, the signal output end, the first node
When test, the corresponding three-level p-wire of the test node is established and two second level p-wires being arranged in below the GOA unit
Between electrical connection, when testing any one test node in the second node and the third node, establish
Being electrically connected between the corresponding three-level p-wire of the test node and two second level p-wires being arranged in above the GOA unit
It connects.
5. GOA as claimed in claim 4 tests circuit, which is characterized in that corresponding two tests of two adjacent GOA units
One group of second level p-wire of units shared.
6. GOA as claimed in claim 2 tests circuit, which is characterized in that the circuit of the GOA circuit and the test circuit
Plate line is realized by two metal layers, wherein second level p-wire and test bus use same layer metal, pass through company between the two
It connects cabling and realizes that electrical connection, the connection cabling and the second level p-wire and the test bus use different layers metal, institute
It states connection cabling to connect with the second level p-wire and the test bus by via hole respectively, three-level p-wire and second level are tested
Line uses different layers metal, and three-level p-wire and test node use different layers metal, the three-level p-wire and corresponding survey
It tries to be electrically connected between node by via hole.
7. a kind of array substrate characterized by comprising
Cascade multiple GOA units；And
As GOA of any of claims 1-6 tests circuit.
8. a kind of display panel characterized by comprising
Color membrane substrates；And
Array substrate as claimed in claim 7, the array substrate are oppositely arranged with the color membrane substrates.
9. a kind of GOA test method is tested for the GOA circuit in the array substrate to display panel, the GOA circuit
Including cascade multiple GOA units, at least one in the multiple GOA unit is with test node, which is characterized in that described
GOA test method includes:
At least one test bus of setting in the multiple GOA unit region, and establish the test bus and be arranged and exist
Electrical connection between the testing weld pad of the display panel；
In the multiple GOA unit region, setting and at least one GOA unit with test node be correspondingly extremely
A few test cell, and in test cell corresponding with having the GOA unit of at least one test node, setting at least one
At least one three-level p-wire is arranged in second level p-wire and at least one corresponding described test node, wherein two pole is surveyed
Examination line is electrically connected with the test bus, and the three-level p-wire is electrically connected with corresponding test node；
When the signal to test node is tested, being electrically connected between the three-level p-wire and two pole p-wire is established
It connects.
10. GOA test method as claimed in claim 9, which is characterized in that synchronization is only to one in the GOA circuit
The signal of a test node is tested, wherein after completing the signal testing of a test node, to another test node
Signal when being tested, cut off being electrically connected between the corresponding three-level p-wire of one test node and two pole p-wires
Afterwards, being electrically connected between the corresponding three-level p-wire of another test node and two pole p-wires is resettled.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910462262.2A CN110189666A (en) | 2019-05-30 | 2019-05-30 | GOA tests circuit, array substrate, display panel and GOA test method |
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| CN201910462262.2A CN110189666A (en) | 2019-05-30 | 2019-05-30 | GOA tests circuit, array substrate, display panel and GOA test method |
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Application publication date: 20190830 |