CN110176866B - 2N inverter parallel system and control method thereof - Google Patents

2N inverter parallel system and control method thereof Download PDF

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CN110176866B
CN110176866B CN201910286900.XA CN201910286900A CN110176866B CN 110176866 B CN110176866 B CN 110176866B CN 201910286900 A CN201910286900 A CN 201910286900A CN 110176866 B CN110176866 B CN 110176866B
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inverter
pulse
parallel
inductor
coupling inductor
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CN110176866A (en
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蒋栋
李桥
张野驰
沈泽微
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel

Abstract

The invention discloses a parallel system of 2N inverters and a control method, wherein one synonym end of a coupling inductor a is connected with a phases of a first inverter and a second inverter, and the other synonym end of the coupling inductor a is connected with the input end of an independent inductor a after being connected in parallel; in the same way, the connection relationship between the coupling inductor b and the coupling inductor c; the output ends of the same independent inductors are connected in parallel; the independent inductors are used for restraining the circulation current among the inverter units; the coupling inductors are used for restraining circulating currents in the inverter units. Based on the inverter parallel system, the control method comprises the following steps: calculating the rising edge and the falling edge of the switching pulse according to the synchronous sawtooth carrier and the pulse phase shifting angle, and acquiring a PWM signal; and the control of the parallel structure of the 2N inverters is realized through PWM signals. The invention combines the advantages of the coupling inductor and the independent inductor to restrain the circulation current of 2N inverters, and realizes the expansion and control of the inverter parallel system based on the coupling inductor.

Description

2N inverter parallel system and control method thereof
Technical Field
The invention belongs to the field of power electronics, and particularly relates to a 2N inverter parallel system and a control method thereof.
Background
Voltage source inverters are widely used in many power conversion applications and are typically operated in parallel to achieve higher output currents, effectively increasing the system power rating. The parallel inverter has high modularization degree, is suitable for adopting a fault-tolerant technology, and ensures the reliability of the system. The staggered pulse width modulation has the capability of reducing the current harmonic wave of the line and the loss of the passive device, and is more and more emphasized by people. In addition, zero common mode modulation based on two inverter parallel systems can theoretically realize zero common mode voltage, and can obviously restrain system common mode current and common mode EMI. When interleaved pulse width modulation or zero common mode modulation is used, the problem of circulating current is caused by artificially introduced instantaneous voltage difference. The problem that the circulating current causes large power loss, overstresses a power device and saturates an inductor needs to be solved.
Currently, there are three main hardware approaches to suppress circulating currents: (1) an isolation transformer; (2) a coupling inductor; (3) an independent inductance. The simplest method is to connect an isolation transformer to the direct current side or the alternating current side of the system to block the circulating current path, but the isolation transformer has the main disadvantage of needing a large and expensive industrial frequency transformer, so that the isolation transformer is not preferred. The coupling inductor can realize high coupling of parallel bridge arms, the main magnetic circuit of the coupling inductor is mainly used for inhibiting the circulating current between the bridge arms, and the leakage inductor of the coupling inductor is used as line inductance and has higher power density. Since the coupling inductors cannot be designed to any number, they are more suitable for a fixed or small number of parallel systems. At present, the circulation current is limited by adopting independent inductors aiming at N inverter parallel systems, but the weight and the volume of the system are obviously larger than those of a coupling inductor; the coupling inductor is mainly used for inhibiting two inverter parallel systems and cannot be directly expanded to a plurality of inverter systems; the zero common mode modulation algorithm is suitable for two parallel inverter systems and cannot be directly expanded to a plurality of inverter systems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a 2N inverter parallel system and a control method thereof, and aims to solve the problem that coupling inductance and zero common mode modulation cannot be expanded to a plurality of inverter parallel systems.
To achieve the above object, the present invention provides a 2N inverter parallel system, comprising: n inverter units and 3N independent inductors; the inverter unit comprises a first inverter, a second inverter, a coupling inductor a, a coupling inductor b and a coupling inductor c;
one different name end of the coupling inductor a is connected with the phase a of the first inverter and the phase a of the second inverter, and the other different name end of the coupling inductor a is connected with the input end of an independent inductor a after being connected in parallel;
one different name end of the coupling inductor b is connected with the phase b of the first inverter and the phase b of the second inverter, and the other different name end of the coupling inductor b is connected with the input end of an independent inductor b after being connected in parallel;
one different name end of the coupling inductor c is connected with the phase c of the first inverter and the phase c of the second inverter, and the other different name end of the coupling inductor c is connected with the input end of an independent inductor c after being connected in parallel;
the output ends of the independent inductors a are connected in parallel; the output ends of the independent inductors b are connected in parallel; the output ends of the independent inductors b are connected in parallel;
the independent inductors are used for restraining the circulation current among the inverter units; the coupling inductors are used for restraining circulating currents in the inverter units.
Based on the 2N inverter parallel system provided by the invention, the invention provides a corresponding control method, which comprises the following steps:
s1, calculating the rising edge and the falling edge of the switching pulse according to the pulse phase shift angle and the sawtooth carrier wave of clock synchronization;
s2, obtaining a PWM signal by comparing the sizes of the synchronous sawtooth carrier wave and the rising edge and the falling edge of the switching pulse;
and S3, controlling the turn-off and turn-on of each switching tube in the inverter through the PWM signal, and further realizing the modulation of the parallel structure of the 2N inverters.
Preferably, in step S1, the pulse phase shift angle includes: pulse phase shift angles in the inverter units and pulse phase shift angles between the inverter units;
the method for generating the pulse phase shift angle in the inverter unit is staggered pulse width modulation or zero common mode pulse width modulation based on clock synchronization sawtooth carriers;
the selection of the pulse phase shift angle between the inverter units can optimize the current output harmonic wave; when the zero common mode modulation is adopted in the unit and the modulation ratio is larger than 0.6, the circulating current peak value of the unit passing through the coupling inductor can be reduced to the greatest extent when the phase shift angle between the units is set to be 90 degrees, so that the maximum saturation flux density of the coupling inductor of the unit is reduced, and the design volume and the weight of the coupling inductor of the unit are reduced.
Preferably, in step S1, the method for calculating the rising edge and the falling edge of the switching pulse includes:
s1.1, calculating the initial rising edge and the falling edge of the pulse switch according to the peak value of the sawtooth carrier, the set pulse switch duty ratio and the pulse phase shift angle:
s1.2, comparing the initial rising edge and the falling edge of the pulse switch with the peak value of the sawtooth carrier respectively, and if the initial rising edge and the falling edge are less than or equal to the peak value of the sawtooth carrier, keeping the initial rising edge and the initial falling edge; otherwise, updating the rising edge and the falling edge;
the updated rising edge is the difference between the initial rising edge and the peak value of the sawtooth carrier, and the updated falling edge is the difference between the initial falling edge and the peak value of the sawtooth carrier;
the concrete expression is as follows:
(1) calculating rising and falling edges:
Figure BDA0002023587860000031
(2) comparison of Rx,j,iAnd size of PRD, Fx,j,iWith the size of PRD, update Fx,j,i、Rx,j,i；
The specific updating method comprises the following steps:
if R isx,j,iPRD is less than or equal to, then:
Figure BDA0002023587860000032
if not, then,
Figure BDA0002023587860000033
if Fx,j,iPRD is less than or equal to, then:
Figure BDA0002023587860000034
otherwise
Figure BDA0002023587860000035
Wherein, Fx,j,iRepresents the falling edge of the ith inverter PWM pulse of the x-phase j unitx,j,iRepresents the rising edge of the PWM pulse of the ith inverter of the x-phase j unit, d represents the duty ratio of PWM, shift _ in and shift _ out represents the phase shift angle within each unit and between units of the PWM pulse, shift represents the total phase shift angle of the PWM pulse (shift _ in + shift _ out), and ranges from 0 to 1, representing 0 to 360 degrees, and PRD represents the peak value of the sawtooth wave.
In step S2, the method for acquiring the PWM signal includes:
when the falling edge of the switching pulse is larger than the rising edge, if the sawtooth carrier is between the two, the PWM pulse outputs high level; otherwise, PWM pulse outputs low level;
when the rising edge of the switching pulse is larger than the falling edge, if the sawtooth carrier is between the two, the PWM pulse outputs low level; otherwise, the PWM pulse outputs a high level.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
(1) on one hand, the invention provides a 2N inverter parallel system, coupling inductors are adopted in inverter units, and the units are connected in parallel through independent inductors, so that the advantage of high power density of the coupling inductors is combined, the internal part of the inverter units is subjected to ring current inhibition, and the defect that the coupling inductors cannot be connected in parallel with a plurality of inverters is overcome by adopting the independent inductors, and the expansion with the 2 inverters and 3 coupling inductors as units is realized; on the other hand, the invention provides a control method for the parallel system of 2N inverters, which is used for popularizing a zero common mode modulation algorithm suitable for two parallel inverters to the parallel system of 2N inverters and solving the problem that the coupling inductor is only suitable for the circulating current suppression of the inverter parallel system with fixed or small number.
(2) In the invention, when the inverter unit adopts zero common mode modulation and the modulation ratio is more than 0.6, the inter-unit phase shift angle is set to 90 degrees, so that the circulating current peak value of the unit passing through the coupling inductor can be reduced to the greatest extent, the maximum saturation flux density of the unit coupling inductor is reduced, and the design volume and the weight of the unit coupling inductor are reduced.
(3) The invention provides a corresponding modulation method aiming at a parallel system of 2N inverters, and each inverter can effectively synchronize the output of PWM pulse signals of each inverter through the same sawtooth carrier and the pulse phase shift angle obtained by the same method, thereby realizing the accurate control of the pulse position.
Drawings
Fig. 1 is a schematic structural diagram of a four-inverter parallel system provided by the invention;
fig. 2 is a schematic diagram of a conventional parallel connection of four inverters;
FIG. 3 is a schematic diagram of a coupled inductor;
FIG. 4(a) is a schematic diagram of PWM pulse control implementation when F > R provided by the present invention;
FIG. 4(b) is a schematic diagram of the PWM pulse control implementation provided by the present invention when F < R;
fig. 5 is a schematic diagram of the intra-cell and inter-cell circulating currents and the common mode voltage when shift _ out is 0 according to the present invention;
fig. 6 is a schematic diagram of the intra-cell and inter-cell circulating currents and the common mode voltage when shift _ out is 0.25 according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention provides a parallel system of 2N inverters, comprising: n inverter units and 3N independent inductors; the inverter unit comprises a first inverter, a second inverter, a coupling inductor a, a coupling inductor b and a coupling inductor c;
one different name end of the coupling inductor a is connected with the phase a of the first inverter and the phase a of the second inverter, and the other different name end of the coupling inductor a is connected with the input end of an independent inductor a after being connected in parallel;
one different name end of the coupling inductor b is connected with the phase b of the first inverter and the phase b of the second inverter, and the other different name end of the coupling inductor b is connected with the input end of an independent inductor b after being connected in parallel;
one different name end of the coupling inductor c is connected with the phase c of the first inverter and the phase c of the second inverter, and the other different name end of the coupling inductor c is connected with the input end of an independent inductor c after being connected in parallel;
the output ends of the independent inductors a are connected in parallel; the output ends of the independent inductors b are connected in parallel; the output ends of the independent inductors b are connected in parallel;
the independent inductors are used for restraining the circulation current among the inverter units; the coupling inductors are used for restraining circulating currents in the inverter units.
As shown in fig. 1, the embodiment provides a schematic structural diagram of a parallel system of four inverters, which includes a first unit and a second unit, as shown in fig. 1, two inverters in a unit suppress a circulating current in the unit through a coupling inductor; and the circulation current between the units is restrained by independent inductance. As shown in fig. 2, the conventional parallel structure of four inverters adopts a single independent inductor to suppress circulating current, and adopts the conventional parallel structure, which requires 12 independent inductors in total; if the parallel structure provided by the invention is adopted, 6 coupling inductors and 6 independent inductors are needed in total. The design of the coupling inductor does not need to consider the output phase current and is only determined by the high-frequency circulating current peak value, so that the coupling inductor has obvious weight and volume advantages. Therefore, the power density of the system can be obviously improved by adopting the parallel topology provided by the invention.
FIG. 3 shows a typical coupling inductance diagram, which has two windings W and W in common*The two coils have the same number of turns and are reversely wound on the magnetic core. i.e. ia1And ia2For parallel bridge arm current, phia1And phia2Is its corresponding magnetic flux. In theory ia1And ia2The fundamental components are the same, the main magnetic path of the magnetic core is mainly determined by the intra-cell circulating current, and the leakage inductance mainly acts on the output phase current and the inter-cell circulating current.
As can be seen from FIG. 3, the coupled inductor has four ports, forming two pairs of synonym terminals, i.e., ia1And ia2The input end is a pair of synonyms, and the other two ports are the other pair of synonyms;
indicating that in order to ensure the consistency of the sampling signal and the PWM signal, the master controller and the slave controller are adopted for controlling, the slave controller sends the sampling signal to the master controller, and meanwhile, the slave controller receives a duty ratio signal; the PWM signal is generated by the slave controller and is transmitted to the IGBT driving board; in order to ensure the consistency of the carrier waves, the master controller synchronizes the carrier waves of the slave inverters through a synchronization signal line; in order to ensure the consistency of the modulation signals, the main controller simultaneously outputs the duty ratio.
Based on the 2N inverter parallel structure provided by the invention, the invention provides a corresponding control method, which comprises the following steps:
s1, calculating the rising edge and the falling edge of the switching pulse according to the pulse phase shift angle and the sawtooth carrier wave of clock synchronization;
s2, obtaining a PWM signal by comparing the sizes of the synchronous sawtooth carrier wave and the rising edge and the falling edge of the switching pulse;
and S3, controlling the turn-off and turn-on of each switching tube in the inverter through the PWM signal, and further realizing the modulation of the parallel structure of the 2N inverters.
Preferably, in step S1, the pulse phase shift angle includes: pulse phase shift angles in the inverter units and pulse phase shift angles between the inverter units;
the generation of the pulse phase shift angle within the inverter unit is based on either interleaved pulse width modulation or zero common mode pulse width modulation of a synchronous sawtooth carrier;
preferably, in step S1, the method for calculating the rising edge and the falling edge of the switching pulse includes:
s1.1, calculating the initial rising edge and the falling edge of the pulse switch according to the peak value of the sawtooth carrier, the set pulse switch duty ratio and the pulse phase shift angle:
s1.2, comparing the initial rising edge and the falling edge of the pulse switch with the peak value of the sawtooth carrier respectively, and if the initial rising edge and the falling edge are less than or equal to the peak value of the sawtooth carrier, keeping the initial rising edge and the initial falling edge; otherwise, updating the rising edge and the falling edge;
the updated rising edge is the difference between the initial rising edge and the peak value of the sawtooth carrier, and the updated falling edge is the difference between the initial falling edge and the peak value of the sawtooth carrier;
fig. 4(a) and 4(b) show PWM pulse control schemes of the present invention, with 4 inverters pulsing using synchronous sawtooth carrier comparison. In order to realize the control of the pulse position, the rising edge (R) and the falling edge (F) of each switching pulse are respectively controlled by two comparison registers, and the PWM pulse is obtained by comparing a carrier wave with a corresponding reference wave. The method specifically comprises the following steps:
(1) calculating rising and falling edges:
Figure BDA0002023587860000071
(2) comparison of Rx,j,iAnd size of PRD, Fx,j,iWith the size of PRD, update Fx,j,i、Rx,j,i；
The specific updating method comprises the following steps:
if R isx,j,iPRD is less than or equal to, then:
Figure BDA0002023587860000072
if not, then,
Figure BDA0002023587860000073
if Fx,j,iPRD is less than or equal to, then:
Figure BDA0002023587860000081
otherwise
Figure BDA0002023587860000082
Wherein, Fx,j,iRepresents the falling edge of the ith inverter PWM pulse of the x-phase j unitx,j,iThe rising edge of the ith inverter PWM pulse of an x-phase j unit is represented, d represents the PWM duty ratio, shift _ in and shift _ out respectively represent the phase shifting angles inside and outside the PWM pulse unit, shift represents the total phase shifting angle of the PWM pulse (shift _ in + shift _ out), the range of the total phase shifting angle is from 0 to 1, the range of the total phase shifting angle is from 0 to 360 degrees, and PRD represents the peak value of a sawtooth wave.
In step S2, the method for acquiring the PWM signal includes:
as shown in fig. 4(a), when the falling edge of the switching pulse is greater than the rising edge (F > R), if the saw-tooth carrier is between the two, the PWM pulse outputs a high level; otherwise, PWM pulse outputs low level;
as shown in fig. 4(b), when the rising edge of the switching pulse is greater than the falling edge (R > F), if the saw-tooth carrier is between the two, the PWM pulse outputs a low level; otherwise, the PWM pulse outputs a high level.
The invention takes a zero common mode modulation algorithm as an example to obtain the PWM pulse position, and realizes the ring current suppression between each inverter unit and the unit by controlling 2N inverter parallel systems, which is concretely as follows:
inverters in the first unit and the second unit adopt a zero common mode modulation algorithm, and PWM pulse positions between the units can be subjected to phase shifting;
fig. 5 is a schematic diagram of the circulating currents and the common mode voltage in the first inverter unit and the second inverter unit and between the first inverter unit and the second inverter unit when the pulse phase shift angle between the first unit and the second unit is 0 degree, that is, shift _ out is 0, because the pulse phase shift angle between the first inverter unit and the second inverter unit is 0 degree, that is, the pulse synchronization between the first inverter unit and the second inverter unit, the circulating current between the first inverter unit and the second inverter unit is 0, the high-frequency circulating currents in the first inverter unit and the second inverter unit are consistent, at this time, the common mode voltage is always 0, and the output phase current THD is 1.78%.
Fig. 6 is a schematic diagram of the circulating currents and the common mode voltage in the first inverter and the second inverter and between the first inverter and the second inverter when the pulse phase shift angle between the first inverter and the second inverter is 90 degrees, that is, shift _ out is 0.25, because the pulse phase shift angle between the first inverter and the second inverter is 90 degrees, that is, the pulses of the first inverter and the second inverter are not synchronous, a high-frequency circulating current exists between the first inverter and the second inverter, the high-frequency circulating currents in the first inverter and the second inverter are not consistent, the peak value of the circulating current in the second inverter is small, at this time, the common mode voltage is always 0, the output phase current THD is 0.67%, and the output current quality is improved.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (6)

1. A 2N inverter parallel system, comprising: n inverter units and 3N independent inductors; the inverter unit comprises a first inverter, a second inverter, a coupling inductor a, a coupling inductor b and a coupling inductor c;
one different name end of the coupling inductor a is connected with the phase a of the first inverter and the phase a of the second inverter, and the other different name end of the coupling inductor a is connected with the input end of an independent inductor a after being connected in parallel;
one different name end of the coupling inductor b is connected with the phase b of the first inverter and the phase b of the second inverter, and the other different name end of the coupling inductor b is connected with the input end of an independent inductor b after being connected in parallel;
one different name end of the coupling inductor c is connected with the phase c of the first inverter and the phase c of the second inverter, and the other different name end of the coupling inductor c is connected with the input end of an independent inductor c after being connected in parallel;
the output ends of the independent inductors a are connected in parallel; the output ends of the independent inductors b are connected in parallel; the output ends of the independent inductors c are connected in parallel;
the independent inductors are used for restraining the circulation current among the inverter units and are used for the parallel connection of the inverter units; the coupling inductors are used for restraining circulating currents in the inverter units.
2. The 2N inverter parallel system of claim 1, wherein the pulse phase shift angle within the inverter unit is generated based on interleaved pulse width modulation or zero common mode pulse width modulation of a clock-synchronized sawtooth carrier.
3. The parallel system of 2N inverters according to claim 1 or 2, wherein there is a pulse phase shift angle between the inverter units.
4. The method for controlling a parallel system of 2N inverters according to claim 1, comprising:
s1, calculating the rising edge and the falling edge of the switching pulse according to the pulse phase shift angle and the sawtooth carrier wave of clock synchronization;
s2, obtaining a PWM signal by comparing the synchronous sawtooth carrier with the rising edge and the falling edge of the switching pulse;
s3, controlling the turn-off and turn-on of each switching tube in the inverter through the PWM signal, and further realizing the control of the parallel structure of the 2N inverters;
the pulse phase shift angle comprises: pulse phase shift angles in the inverter units and pulse phase shift angles between the inverter units;
when zero common mode modulation is adopted in the inverter units and the modulation ratio is larger than 0.6, the phase shift angle between the units is set to be 90 degrees.
5. The control method according to claim 4, wherein the step S1 includes:
s1.1: calculating the initial rising edge and the falling edge of the pulse switch according to the peak value of the sawtooth carrier, the set pulse switch duty ratio and the pulse phase shift angle:
s1.2: comparing the initial rising edge of the pulse switch with the peak value of the sawtooth carrier, and if the initial rising edge is less than or equal to the peak value of the sawtooth carrier, keeping the initial rising edge; otherwise, updating the rising edge as the difference between the initial rising edge and the peak value of the sawtooth carrier;
comparing the initial falling edge of the pulse switch with the peak value of the sawtooth carrier, and if the initial falling edge is less than or equal to the peak value of the sawtooth carrier, keeping the initial falling edge; otherwise, the falling edge is updated to be the difference between the initial falling edge and the peak value of the sawtooth carrier.
6. The control method according to claim 5, wherein the PWM signal is obtained by:
when the falling edge of the switching pulse is larger than the rising edge, if the sawtooth carrier is between the two, the PWM pulse outputs high level; otherwise, PWM pulse outputs low level;
when the rising edge of the switching pulse is larger than the falling edge, if the sawtooth carrier is between the two, the PWM pulse outputs low level; otherwise, the PWM pulse outputs a high level.
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