CN110175017B - Multiplier based on RRAM and operation method thereof - Google Patents
Multiplier based on RRAM and operation method thereof Download PDFInfo
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- CN110175017B CN110175017B CN201910436604.3A CN201910436604A CN110175017B CN 110175017 B CN110175017 B CN 110175017B CN 201910436604 A CN201910436604 A CN 201910436604A CN 110175017 B CN110175017 B CN 110175017B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
Abstract
The invention discloses a multiplier based on RRAM and an operation method thereof. The RRAM-based multiplier includes: the array of RRAMs, amplifier, RS flip-flop array and adder module. 1) Setting all BL lines to be-1V, setting all WL lines to be 1V, lasting for 1ns, respectively adding multiplicands and multipliers to BL [7:0] lines and WL [7:0] lines, wherein the product of a certain multiplicand and a certain multiplicand is an intermediate result and is written into an RRAM array; respectively placing reading voltage on each row of RRAM in the RRAM array, and storing the read intermediate result stored in the RRAM into the RS trigger array after the intermediate result is amplified by an amplifier; the output of the RS trigger array is used as the input of an adder, and after N read cycles, the adder calculates the final result of multiplication; where N is the number of columns in the RRAM array. The multiplier provided by the invention is based on the resistive nonvolatile novel memory RRAM, has the characteristics of better power consumption and time performance, and expands the application range of the novel memory RRAM in a basic circuit.
Description
Technical Field
The invention belongs to the field of analog integrated circuit design, and relates to a multiplier based on RRAM and an operation method thereof.
Background
In recent years, various new memory devices have been developed to the public, with the potential for future access to the mainstream memory market. If new types of memory devices, such as RRAM, enter the market, many basic circuits based on these new types of memory devices are required for near memory computation. Therefore, the present invention proposes a RRAM-based multiplier. The first part of calculation of the multiplier based on the RRAM is completed in the RRAM array, the near memory calculation of the second part is completed in the adder based on the CMOS, the power consumption performance is better, the energy consumption of one calculation is about 2.116nJ, the speed is higher, and the worst calculation needs 1.6 us.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a multiplier based on RRAM and an operation method thereof. In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention first discloses a multiplier based on RRAM, comprising: an RRAM array; the amplifier is connected with the output end of the RRAM array; the RS trigger array is connected with the output end of the amplifier; and the adder module is connected with the output end of the RS trigger array.
Preferably, the RRAM array is a crossbar structure, and comprises 8 × 8 RRAMs, and each RRAM is positioned at the intersection of any two lines in BL [7:0] and WL [7:0 ]; BL [7:0] is the port for inputting the multiplier, each BL line is connected to the positive pole of a column of RRAMs, and WL [7:0] is the port for inputting the multiplicand, each BL line is connected to the negative pole of a column of RRAMs; the leftmost string of each WL line has a resistor for reading out the information stored in the RRAM in the reading step.
Preferably, the RS flip-flop array comprises 8 × 8 RS flip-flops for storing intermediate results read from the RRAM array; each 8RRAM shares one WL line for reading, so 8 read cycles are needed to complete the read operation of an 8x 8RRAM array; since information in the RRAM array can only be read out one column at a time, RS flip-flops are required to store the data of the RRAM, facilitating the input of intermediate results to the adder.
The invention also discloses an operation method of the multiplier based on the RRAM, which comprises the following steps:
1) all BL lines are set to-1V, all WL lines are set to 1V, the duration is 1ns,
2) adding multiplicand and multiplier to BL [7:0] and WL [7:0] lines respectively, the product of a certain bit of multiplier and a certain bit of multiplicand is an intermediate result, and writing the intermediate result into RRAM array;
3) respectively placing reading voltage on each row of RRAM in the RRAM array, and storing the read intermediate result stored in the RRAM into the RS trigger array after the intermediate result is amplified by an amplifier;
4) the output of the RS trigger array is used as the input of an adder, and after N read cycles, the adder calculates the final result of multiplication; where N is the number of columns in the RRAM array, and N is 8 in this 8 × 8 multiplier.
Preferably, the step 2) is specifically: in an 8x8 array of RRAMs, BL [7:0] is the port for inputting the multiplier, each BL line is connected to the anode of a column of RRAMs, and WL [7:0] is the port for inputting the multiplicand, each BL line is connected to the cathode of a column of RRAMs; the multiplicand is a [7:0], the multiplier is b [7:0 ]; when a [ i ] is 0 or b [ j ] is 0, a voltage of 0V is added to the corresponding WL [ i ] or BL [ j ]; when a [ i ] is equal to 1, WL [ i ] is added with a voltage of-1V; when b [ j ] is equal to 1, adding 1V voltage to BL [ j ]; the state of RRAM is determined by the voltage difference between the positive pole and the negative pole, namely the voltage difference between BL [ j ] and WL [ i ]; when a [ i ] is 1 and b [ j ] is 0 or a [ i ] is 0 and b [ j ] is 1, the voltage difference across the RRAM is 1V, and the RRAM state is not changed; similarly, when a [ i ] is 0 and b [ j ] is 0, the voltage difference across the RRAM is 0V; only when a [ i ] is 1 and b [ j ] is 1, the voltage difference across the RRAM is 2V, reaching the set threshold voltage; that is, by inputting the multiplicand a [7:0] and multiplier b [7:0], an 8x 8RRAM array can be made to directly compute and store all the intermediate results of a [7:0] xb [7:0], i.e., the product of all a [ i ] xb [ j ].
Preferably, the a [7:0], b [7:0] signals representing the multiplicand and multiplier are all 1ns in duration to ensure that the intermediate results are successfully written into the RRAM.
Compared with the prior art, the invention has the beneficial effects that: the application range of the novel memory device RRAM is widened, so that the RRAM can be used for a multiplier circuit. The multiplier based on RRAM consumes about 2.116nJ energy by one calculation, and the worst case one multiplication calculation needs 1.6 us. Although the multiplier based on the RRAM has higher energy consumption and time in one calculation compared with the traditional multiplier based on the CMOS, considering that the RRAM will occupy a certain share in the memory market in the future, the multiplier based on the CMOS needs to read the data in the RRAM to the CMOS for multiplication, which requires a large time cost and power consumption cost; the RRAM-based multiplier can directly perform part of the calculation of multiplication in the RRAM array, that is, the RRAM-based multiplier is more advantageous in time and power consumption on the basis that the memory is the RRAM.
Drawings
FIG. 1 is a circuit diagram of a RRAM-based multiplier;
FIG. 2 is a circuit diagram of an RS flip-flop;
fig. 3 is an amplifier circuit diagram.
Detailed Description
The present invention will be described in further detail with reference to specific embodiments.
The invention proposes a RAAM-based multiplier, and the following describes in detail the RRAM-based multiplier proposed by the invention.
The circuit diagram of the multiplier based on the RRAM is shown in fig. 1, and the circuit can be divided into the following parts: RRAM array, RS flip-flop array, adder module. The multiplication process is that the multiplicand is input into the RRAM array, the result after the calculation in the memory RRAM is amplified by the amplifier and then stored in the RS trigger array, the output end of the RS trigger array is connected with the adder module, and finally the adder module calculates the final result of the multiplication.
The read operation of RRAM has two kinds of SET (SET) and RESET (RESET). Wherein SET can change the RRAM from a high resistance state (0) to a low resistance state (1), and RESET can change the RRAM from the low resistance state (1) to the high resistance state (0). The RRAM and SET operation adopted by the invention require that the voltage difference of the positive and negative ports of the RRAM is more than 2V, the voltage difference of the positive and negative ports of the RESET operation is less than-2V, and the read operation voltage is preferably 1V.
The operation method of the multiplier based on RRAM of the invention has the following specific flows:
first, before inputting the multiplicand and multiplier into the multiplier, all BL lines need to be set to-1V and all WL lines need to be set to 1V for 1ns, in order to let all RRAMs be reset to a high-impedance state so as not to affect the subsequent writing.
After all the RRAM are set, the multiplicand, multiplier, needs to be input into the RRAM array. In an 8x 8RRAM array, BL [7:0] is the port for inputting the multiplier, each BL line is connected to the anode of a column of RRAMs, and WL [7:0] is the port for inputting the multiplicand, each BL line is connected to the cathode of a column of RRAMs. Assume that the multiplicand is a [7:0] and the multiplier is b [7:0 ]. When a [ i ] is equal to 0 or b [ j ] is equal to 0, a voltage of 0V is added to the corresponding WL [ i ] or BL [ j ]. When a [ i ] is equal to 1, WL [ i ] is added with a voltage of-1V; when b [ j ] is 1, a voltage of 1V is applied to BL [ j ]. For an array with BL [ j ] and WL [ i ] connected to the RRAM, the state of the RRAM is determined by the voltage difference between the positive and negative poles, i.e., BL [ j ] and WL [ i ]. When a [ i ] ═ 1b [ j ] ═ 0 or a [ i ] ═ 0b [ j ] ═ 1, the voltage difference between two ends of the RRAM is 1V, and the state of the RRAM is not changed; similarly, when a [ i ] is 0b [ j ] is 0, the voltage difference across the RRAM is 0V. Only when a [ i ] is 1 and b [ j ] is 1, the voltage difference across the RRAM is 2V, reaching the set threshold voltage. That is, by correctly inputting the multiplicand a [7:0] and multiplier b [7:0], it is possible for the 8x 8RRAM to directly compute and store all the intermediate results of a [7:0] xb [7:0], i.e., the product of all a [ i ] xb [ j ]. Note that the a [7:0], b [7:0] signals representing the multiplicand and multiplier each need to last 1ns to ensure that the intermediate results are successfully written into the RRAM.
When all intermediate results have been calculated, the data of the RRAM array needs to be read out into the flip-flop array. The 8x8 flip-flop array functions to store intermediate results so that all intermediate results are input to the CMOS adder to obtain the final multiplication result. The flip-flop is an RS flip-flop with an enable terminal, and as shown in fig. 2, the CP is the enable terminal. When CP is 0, the RS flip-flop is locked and in a holding state, and the output is not changed along with the change of the input; when CP is 1, RS flip-flop is in writing state. Since only 1 WL per row of the RRAM array can be used to read the results, only 8 RRAM's can be read per 1 column per read to avoid clutter. The current on the WL is reflected by the RRAM data when a 1V read voltage is applied to the corresponding BL line in the column, and a 1k Ω resistor is connected to the left-most side of each WL line, so that the voltage on the right side of the WL, which is proportional to the current on the WL, can represent the data stored inside the RRAM. At the time of reading, all WLs are set to 0V. In these 8 read cycles, the 8 ports from BL [7] to BL [0] are set to 1V, respectively, and only one BL port is set to 1V at a time, and the other BL ports are set to 0V. In the first reading period, all the RS triggers are set to be in working states, RRAM state information read out from the right ends of the resistors of all the WL lines is stored to the right end output ends of the RS triggers in the rightmost column through amplification of the amplifiers. The differential amplifier schematic is shown in FIG. 3, where Vin + is connected to the right end of the WL line of the preceding RRAM array, Vin-is connected to the low voltage Vss, and the amplifier output is the Vo terminal. That is, all RS flip-flops, including the rightmost column of RS flip-flops, store information for all RRAMs connected by BL [7 ]. In order to keep the output of the rightmost column of RS flip-flops holding the information of all RRAMs connected with BL [7], the column of flip-flops is not operated and is set to a holding state. In the second cycle, all flip-flops are active except for the rightmost column of flip-flops, and then all RRAM state information for the BL [6] connection is stored to the RS flip-flop in the second column from the right. Similarly, 8x8 flip-flops store all the information in an 8x 8RRAM after 8 cycles. The read speed of RRAM is again on the order of nanoseconds (ns), but because storage of the flip-flop requires time, each read cycle lasts 200 ns. By controlling the trigger switch, after 8 read cycles, all intermediate results are stored in the trigger. At the same time, the CMOS adder calculates the final multiplication result.
Claims (2)
1. A method of operating a RRAM-based multiplier, said multiplier comprising:
an RRAM array; the RRAM array is a crossbar structure and comprises 8 multiplied by 8 RRAMs, and each RRAM is positioned at the intersection point of any two lines in BL [7:0] and WL [7:0 ]; BL [7:0] is the port for inputting the multiplier, each BL line is connected to the positive pole of a column of RRAMs, and WL [7:0] is the port for inputting the multiplicand, each BL line is connected to the negative pole of a column of RRAMs; the leftmost string of each WL line has a resistor for reading out the information stored in the RRAM in the reading step;
the amplifier is connected with the output end of the RRAM array;
the RS trigger array is connected with the output end of the amplifier; the RS trigger array comprises 8 multiplied by 8 RS triggers and is used for storing intermediate results read out from the RRAM array; each 8RRAM shares one WL line for reading, so 8 read cycles are needed to complete the read operation of an 8x 8RRAM array; because the information in the RRAM array can be read out one column at a time, an RS trigger is required to store the data of the RRAM, and an intermediate result is conveniently input to the adder;
the adder module is connected with the output end of the RS trigger array;
the method is characterized by comprising the following steps:
1) all BL lines are set to-1V, all WL lines are set to 1V, the duration is 1ns,
2) adding multiplicand and multiplier to BL [7:0] and WL [7:0] lines respectively, the product of a certain bit of multiplier and a certain bit of multiplicand is an intermediate result, and writing the intermediate result into RRAM array; the method specifically comprises the following steps:
in an 8x 8RRAM, BL [7:0] is the port for inputting the multiplier, each BL line is connected to the anode of a column of RRAM, and WL [7:0] is the port for inputting the multiplicand, each BL line is connected to the cathode of a column of RRAM; the multiplicand is a [7:0], the multiplier is b [7:0 ]; when a [ i ] =0 or b [ j ] =0, the corresponding WL [ i ] or BL [ j ] is added with a voltage of 0V; when a [ i ] =1, WL [ i ] is added with-1V voltage; when b [ j ] =1, BL [ j ] is added with 1V voltage; the state of RRAM is determined by the voltage difference between the positive pole and the negative pole, namely the voltage difference between BL [ j ] and WL [ i ]; when a [ i ] =1 and b [ j ] =0 or a [ i ] =0 and b [ j ] =1, the voltage difference across the RRAM is 1V, the RRAM state is not changed; similarly, when a [ i ] =0 and b [ j ] =0, the voltage difference between two ends of the RRAM is 0V; only when a [ i ] =1 and b [ j ] =1, the voltage difference between two ends of the RRAM is 2V, and the set threshold voltage is reached;
by inputting the multiplicand a [7:0] and multiplier b [7:0], it is possible for the 8x 8RRAM array to compute and store all intermediate results of a [7:0] xb [7:0], i.e., the product of all a [ i ] xb [ j ];
3) respectively placing reading voltage on each row of RRAM in the RRAM array, and storing the read intermediate result stored in the RRAM into the RS trigger array after the intermediate result is amplified by an amplifier;
4) the output of the RS trigger array is used as the input of an adder, and after N read cycles, the adder calculates the final result of multiplication; where N is the number of columns in the RRAM array.
2. The method of claim 1 wherein the a [7:0], b [7:0] signals representing the multiplicand and multiplier each last for 1ns to ensure that intermediate results are successfully written into the RRAM.
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