CN110168642A - Semiconductor device and its working method, electronic component and electronic equipment - Google Patents

Semiconductor device and its working method, electronic component and electronic equipment Download PDF

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Publication number
CN110168642A
CN110168642A CN201880006239.6A CN201880006239A CN110168642A CN 110168642 A CN110168642 A CN 110168642A CN 201880006239 A CN201880006239 A CN 201880006239A CN 110168642 A CN110168642 A CN 110168642A
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state
circuit
voltage
node
transistor
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CN110168642B (en
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石津贵彦
斋藤利彦
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Computing Systems (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Memory System (AREA)

Abstract

Efficiently reduce the power consumption of semiconductor device.Semiconductor device includes electric power controller, cell array and the peripheral circuit for driving unit array.Cell array includes wordline, bit line to, the fallback circuit of storage unit, the data of redundant memory cell.The the first power supply localization for being able to carry out power gating is arranged in row circuit and column circuits, and the second source localization for being able to carry out power gating is arranged in cell array.As the much lower a low-power consumption mode of its power dissipation ratio standby mode of the Working mode set of storage device.Electric power controller selects one from multiple low-power consumption modes and carries out the control for storage device to be transferred to selected low-power consumption mode.

Description

Semiconductor device and its working method, electronic component and electronic equipment
Technical field
The description of the present application, attached drawing and claims (hereinafter referred to as " this specification etc. ") are related to a kind of semiconductor Device and its working method etc..Note that one embodiment of the present invention be not limited to illustrated by technical field.
In this specification etc, semiconductor device refers to the device using characteristic of semiconductor and refers to including semiconductor element Circuit and the device including the circuit of (transistor, diode, photodiode etc.) etc..In addition, semiconductor device refers to energy All devices enough to be played a role using characteristic of semiconductor.For example, the example as semiconductor device, there is integrated circuit, tool The electronic component of chip is accommodated in the chip of standby integrated circuit, encapsulation.In addition, storage device, display device, light emitting device, Lighting device, electronic component and electronic equipment etc. are semiconductor device in itself sometimes, or sometimes include semiconductor device.
Background technique
The low power consumption of electronic equipment is taken seriously.Therefore, the low power consumption of the integrated circuits such as CPU (IC) is set as circuit Free-revving engine on meter.Power consumption (dynamic power) when the power consumption of IC is broadly divided into work and function when not working (when standby) Consume (static power) both power consumptions.When in order to realize high performance when improving working frequency, dynamic power increases.Static function The major part of rate is the power being consumed by the leakage current of transistor.As leakage current, there are sub-threshold leakage current, grid Pole tunnel leakage current, gate induced drain leakage (GIDL:Gate-induced drain leakage) electric current, knot tunnelling are let out Leakage current.These leakage currents increase with the progress of the micromation of transistor, therefore, make IC high performance or highly integrated When change, the increase of power consumption can become very big barrier.
In order to reduce the power consumption of semiconductor device, work is not needed by stopping using power gating or Clock gating Circuit.Power supply supply stops in power gating, thus there is the effect for cutting down standby power.In order to carry out power supply door in CPU Control needs to back up the storage content of register or cache memory in nonvolatile memory.
The transistor that its known channel formation region is formed by metal oxide is (hereinafter, sometimes referred to as " oxide semiconductor Transistor " or " OS transistor ").A kind of characteristic minimum by the off-state current using OS transistor is had been presented for, is being stopped Also the fallback circuit of data is able to maintain when power supply.For example, patent document 1,2 and non-patent literature 1 propose and have using OS The SRAM (static random access memory) of the fallback circuit of transistor.
[advanced technical literature]
[patent document]
[patent document 1] Japanese patent application discloses 2015-195075 bulletin
[patent document 2] Japanese patent application discloses 2016-139450 bulletin
[non-patent literature]
[non-patent literature 1] T.Ishizuetal., " SRAMwithC-AxisAlignedCrystallineOxideSem Iconductor:LeakagePowerReductionTechniqueforMicroprocess orCaches, " Int.MemoryWorkshop, 2014, pp.106-103.
Summary of the invention
The technical problems to be solved by the invention
The first purpose of one embodiment of the present invention is to provide a kind of storage device or height for being able to carry out power gating Effect ground reduces the power consumption of storage device.
The record of multiple purposes does not interfere mutually mutual presence.An embodiment of the invention does not need to solve institute There is above-mentioned purpose.Purpose other than the above-mentioned purpose enumerated be learnt from the record nature of this specification etc., and be possible at For the purpose of one embodiment of the present invention.
Solve the means of technical problem
One embodiment of the present invention is a kind of including electric power controller, cell array and for driving unit array The storage device of peripheral circuit.Cell array includes wordline, bit line to, the backup of storage unit, the data of redundant memory cell Circuit.The the first power supply localization for being able to carry out power gating is arranged in peripheral circuit, and cell array setting is being able to carry out power supply The second source localization of gate.As the much lower a low-power consumption mould of its power dissipation ratio standby mode of the Working mode set of storage device Formula.Electric power controller selects one from multiple low-power consumption modes and carries out for storage device is transferred to selected low function The control of consumption mode.
In this specification etc, the ordinal numbers such as " first ", " second ", " third " are attached sometimes for order of representation.Or Person sometimes uses in order to avoid obscuring for constituent element, and in the case, the use of these ordinal numbers is not configured to limit The number of constituent element, nor in order to limit sequence.Illustrate for example, " first " can be exchanged for " second " or " third " One mode of invention.
In this specification etc, open in this specification etc.: the case where X is electrically connected with Y when being recorded as X and being connect with Y；X The case where functionally being connect with Y；And X and Y the case where being directly connected to.Therefore, it is not limited to connect shown in attached drawing or text Connection relationship as defined in relationship etc. is connect, the connection relationship other than connection relationship shown in attached drawing or text is also in attached drawing or Wen Zhongji It carries.X and Y is object (for example, device, element, circuit, wiring, electrode, terminal, conductive film, layer etc.).
Transistor includes grid, source electrode and these three terminals that drain.Grid is used as controlling the conduction and cut-off of transistor The control terminal of state.In two input and output terminals for being used as source electrode or drain electrode, according to the type or supply of transistor One terminal is used as source electrode and another terminal is used as drain electrode by the potential level to each terminal.Therefore, in this specification etc. In, source electrode and drain electrode can exchange mutually.In addition, in this specification etc, two terminals other than grid are known as sometimes One terminal and Second terminal.
Voltage refers to the potential difference between some current potential and normal potential (for example, earthing potential (GND) or source electric potential) mostly. Thus, it is possible to which voltage is referred to as current potential.Current potential is relativity.Therefore, it even if being recorded as " GND ", is also not necessarily meant to refer to 0V's.
Node can be referred to as according to circuit structure or apparatus structure etc. terminal, wiring, electrode, conductive layer, electric conductor or Extrinsic region etc..In addition, terminal, wiring etc. can also be referred to as node.
In this specification etc, " film " and " layer " can according to circumstances or situation is mutually exchanged.For example, can incite somebody to action sometimes " conductive layer " is referred to as " conductive film ".For example, " insulating film " can be referred to as " insulating layer " sometimes.
In this specification etc, metal oxide (metal oxide) refers to the oxide of sensu lato metal.Metal oxygen Compound is classified as oxide-insulator, oxide conductor (including transparent oxide conductor) and oxide semiconductor (Oxide Semiconductor can also be referred to as OS) etc..For example, will be used in the channel formation region of transistor sometimes Metal oxide be known as oxide semiconductor.
In this specification etc, in case of no particular description, the metal for the channel formation region of transistor Oxide, including the metal oxide comprising nitrogen.In addition it is also possible to which the metal oxide comprising nitrogen is known as metal oxynitrides (metal oxynitride)。
Invention effect
One embodiment of the present invention can provide a kind of storage device for being able to carry out power gating or can be efficiently Reduce the power consumption of storage device.
The record of multiple effects does not interfere the presence of other effects.In addition, one embodiment of the present invention does not need to have All said effect.In one embodiment of the present invention, it is above-mentioned except purpose, effect and novel feature can be from this specification In description and attached drawing learn naturally.
Detailed description of the invention
[Fig. 1] shows the block diagram of the configuration example of storage device.
[Fig. 2] A: the circuit diagram of the configuration example of unit is shown.B: the timing diagram of the worked example of storage device is shown.
[Fig. 3] shows the circuit diagram of the configuration example of column circuits.
The state transition diagram of [Fig. 4] storage device.
[Fig. 5] shows the timing diagram of the work sequence example of storage device.
[Fig. 6] shows the timing diagram of the work sequence example of storage device.
[Fig. 7] shows the timing diagram of the work sequence example of storage device.
[Fig. 8] shows the timing diagram of the work sequence example of storage device.
[Fig. 9] shows the block diagram of the configuration example of storage device.
[Figure 10] shows the timing diagram of the work sequence example of storage device.
[Figure 11] shows the block diagram of the configuration example of storage device.
[Figure 12] A: the circuit diagram of the configuration example of unit is shown.B: the timing diagram of the worked example of storage device is shown.
[Figure 13] A: the circuit diagram of the configuration example of unit is shown.B: the timing diagram of the worked example of storage device is shown.
[Figure 14] A and B: the circuit diagram of the configuration example of unit is shown.
[Figure 15] shows the block diagram of the configuration example of CPU.
[Figure 16] shows the circuit diagram of the configuration example of trigger.
[Figure 17] shows the timing diagram of the worked example of trigger.
[Figure 18] A: the flow chart of the manufacturing method example of electronic component is shown.B: the configuration example of electronic component is shown Stereoscopic schematic diagram.
[Figure 19] A to F: the figure of the configuration example of electronic equipment is shown.
[Figure 20] shows the sectional view of the laminated construction example of storage device.
[Figure 21] A and B: the sectional view of the configuration example of OS transistor is shown.
[Figure 22] A and B: the sectional view of the configuration example of OS transistor is shown.
Specific embodiment
Illustrate embodiments of the present invention below.Note that an embodiment of the invention is not limited to following explanation, institute The those of ordinary skill for belonging to technical field should be readily understood that a fact, be exactly the present invention without departing from the spirit and its Under conditions of range, mode and detailed content can be transformed to various forms.Therefore, one embodiment of the present invention It is not construed as being limited in the content described in embodiment as shown below.
Multiple embodiments shown below can be appropriately combined.In addition, showing multiple knots in one embodiment In the case where structure example (including manufacturing method example, working method example etc.), it can be appropriately combined the configuration example, and One or more configuration example documented by other embodiments can be appropriately combined.
In the accompanying drawings, be denoted by the same reference numeral sometimes same inscape, constituent element with the same function, The constituent element of same material or the constituent element being formed simultaneously etc., and its repeated explanation is omitted sometimes.
In the accompanying drawings, convenient for clearly demonstrating, to exaggerate size, the thickness of layer and region etc. sometimes.Therefore, the present invention is simultaneously The size being not limited in attached drawing.In addition, in the accompanying drawings, it is schematically shown ideal example, therefore the present invention is not limited to Shape shown in the drawings or numerical value etc..For example, may include because of noise caused by signal, voltage or electric current uneven or It is uneven etc. because of signal caused by timing offset, voltage or electric current.
In the present specification, for convenience's sake, sometimes using the words and phrases of the expressions such as "upper" "lower" configuration referring to attached drawing Illustrate the positional relationship of constituent element.In addition, the positional relationship of constituent element according to description each component direction suitably Change.Therefore, words and phrases disclosed in the specification are not limited to, words and phrases according to circumstances can be suitably changed.
(embodiment 1)
In the present embodiment, as an example of storage device, illustrate the SRAM for being able to carry out power gating.
" storage device 100 "
Fig. 1 is the functional-block diagram for showing the configuration example of storage device.Storage device 100 shown in FIG. 1 includes power supply Administrative unit (PMU) 105, cell array 110, peripheral circuit 120 and power switch 150 to 153.
In storage device 100 data of sensing element array 110 and to cell array 110 be written data.Data RDA is Data are read, data WDA is write-in data.To 100 input clock signal CLK1, CLK of storage device, address signal ADDR and letter Number RST, INT1, CE, GW, BW.Signal RST is reset signal, and is input into PMU105 and peripheral circuit 120.Signal INT1 It is interrupt signal.Signal CE is chip enable signal, and signal GW is global write-in enable signal, and signal BW is that byte write-in is enabled Signal.
To storage device 100 input voltage VDD, VDH, VDM, VDML, VSS, VSM, VBG.Voltage VDD, VDM, VDML, VDH is high level supply voltage.Voltage VSS, VSM are low level power voltage, e.g. GND (earthing potential) or 0V.
Cell array 110 includes unit 10, wordline WL, bit line BL, BLB and wiring OGL.Bit line BL, BLB are referred to as Local bitline.Sometimes the wiring being made of the bit line BL and bit line BLB that are arranged in same row is to referred to as bit line to (BL, BLB).
Peripheral circuit 120 includes controller 122, row circuit 123, column circuits 124 and backup/restoration driver 125.
Controller 122 includes the function of to signal CE, GW, BW progress logical operation and determining operating mode；Generation is used to Execute the function of the row circuit 123 of determined operating mode and the control signal of column circuits 124.Alternatively, it is also possible to control The register of temporarily storage address signal ADDR, signal CE, GW, BW and data RDA, WDA is set in device 122.
Row circuit 123 includes line decoder 131 and word line driver 132.Line decoder 131 carries out address signal ADDR Decoding generates the control signal of word line driver 132.Word line driver 132 makes the wordline of row specified by address signal ADDR As selection state.
Column circuits 124 include column decoder 133, pre-charge circuit 134, local bitline MUX (multiplexer) 135, read and put Big device 136, write driver 137 and output driver 138.Bit line of the column circuits 124 to column specified by address signal ADDR BL carries out the write-in of data and the reading of data.The circuit structure of column circuits 124 is explained below.
In storage device 100, above-mentioned each circuit, each signal and each voltage can be suitably accepted or rejected as needed.Alternatively, Other circuits or other signals can also be added.In addition, storage device 100 input signal and output signal structure (for example, Bit wide) it is set according to the operating mode of storage device 100 and structure of cell array 110 etc..
<power supply localization>
Storage device 100 includes multiple power supply localization.Power supply localization 160,161 and 162 is provided in the example of Fig. 1.It is right Power supply localization 160 is without power gating.Power gating is carried out to power supply localization 161,162.The obstructed overpower switch of voltage VSS And it is input into each power supply localization 160,161 and 162.
PMU105 is provided in power supply localization 160.Obstructed overpower switch and to 160 input voltage VDD of power supply localization.
Peripheral circuit 120 and virtual voltage line V_VDD, V_VDH are provided in power supply localization 161.Power switch 150 controls Voltage VDD is supplied to virtual voltage line V_VDD (hereinafter referred to as V_VDD line).Power switch 151 is controlled to virtual voltage line V_ VDH (hereinafter referred to as V_VDH line) supplies voltage VDH.Voltage VDH is the voltage used in backup/restoration driver 125.
Cell array 110 and virtual voltage line V_VDM (hereinafter referred to as, V_VDM line) are provided in power supply localization 162.Function Rate switch 152 is controlled to V_VDM line input voltage VDM, and power switch 153 is controlled to V_VDM line input voltage VDML.Voltage VDML is less than the voltage of voltage VDM.Obstructed overpower switch and to power supply localization 162 input voltage VSM, VBG.
<PMU>
PMU105 controls storage device 100 in low-power consumption mode.To PMU105 input clock signal CLK1 and signal INT1.Signal INT1 is interrupt signal.A variety of interrupt signals can be inputted to PMU105.PMU105 is according to signal CLK1, INT1 Generate signal PSE1, PSE2, PSE3, BLFE, BLRE, NDRE and PGM.
Signal PSE1, PSE2 and PSE3 are power switch enable signals.Signal PSE1 control power switch 150,151 is opened It opens/closes, signal PSE2 controls unlatching/closing of power switch 152, and signal PSE3 controls unlatching/pass of power switch 153 It closes.Here, power switch 150 is in the open state when signal PSE1 is " H ", the power switch 150 when signal PSE1 is " L " It is in close state.Unlatching/closing control of other power switch is also same.
Signal NDRE, BLFE, BLRE and PGM are to control signal used in low-power consumption mode.Signal NDRE is node Reset enable signal, and the reset work of node Q, Qb of control unit 10.Signal NDRE is input into row circuit 123.Row electricity Road 123 makes all wordline WL of cell array 110 become selection state according to signal NDRE.Signal BLFE, BLRE are input into Column circuits 124.Signal BLFE is bit lines float enable signal, and controls the work for making bit line become quick condition to (BL, BLB) Make.Signal BLRE is that bit line resets enable signal, and reset work of the control bit line to (BL, BLB).
Signal PGM is input into backup/restoration driver 125.Backup/restoration driver 125 makes unit according to signal PGM All wiring OGL of array 110 become selection state.For example, backup/restoration driver 125 carries out level shift to signal PGM Generate the selection signal of wiring OGL.The high level voltage of selection signal is VDH.Voltage VDH is higher than voltage VDD.In selection signal High level voltage can be in the case where VDD, not need setting power switch 151.
<unit>
Fig. 2A shows the circuit structure example of unit 10.Unit 10 includes storage unit 20, fallback circuit 30.Storage unit 20 have circuit structure identical with standard 6T (transistor) sram cell, by bistable circuit 25, transistor MT1, MT2 structure At.Bistable circuit 25 is electrically connected with the power supply line (hereinafter referred to as VSM line) of V_VDM line, supply voltage VSM.
In the example of Fig. 2A, bistable circuit 25 is the latch cicuit being made of two CMOS inverter circuits.Node Q, Qb is respectively the interconnecting piece of the input terminal and the output terminal of two CMOS inverter circuits, and is the holding section of complementary data Point.When node Q/Qb, which becomes " H "/" L " or node Q/Qb, becomes " L "/" H ", bistable circuit 25 becomes stable state.It is brilliant Body pipe MT1, MT2 are transfering transistor.By the on state between transistor MT1 control bit line BL and node Q, by transistor On state between MT2 control bit line BLB and node Qb.
Fallback circuit 30 is the circuit for the data of redundant memory cell 20.By the way that backup electricity is arranged in each unit 10 Road 30 is able to carry out the power gating of power supply localization 162.
Fallback circuit 30 is electrically connected to the pressure-wire (hereinafter referred to as VSS line) of supply voltage VSS, supplies the electricity of voltage VBG Crimping (hereinafter referred to as VBG line).Fallback circuit 30 is made of two 1T1C (capacitor) type DRAM cells.Fallback circuit 30 wraps Include node SN1, SN2, transistor MO1, MO2 and capacitor C1, C2.Node SN1, SN2 are the data for keeping node Q, Qb Holding node.Capacitor C1, C2 are the storages for keeping the voltage of node SN1, SN2.Transistor MO1 control section On state between point Q and node SN1, the on state between transistor MO2 control node Qb and node SN2.
In order to make fallback circuit 30 keep data for a long time, the crystalline substance minimum as transistor MO1, MO2 selection off-state current Body pipe.As transistor MO1, MO2, it is preferable to use OS transistors.It, can be with by using OS transistor as transistor MO1, MO2 Charge is inhibited to leak from capacitor C1, C2, thus fallback circuit 30 can keep data for a long time.That is, fallback circuit 30 are used as non-volatile memory.
Since the band gap of metal oxide is 2.5eV or more, OS transistor because of the leakage electricity caused by thermal excitation Flow it is small, and as described above off-state current it is minimum.It can will be with the OFF state of the standardized OS transistor of the channel width of transistor Current reduction is to a few yA/ μm or more and a few zA/ μm or less Zuo You.As the metal oxide for being applied to channel formation region, have (M is for Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide and In-M-Zn oxide Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) etc..In addition, the oxide comprising indium and zinc can also also comprising selected from aluminium, gallium, One of yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium etc. are a variety of.
By using OS transistor as transistor MO1, MO2, fallback circuit 30 can be laminated in by Si transistor structure At storage unit 20 on, it is possible thereby to inhibit the area overhead of the unit 10 occurred because fallback circuit 30 are arranged.
Transistor MO1, MO2 include back grid, and back grid is electrically connected to VBG line.For example, voltage VBG is to make transistor The voltage that the threshold voltage of MO1, MO2 drift about to positive side.Furthermore, it is possible to have backup/restoration driver 125 according to backup The work of circuit 30 and the function of being input to the voltage of VBG line can be changed.Transistor MO1, MO2 can be not include back grid OS transistor.
<column circuits>
Illustrate the circuit structure example of column circuits 124 referring to Fig. 3.
(pre-charge circuit 134)
Pre-charge circuit 134 includes pre-charge circuit 51,52.Pre-charge circuit 51,52 is controlled by signal PRCH1, PRCH2 System.Bit line is pre-charged to voltage Vpr1 to (BL, BLB) by pre-charge circuit 51, and pre-charge circuit 52 is by bit line to (BL, BLB) It is pre-charged to voltage Vpr2.Pre-charge circuit 51,52 is used as the balanced device for the voltage smoothing for making bit line to (BL, BLB).
Pre-charge circuit 51 is for carrying out preliminary filling to (BL, BLB) to bit line in normal operation mode and standby mode The circuit of electricity.In addition, pre-charge circuit 52 is pre- for carrying out to bit line to (BL, BLB) under recovery state and Status of Backups The circuit of charging.Voltage Vpr2 is recovery pre-charge voltage, and is backup pre-charge voltage.
(sense amplifier 136)
To 136 input signal PRCH3, SNS of sense amplifier.Sense amplifier 136 include local bitline to (LRBL, LRBLB), pre-charge circuit 53, sense amplifier 55, RS (reset-set) latch cicuit 56, inverter circuit 57,58 and crystalline substance Body pipe MP3, MP4.
LRBL, LRBLB are local readout bit lines.A local bitline pair is provided with to (BL, BLB) to multiple bit lines (LRBL, LRBLB).Here, being provided with a local bitline to (LRBL, LRBLB) to (BL, BLB) to four bit lines.
Local bitline is pre-charged to voltage Vpr1 to (LRBL, LRBLB) according to signal PRCH3 by pre-charge circuit 53.In advance Charging circuit 53 is used as the balanced device for the voltage smoothing for making local bitline to (LRBL, LRBLB).
Sense amplifier 55 is detected from unit 10 and is read by amplifying local bitline to the voltage difference of (LRBL, LRBLB) Data out.Sense amplifier 55 includes transistor MN3 and latch cicuit 55a and is electrically connected to VSS line, V_VDD line.Latch electricity Road 55a is made of two inverter circuits.Node QS, QSb are the holding nodes of latch cicuit 55a, are electrically connected to RS and latch electricity The input on road 56.The data detected of sense amplifier 55 are kept by RS latch cicuit 56.RS latch cicuit 56 is by two NAND Circuit is constituted.Data LATOB, LATO that RS latch cicuit 56 is kept are input into inverter circuit 57,58.Inverter circuit 57 output (data DO) and the output (data DOB) of inverter circuit 58 are input into output driver 138.
Transistor MP3, MP4 control local bitline to the on state between (LRBL, LRBLB) and sense amplifier 55 with And local bitline is to the on state between (LRBL, LRBLB) and RS latch cicuit 56.By signal SNS control transistor MP3, Unlatching/closing of MP4.Signal SNS also controls unlatching/closing of transistor MN3.Signal SNS is for making sense amplifier 55 The sense amplifier enable signal being in active state.When sense amplifier 55 is in active state, sense amplifier 55 with Local bitline between (LRBL, LRBLB) be in nonconducting state.
(write driver 137)
Write driver 137 is for the circuit to local bitline to (LWBL, LWBLB) write-in data.Write driver 137 include inverter circuit 59.
LWBL, LWBLB are to be partially written bit line.A local bitline pair is provided with to (BL, BLB) to multiple bit lines (LWBL, LWBLB).Here, being provided with a local bitline to (LWBL, LWBLB) to (BL, BLB) to four bit lines.
Data DIN is write-in data.Data DIN is input into local bitline LWBL and inverter circuit 59.Phase inverter electricity The output (data DINB) on road 59 is input into local bitline LWBLB.
(local bitline MUX135)
Local bitline MUX135 includes MUX135r and MUX135w and is entered signal RDE [3:0] and WTE [15:0].Letter Number RDE [3:0] is to read enable signal, and signal WTE [15:0] is write-in enable signal.
MUX135r selection reads the bit line of the column of data to (BL, BLB).By MUX135r select multiple bit lines to (BL, BLB) (LRBL, LRBLB) is electrically connected from different local bitlines respectively.
MUX135r is made of transistor MP1, MP2.Any one into transistor MP1, MP2 input signal RDE [3:0] Position.Transistor MP1, MP2 are used as control bit line to (BL, BLB) and local bitline to the conducting shape between (LRBL, LRBLB) The switch of state.
The bit line of the column of MUX135w selection write-in data is to (BL, BLB).By MUX135w select multiple bit lines to (BL, BLB) (LWBL, LWBLB) is electrically connected from different local bitlines respectively.MUX135w is made of transistor MN1, MN2.Xiang Jing Any one in body pipe MN1, MN2 input signal WTE [15:0].Transistor MN1, MN2 be used as control bit line to (BL, BLB) and local bitline is to the switch of the on state between (LWBL, LWBLB).
The circuit structure of column circuits 124 is not limited to Fig. 3.It can be suitably changed according to input signal, input voltage etc.. In the example in figure 3, pre-charge circuit 52 is made of three n-channel type transistors, but sometimes by three p-channel type transistors It constitutes.
" operating mode "
Then, the operating mode of storage device 100, especially low-power consumption mode are illustrated.Table 1 shows storage device 100 truth table.Here, the bit wide of signal BW is 4, the bit wide of data WDA, RDA is 32.
[table 1]
※ PG: power gating
In 0 write mode of byte, the work for the data that 1 byte (8) for being allocated in signal BW [0] is written is carried out.Example Such as, it in 0 write mode of byte, is written data WDA [7:0].In byte write-in work, BW [1], BW [2], BW [3] are " H " When write-in data be WDA [15:8], WDA [23:16], WDA [31:24] respectively.
<power gating sequence>
Because being provided with fallback circuit 30 in each unit 10, it is able to carry out the power gating of power supply localization 162.Fig. 2 B One example of the power gating sequence relative to power supply localization 162 is shown.In fig. 2b, during the expression such as t1 and t2.
(usually work, Normal Operation)
Before t1, storage device 100 is in usual working condition (write state or reading state).Storage device 100 Progress similarly usually works with single-port SRAM.During signal NDRE is " L ", row circuit 123 is according to controller 122 Control signal works.During signal BLFE, BLRE are " L ", column circuits 124 are according to the control signal of controller 122 It works.Power switch 150 to 152 is in the open state, and power switch 153 is in close state.
(backup, Backup)
By being input into backup/restoration driver 125 in the signal PGM of t1 " H ", back-up job starts.Here, in t1 Node Q/Qb becomes " H "/" L ", and node SN1/SN2 becomes " L "/" H ".The wordline WL of all rows becomes " L ", therefore all units 10 are in nonselection mode.
Backup/restoration driver 125 carries out level transfer to signal PGM and generates selection signal, by all selection signals It is output to wiring OGL.Become open state in transistor MO1, MO2 of fallback circuit 30, to the section of node SN1, SN2 write-in t1 The data of point Q, Qb.The voltage of node SN1 rises to VDM from VSM, and the voltage of node SN2 is reduced to VSM from VDM.In t2 signal PGM becomes " L ", and back-up job terminates.
(power gating, Power-gating (PG))
Signal PSE2 is set to become " L " in t2 by PMU105, the power gating of power supply localization 162 starts.Since power is opened Closing 152 becomes closed state, and the voltage of V_VDM line is reduced to VSM from VDM.It is reduced by the voltage of V_VDM line, storage unit 20 become inactive state.The data of storage unit 20 disappear, but fallback circuit 30 continues to keep data.
Here, making bit line be in quick condition to (BL, BLB) when power supply localization 162 is not powered.As a result, PMU105 is so that signal PSE2 makes signal BLFE become " H " as the opportunity of " L ".
After the time tl, the logic regardless of signal BLFE, transistor MN1, MN2, MP1 of local bitline MUX135 And MP2 is also at closed state.By inputting the signal BLFE of " H ", the precharge electricity of pre-charge circuit 134 to column circuits 124 Road 51,52 becomes closed state, therefore whole bit lines of cell array 110 become quick condition to (BL, BLB).
(restoring, Recovery)
Resume work the work for referring to that the data kept according to fallback circuit 30 restore the data of storage unit 20 Make.In resuming work, bistable circuit 25 is used as the sense amplifier for detecting the data that storage unit 20 is kept. In resuming work, bistable circuit 25 is used as the sense amplifier of the data for detection node Q/Qb.
The signal PGM of " H ", beginning of resuming work are generated in t3 by PMU105.Transistor MO1, MO2 become opening state State, so the charge of capacitor C1 is allocated in node Q, node SN1, the charge of capacitor C2 is allocated in node Qb, node SN2.
Keep power switch 152 in the open state in t4, to V_VDM line input voltage VDM.V_VDM line is electrically charged, then Bistable circuit 25 becomes active state.The voltage difference of the amplification of bistable circuit 25 node Q and node Qb.Finally, node Q, SN1 Voltage become VDM, the voltage of node Qb, SN2 becomes VSM.In other words, the state ash of node Q/Qb arrives the state of t1 again ("H"/"L").PMU105 makes signal PGM become " L " in t5, so that signal BLFE is become " L " in t6, end of resuming work.
" low-power consumption mode "
Fig. 4 shows the state transition diagram of storage device 100.As the state of storage device 100, there is electric power starting (PowerOn) state SS1, reset (Reset) state SS2, standby (Stand-by) state SS3, write-in (Writing) state SS4, reading (Reading) state SS5, bit lines float (BitLineFloating) state SS11, suspend mode (Sleep) state SS12, cell array localization power gating (PGforCellArray (CA) Domain) state SS13, whole localization PG (PGforAllDomains) state SS14, backup (Backup) state SS21 to SS23, restore (Recovery) state SS25, SS26.If the truth table of table 1 indicates, the state of storage device 100 is shifted according to external signal and internal signal, under each state Execute corresponding operating mode.
There are four types of low-power consumption modes for the tool of storage device 100.(1) bit lines float mode, (2) suspend mode, (3) cell array Localization PG mode, (4) whole localization PG modes.PMU105 manages the operating mode of the storage device 100 under low power consumpting state. PMU105 selects an operating mode from above-mentioned low-power consumption mode, and storage device 100 is made to execute regulation work sequence.
(bit lines float mode)
In standby mode, bit line is boosted into pre-charge voltage (Vpr1) to (BL, BLB).In bit line floating mode, make position Line becomes quick condition to (BL, BLB).The data of storage unit 20 do not disappear.
(suspend mode)
In stand-by mode, voltage VDM is supplied to power supply localization 162.In suspend mode, supplied to power supply localization 162 Voltage VDML lower than voltage VDM.Voltage VDML is the big voltage of degree that the data of storage unit 20 do not disappear.Make bit line pair (BL, BLB) becomes quick condition.
(cell array localization PG mode)
Stop supplying voltage VDM to power supply localization 162.Bit line is set to become quick condition to (BL, BLB).Storage unit 20 Data disappear.
(whole localization PG modes)
In whole localization PG modes, power gating is carried out to the whole localization for being able to carry out power gating.Stop to electricity Source localization 161 supplies voltage VDD, VDH, and stops supplying voltage VDM to power supply localization 162.The data of storage unit 20 disappear It loses.
The break-even time (BET) that can obtain lower power consumption effect in four low-power consumption modes is different from each other, i.e., Meet BET_blfl < BET_slp < BET_pgca < BET_pgall.BET_blfl, BET_slp, BET_pgca and BET_ Pgall is the BET of bit lines float mode, suspend mode, cell array localization PG mode and whole localization PG modes respectively.Pass through With the different multiple low-power consumption modes of BET, the power consumption of storage device 100 can be efficiently reduced.
When being transferred to cell array localization PG state SS13 from standby mode SS3, need the data of storage unit 20 The back-up job of fallback circuit 30 is backuped to, and when being restored to standby mode SS3 from cell array localization PG state SS13, it needs Want resuming work for the data of storage unit 20.Whole localization PG state SS14 are also same.BET_pgca, BET_ as a result, Pgall longer.When the stationary state of (such as several hundred milliseconds) for a long time occurs, can obtain due to whole localization PG modes The effect of lower power consumption.
In bit line floating mode, the data of storage unit 20 do not disappear.Standby mode SS3 and bit lines float state SS11 Between transfer do not need to back up and resume work.Therefore, in the transfer between standby mode SS3 and bit lines float state SS11, The expense of time and energy is small.Suspend mode is also same.
In suspend mode, the supply voltage of cell array 110 is reduced to VDML from VDM, it is possible to reduce storage dress Set 100 standby power.Standby power is the power consumption occurred by the leakage current of transistor.The master of the leakage current of transistor The subthreshold current of reason is wanted exponentially to reduce when supply voltage becomes some value or less.As a result, by suspend mode band The effect for 110 standby power reduction of cell array come is very high.For example, being 0V, VDM 1.2V, VDML 0.6V in VSS (=VDM/2) under conditions of, the leakage current of suspend mode becomes 20% to 30% left side of the leakage current of standby mode sometimes It is right.BET_slp changes according to VDML, such as can set in a manner of as the median of BET_blfl and BET_pgca VDML。
The difference of BET_blfl and BET_pgca becomes longer in many cases,.It can be made up by providing suspend mode The difference, it is possible to more appropriate low-power consumption mode is selected according to quiescent time.For example, in no suspend mode and BET_blfl For 10 μ sec and when quiescent time is 6msec frequent occurrence in the case that BET_pgca is 10msec state, it is difficult to effectively Reduce power consumption.By providing suspend mode, the efficiency for reducing power consumption can be improved.
Illustrate the work sequence in the low-power consumption mode of storage device 100 referring to Fig. 5 to Fig. 8.TB1, TR1 etc. are indicated The state of circuit, stand-by time until supply voltage etc. is stablized.The length of TB1, TR1 etc. are 1 more than the clock cycle, portion Point stand-by time was 0 clock cycle sometimes.
(bit lines float sequence, sleep sequence)
Illustrate an example of bit lines float sequence, sleep sequence referring to Fig. 5.
At standby mode SS3, storage device 100 remains static.For example, whole bit lines are to (BL, BLB) by preliminary filling Circuit 51 is pre-charged to voltage Vpr1.
For example, execution is transferred to bit line from standby mode and floats when the time of standby mode SS3 being more than setting time tk3 The work sequence of dynamic model formula.The setting time as the condition for shifting the state of storage device 100 in time tk3 is according to each The setting such as BET of low-power consumption mode.
The signal BLFE that " H " is issued by PMU105, is transferred to bit lines float state SS11 from standby mode SS3.Pass through The input of the signal BLFE of " H ", column circuits 124 make whole bit lines be in quick condition to (BL, BLB).
When the storage device 100 of bit line quick condition SS11 is accessed, PMU105 makes signal BLFE become " L " and make to deposit Storage device 100 is restored to standby mode SS3.
When the time of bit line quick condition SS11 being more than setting time tk11, the signal PSE2 of PMU105 sending " L ", The signal PSE3 of " H ", makes storage device 100 be transferred to dormant state SS12.Power switch 152 becomes closed state, and power is opened Closing 153 becomes open state, therefore the voltage of V_VDM line is reduced to VDML from VDM.The signal BLFE of " H " continues to be input to column Circuit 124, so whole bit lines remain quick condition to (BL, BLB).
At dormant state SS12, when storage device 100 is accessed, PMU105 issues the letter of the signal PSE2 of " H ", " L " Number PSE3, " L " signal BLFE and so that the state of storage device 100 is restored to standby mode SS3.Power switch 152, which becomes, to be opened State is opened, power switch 153 becomes closed state, so the voltage of V_VDM line rises to VDM from VDML.
At write state SS4, reading state SS5, controlled by controller 122, storage device 100 carries out write-in work Make, read work.
(cell array localization PG sequence)
During Fig. 5 after TB2, when the time of dormant state SS12 being more than setting time tk12, controlled by PMU105 System executes the work sequence that cell array power gating mode is transferred to from suspend mode.Illustrate above-mentioned work sequence referring to Fig. 6 An example.
In order to become cell array PG state SS13, back-up job is carried out.By PMU105 issue " H " signal PSE2, The signal PSE3 of " L " is transferred to Status of Backups SS21 from dormant state SS12.The voltage of V_VDM line rises, and stablizes in VDM, so PMU105 makes signal PGM become " H " afterwards.All wiring OGL are in selection state, each unit 10 by backup/restoration driver 125 The data of node Q, Qb be written to node SN1, SN2 (referring to Fig. 2A, Fig. 2 B) of fallback circuit 30.
So that signal PSE2 is become " L " by PMU105, is transferred to unit localization PG state SS13 from Status of Backups SS21.By Become closed state in power switch 152, so the voltage of V_VDM line reduces and becomes VSM.Alternatively, it is also possible to make signal The opportunity of PGM decline declines signal PSE2.
When storage device 100 is accessed at cell array localization PG state SS13, is controlled by PMU105, execute recovery Work (referring to Fig. 2A, Fig. 2 B).The signal PGM that H " is issued by PMU105, is transferred to from cell array localization PG state SS13 Recovery state SS25.PMU105 makes signal PSE2 become " H " when signal PGM is " H ", and power switch 152 is made to be in opening state State.The voltage of V_VDM line rises and becomes VDM.PMU105 makes signal PGM become " L ", and signal BLFE is then made to become " L ", by This is transferred to standby mode SS3 from state SS25 is restored.
For example, power switch can also be set in power supply localization 162 when cell array 110 is made of multiple subarrays, with It can control to each subarray and supply high level supply voltage (VDM, VDML).By above structure, power supply can be reduced The granularity spatially of the power gating of localization 162.
(whole localization PG sequences)
For example, executing when the quiescent time that can be predicted as storage device 100 being more than BET_pgall from standby mode It is transferred to the work sequence of whole localization PG modes.Illustrate an example of above-mentioned work sequence referring to Fig. 7.
The signal PGM that " H " is issued by PMU105, is transferred to Status of Backups SS22 from standby mode SS3.In signal PGM During as " H ", data backup to fallback circuit 30 in each unit 10 of cell array 110.In whole localization PG modes In, power gating is carried out to cell array 110 during longer than cell array localization PG mode.Therefore, in Status of Backups Signal PGM under SS22 is longer than Status of Backups SS21 during becoming " H ".That is TB21 ratio TB11 long.
When the signal RST of " L " is entered, signal PSE1, PSE2 is set to become " L ", so that PMU105 makes storage device 100 As whole localization PG state SS14.Power switch 150 to 152 is in close state, the voltage reduction of V_VDD line, V_VDH line To VSS, the voltage drop of V_VDM line is as low as VSM.
The signal PSE1 that " H " is issued by PMU105, is transferred to recovery state SS26 from whole localization PG state SS14.Function Rate switch 150-152 become open state, so the voltage of V_VDD line, V_VDH line, V_VDM line rise to respectively VDD, VDH, VDM。
PMU105 executes the reset work of node Q, Qb before the signal PGM of sending " H ".By above-mentioned reset work, The voltage of node Q, Qb are set as voltage Vpr2.
Firstly, PMU105 makes opportunity of the signal PSE1 as " H " that signal BLFE, BLRE be made to become " H ".Column circuits 124 Reset work of whole bit lines to (BL, BLB) is carried out according to signal BLFE, the BLRE of " H ".Specifically, making pre-charge circuit 51 are in close state, and keep pre-charge circuit 52 in the open state.Transistor MN1, MN2 of local bitline MUX135, MP1, MP2 is in close state, so the supply voltage by column circuits 124 restores, whole bit lines are pre- to the voltage of (BL, BLB) It is charged to voltage Vpr2.
PMU105 makes signal NDRE become " H " in the signal RST of input " H ".Row circuit 123 is in the letter for being entered " H " All wordline WL are made to be in selection state when number NDRE.The voltage of node Q, Qb is precharged to voltage Vpr2 as a result,.In signal When NDRE becomes " L ", the reset work of node Q, Qb terminate.
Then, PMU105 exports the signal PGM of " H ".Then, signal PSE2 is made to become " H ".The node of fallback circuit 30 The data that SN1, SN2 are kept write back to node Q, Qb.Signal BLFE, BLRE that " L " is issued by PMU105, from Status of Backups SS26 is transferred to standby mode SS3.
Then, illustrate referring to Fig. 8 the work sequence that cell array PG mode is transferred to from standby mode an example and From cell array PG mode shifts to an example of the work sequence of whole localization PG modes.For example, that can predict to store When the quiescent time of device 100 is more than BET_pgca, the work sequence that cell array PG mode is transferred to from standby mode is executed.
The signal PGM that " H " is issued by PMU105, is transferred to Status of Backups SS21 from standby mode SS3.Status of Backups The work sequence of SS21 quotes the explanation of Fig. 6.
The time of storage unit PG state SS13 passes through setting time tk13, and PMU105 is executed to be turned from cell array PG mode Move on to the work sequence of whole localization PG modes.
The signal PGM that " H " is issued by PMU105, is transferred to Status of Backups SS23 from storage unit PG state SS13.It deposits Shape is on by backup/restoration driver 125 between node Q, Qb of storage unit 20 and node SN1, SN2 of fallback circuit 30 State.Then, PMU105 makes signal PSE2 become " H " and keep power switch 152 in the open state.Pass through the voltage of V_VDM line VDM is risen to from VDML, the bistable circuit 25 of unit 10 activates.At Status of Backups SS23, bistable circuit 25 by with The sense amplifier for acting on detecting the data of fallback circuit 30.By amplifying node SN1 and node by bistable circuit 25 Voltage difference between SN2, to node SN1, SN2 writing backup data again.
PMU105 makes signal PGM become " L ", and signal BLFE is then made to become " L ".When the signal RST of " L " is entered, PMU105 makes signal PSE1, PSE2 become " L ".The state of storage device 100 is transferred to whole localization PG state SS14.
Due to it is longer than cell array localization PG mode in whole localization PG modes during electricity is carried out to cell array 110 Source gate, so signal PGM becomes longer during " H " at Status of Backups SS23 compared with Status of Backups SS21.
(suspend mode)
Alternatively, it is also possible to be switched according to the quiescent time of storage device 100 using the multiple voltages for preparing suspend mode To the structure of the input voltage of V_VDM line.Fig. 9 indicates the example of this structure.Voltage VDML1, VDML2, VDML3 are suspend mode moulds The voltage of formula.VDM>VDML1>VDML2>VDML3.Voltage VDML3 is the size that the data of unit 10 do not disappear.
Power switch 154 to 156 is set, to control the input of voltage VDML1, VDML2, VDML3 to V_VDM line.Power Unlatching/closing of switch 154 to 156 is controlled by signal PSE4 to PSE6.Signal PSE4 to PSE6 is generated by PMU105.In suspend mode In mode, any one of power switch 154 to 156 becomes open state.
In the example of figure 9, three kinds of setting BET different dormant states.The lower BET of the voltage of substantially V_VDM line is more It is long.As described above, the difference of BET_blfl and BET_pgca is elongated in many cases.In such cases, there are multiple When dormant state, more appropriate low-power consumption mode can also be selected according to the various idle periods, it is possible to more efficiently reduce The power consumption of storage device 100.
0 example for illustrating sleep sequence referring to Fig.1.Here, be VDML1, VDML2 by the voltage of V_VDM line, The state of VDML3 is referred to as dormant state SS31, SS32, SS33.
The signal PSE2 of " L ", the signal PSE4 of " H " are issued by PMU105, is transferred to dormant state from standby mode SS3 SS31.The voltage drop of V_VDM line is as low as VDML1.Column are input into as the signal BLFE on the opportunity " H " of " H " in signal PSE4 Circuit 124 makes whole bit lines be in quick condition to (BL, BLB).
When the time of dormant state SS31 being more than setting time tk31, it is transferred to dormant state SS32.PMU105 makes letter Number PSE4 becomes " L ", and signal PSE5 is made to become " H ".Power switch 154 becomes closed state, and power switch 155 becomes opening state State.The voltage drop of V_VDM line is as low as VDML2.
When the time of dormant state SS32 being more than setting time tk32, it is transferred to dormant state SS33.PMU105 makes letter Number PSE5 becomes " L ", and signal PSE6 is made to become " H ".Power switch 155 becomes closed state, and power switch 156 becomes opening state State.The voltage drop of V_VDM line is as low as VDML3.
At dormant state SS33, when storage device 100 is accessed, the sequence for being restored to standby mode SS3 is executed. PMU105 issues the signal BLFE of the signal PSE2 of " H ", the signal PSE6 of " L ", " L ".Power switch 152 become open state and Power switch 156 becomes closed state, so the voltage of V_VDM line rises to VDM from VDML3.Dormant state SS33 when Between when being more than setting time tk33, execution unit array PG sequence.
Then, illustrate the other structures example of storage device.
" storage device 101 "
Storage device 101 shown in Figure 11 is the version of storage device 100.Storage device 101 and storage device 100 Similarly work.Storage device 101 is provided with power supply localization 163 and replaces power supply localization 162.Power supply localization 163 is provided with unit Array 111, V_VDM line, virtual powerline V_VSM (hereinafter referred to as V_VSM line).Storage device 101 is provided with power switch 157.Unlatching/closing of power switch 157 is controlled by signal PSE2.157 input voltage VSM of power switch is passed through to V_VSM line.
Cell array 111 includes multiple units 11.Figure 12 A shows the circuit structure example of unit 11.Unit 11 includes depositing Storage unit 20, fallback circuit 31.V_VSM line input voltage VSM is passed through to storage unit 20.
Fallback circuit 31 is made of a 1T1C type DRAM cell.Fallback circuit 31 include node SN3, transistor MO3 and Capacitor C3.Same as transistor MO1, MO2, transistor MO3 is the OS transistor for including back grid.The backgate of transistor MO3 Pole is electrically connected to VBG line.Transistor MO3 be also possible to do not include back grid OS transistor.
2B illustrates an example of the power gating sequence relative to power supply localization 163 referring to Fig.1.Here, main explanation With power gating sequence (Fig. 2 B) difference relative to power supply localization 162.
(usually work)
Before t1, storage device 101 is in usual working condition (write state or reading state).Storage device 101 Progress similarly usually works with single-port SRAM.Power switch 152,157 becomes open state, to V_VDM line input voltage VDM, to V_VSM line input voltage VSM.
(backup)
By being input into backup/restoration driver 125 in the signal PGM of t1 " H ", back-up job starts.Here, when Carving t1 node Q/Qb is " H "/" L ", and node SN3 is " L ".All wiring OGL become " H ", so the transistor of fallback circuit 31 MO3 is in the open state, and the voltage of node SN3 rises to VDM from VSM.By becoming " L " in t2 signal PGM, back-up job knot Beam.To the data of the node Q of node SN3 write-in t1.
(power gating)
Decline signal PSE2 in t2, PMU105 and power switch 152,157 is made to become closed state.In order to make bit line pair (BL, BLB) becomes quick condition, and PMU105 rises signal BLFE on the opportunity for declining signal PSE2.
(recovery)
Firstly, carrying out the reset work of node Q, Qb.Signal BLRE, NDRE is set to become " H " in t3, PMU105.Whole positions Line is pre-charged to voltage Vpr2 by column circuits 124 to (BL, BLB), and all wordline WL become selection state by row circuit 123.V_ VDM line, V_VSM line are precharged to voltage Vpr2, and the voltage of node Q, Qb are fixed as Vpr2.
So that signal NDRE is become " L " in t4, PMU105 and signal PGM is made to become " H ".Transistor MO3 becomes open state, The charge of capacitor C3 is allocated in node Q, node SN3, generates voltage difference between node Q and node Qb.
Then, so that bistable circuit 25 is used as sense amplifier, amplify the voltage difference of node Q and node Qb.In t5, make function Rate switch 152,157 is in the open state, starts again to power supply localization 163 input voltage VDM, VSM.Bistable circuit 25 As active state and the voltage difference of amplification node Q and node Qb.Finally, the voltage of node Q, SN3 become VDM, node Qb's Voltage becomes VSM.In other words, the state of node Q/Qb is restored to the state (" H "/" L ") of t1.PMU105 makes signal PGM in t6 As " L ", signal BLFE, BLRE is set to become " L " in t7.Resume work end in t7.
Fallback circuit 31 has the structure of a backup node Q.Pass through the envoy before making the voltage for being routed OGL become " H " The voltage of point Q, Qb become Vpr2, can be by the data of data recovery nodes Q, Qb of the node SN3 of fallback circuit 31.Therefore, In storage device 101, in the case where restoring state SS25, SS26, PMU105 sending " H " signal PGM before execute node Q, The reset work of Qb.
It can be by 10 Component units array 111 (3A referring to Fig.1) of unit.In above structure example, power supply localization 163 Power gating sequence is identical as above-mentioned power gating sequence (3B referring to Fig.1).The explanation of Figure 13 B quotes the explanation of Figure 12 B.
In cell array 111, capacitor C1, C2 of fallback circuit 30 can reduce.This is because in resuming work OGL will be made to be routed as " H " after the voltage pre-charge of node Q, Qb to Vpr2.By making to be routed OGL as " H ", even if electric The quantity of electric charge that container C1, C2 are kept is reduced, and the voltage difference of node Q and node Qb can also be set as can be by bistable electro The size that road 25 is detected.When capacitor C1, C2 reduce, it is possible to reduce the face of the unit 10 occurred by additional fallback circuit 30 Product expense.
Although above structure example is the example by fallback circuit applied to the storage unit of single-ended shape of the mouth as one speaks SRAM, The fallback circuit of present embodiment can be applied to multiterminal shape of the mouth as one speaks SRAM.The example of such circuit structure is illustrated below.
Unit 12 shown in figure 14 A includes storage unit 22, fallback circuit 30, and unit 13 shown in Figure 14 B includes storage Unit 22, fallback circuit 31.
Storage unit 22 is the storage unit of multi-port SRAM and including bistable circuit 25, transistor MT11 to MT14. Transistor MT11 to MT14 is transfering transistor.Storage unit 22 be electrically connected with wordline WL1, WL2, bit line to (BL1, BLB1), Bit line is to (BL2, BLB2), V_VDM line, V_VSM line (or VSM line).
The storage device of present embodiment is used as the storage device in various electronic components and electronic equipment.Originally it deposits Storage device multiple low-power consumption modes also shorter than power gating mode with its BET other than two kinds of power gating modes, by This can efficiently reduce the power consumption of the electronic component and electronic equipment that are equipped with this storage device.
The storage device of present embodiment is typically the storage device that can replace SRAM.For example, can be in micro-control unit (MCU), the storage device that present embodiment is assembled in the various processors such as FPGA, CPU, GPU replaces SRAM.In addition it is also possible to The storage device of present embodiment is assembled in wireless IC, display controller IC, source electrode driver IC, image decoder IC etc. In various IC.Hereinafter, an example as processor, illustrates to be equipped with processor core and height on a chip (die) The processor of fast buffer storage.
" processor "
Figure 15 is the block diagram for showing the configuration example of processor.Processor 300 shown in figure 15 includes PMU305, bus 306, cache memory 320, core cpu 330, backup/restoration driver 311 and power switch 390 to 394,398, 399。
Data and signal between core cpu 330 and cache memory 320 transport through the progress of bus 306.CPU Core 330 includes trigger 331 and combinational circuit 332.For example, trigger 331 includes in a register.By in trigger Fallback circuit is set in 331, is able to carry out the power gating of core cpu 330.
Here, the storage device 101 of Figure 11 is used as cache memory 320.Of course, it is possible to by storage device 100 As cache memory 320.
Cache memory 320 includes cell array 321 and peripheral circuit 322.Peripheral circuit 322 includes controller 324, backup/restoration driver 325, row circuit 326 and column circuits 327.Power switch 390 to 394 corresponds to storage device 101 Power switch 150 to 153,157.PMU305 has function same as the PMU105 of storage device 101 and generates signal PSE1 is to PSE3, PGM, BLFE, BLRE and NDRE.
PMU305 use generates clock signal GCLK from externally input clock signal clk 2.Clock signal GCLK is entered To cache memory 320 and core cpu 330.PMU305 generates signal PSE8, SCE, BK and RC.Signal PSE8, BK and RC It is that signal is controlled for the power gating of core cpu 330.
Signal PSE8 is the unlatching/closing power switch enable signal for controlling power switch 398,399.Power switch 398 control to the voltage VDD of core cpu 330 supply, and power switch 399 controls the voltage VDH to backup/restoration driver 311 Supply.
Signal SCE is scan enable signal, and is input to trigger 331.
Backup/restoration driver 311 is according to the fallback circuit of signal BK, RC control trigger 331.Signal BK is backup letter Number, signal RC is to restore signal.The signal BKH of raw pair signals BK, RC progress level shift of backup/restoration driver 311, RCH.Signal BKH, RCH are input into the fallback circuit of trigger 331.Voltage VDH is the high level voltage of signal BKH, RCH.
When PMU305 is generated according to the SLEEP signal issued from externally input interrupt signal INT2, core cpu 330 Clock signal GCLK and various control signals.For example, SLEEP signal, which may be used as becoming, is transferred to power gating for core cpu 330 The signal of the triggering of mode.
" trigger 331 "
Figure 16 shows the circuit structure example of trigger 331.Trigger 331 includes sweep trigger 335, fallback circuit 340。
V_VDD line and VSS line input voltage VDD, VSS in core cpu 330 is passed through to sweep trigger 335.Scanning touching Sending out device 335 includes node D1, Q1, SD, SE, RT, CK and clock buffer circuit 335A.
Node D1 is data input node, and node Q1 is data out node, and node SD is the input of scan test data Node.Node SE is the input node of signal SCE.Node CK is the input node of clock signal GCLK.Clock signal GCLK quilt It is input to clock buffer circuit 335A.The analog switch of sweep trigger 335 is electrically connected in clock buffer circuit Node CK1, CKB1 of 335A.Node R T is the input node of reset signal (resetsignal).
The circuit structure of sweep trigger 335 is not limited to circuit structure shown in Figure 16.The electricity in standard can be used The sweep trigger prepared in the library of road.
<fallback circuit 340>
Fallback circuit 340 includes node SD_IN, SN11, transistor MO11 to MO13 and capacitor C11.
Node SD_IN is the input node of scan test data, and is electrically connected to the node of other sweep triggers 335 Q1.Node SN11 is the holding node of fallback circuit 340.Capacitor C11 is electrically connected to VSS line and node SN11.
On state between transistor MO11 control node Q1 and node SN11.Transistor MO12 control node SN11 with On state between node SD.On state between transistor MO13 control node SD_IN and node SD.Transistor Unlatching/closing of MO11, MO13 are controlled by signal BKH, and unlatching/closing of transistor MO12 is controlled by signal RCH.
Same as transistor MO1, transistor MO11 to MO13 is by including that the OS transistor of back grid is constituted.Transistor MO11 Back grid to MO13 is electrically connected to the VBG line in core cpu 330.Preferably, at least transistor MO11, MO12 is OS brilliant Body pipe.Due to the minimum feature of the off-state current of OS transistor, the voltage of node SN11 can be inhibited to decline.Because OS is brilliant Body pipe hardly power consumption when keeping data, so fallback circuit 340 has can keep the non-volatile of data for a long time.Cause This, during core cpu 330 is in power gating state, fallback circuit 340 can keep data.
" low-power consumption mode of core cpu 330 "
As the low-power consumption mode of core cpu 330, clock gating mode, power gating mode can be set.PMU305 root It is believed that the low-power consumption mode of number INT2, SLEEP signal selection core cpu 330.By the life for making PMU305 stop signal GCLK At, can make core cpu 330 state become Clock gating state.
It is carried out when core cpu 330 is transferred to power gating state from usual working condition by the data of trigger 331 Backup to the work of fallback circuit 340.By core cpu 330 from the when progress that is restored to usual working condition of power gating state The data of fallback circuit 340 are written to resuming work for trigger 331 again.In the following, 7 illustrating core cpu 330 referring to Fig.1 Power gating sequence an example.
(usually work)
Before t1, trigger 331 is usually worked.PMU305 exports signal SCE, BK and the RC of " L ".Here, T1, the node SN11 of fallback circuit 340 are " L ".Since node SE is " L ", the data of 335 storage node D1 of sweep trigger.
(backup)
Stop clock signal GCLK in t1, PMU305, signal BK is made to become " H ".Transistor MO11 becomes open state, sweeps The data for retouching the node Q1 of trigger 335 are written to the node SN11 of fallback circuit 340.If the node Q1 of sweep trigger 335 For " L ", node SN11 then keeps " L ", if node Q1 is " H ", node SN11 becomes " H ".
PMU305 makes signal BK become " L " in t2, so that signal PSE8 is become " L in t3.In t3, the state of core cpu 330 It is transferred to power gating state.Can so that signal BK decline opportunity make signal PSE8 decline.
(power gating)
When signal PSE8 becomes " L ", power switch 398,399 becomes closed state.Because under the voltage of V_VDD line The data of drop, node Q1 disappear.Node SN11 keeps the data of the node Q1 of t1.
(recovery)
So that signal PSE8 is become " H " in t4, PMU305, therefore is transferred to recovery state from power gating state.Start V_ The charging of vdd line.In the state that the voltage of V_VDD is VDD (moment t5), PMU305 makes signal RC, SCE become " H ".
Because signal RCH becomes " H ", transistor MO12 becomes open state, and the charge of capacitor C11 is allocated in section Point SN11 and node SD.If node SN11 is " H ", the voltage of node SD rises.Because node SE is " H ", the number of node SD According to the input side latch cicuit for being written to sweep trigger 335.In t6, Xiang Jiedian CK input clock signal GCLK, input side The data of latch cicuit are written to node Q1.That is, the data of node SN11 are written to node Q1.
So that signal SCE, RC is become " L " in t7, PMU305, thus terminates recovery state.
Due to being both provided with fallback circuit in the processor core and storage device of the processor of present embodiment, so can Efficiently to reduce the power consumption of processor entirety.
(embodiment 2)
In the present embodiment, as an example of semiconductor device, to IC chip, electronic component and electronic equipment etc. It is illustrated.
" the manufacturing method example of electronic component "
Electronic component is also referred to as semiconductor packages or IC encapsulation etc..
Electronic component is completed by preceding process and assembling procedure (after process).In preceding process, in semiconductor wafer (example Such as, silicon wafer) on form semiconductor device etc. according to one method of the present invention.Hereinafter, process after 8A illustrates referring to Fig.1.
In rear process, firstly, carried out to the back side (not forming the face of semiconductor device etc.) of semiconductor wafer " back grinding procedure " (the step SP71) of grinding.Semiconductor wafer is thinned by grinding, realizes the miniaturization of electronic component.? After step SP71, " cutting action " (step SP72) that semiconductor wafer is divided into multiple chips is carried out.In cutting action, By being cut into chip from semiconductor wafer along defiber cutting semiconductor chip.
Be picked up separation after chip and be engaged on lead frame " chip engage (die bonding) work Sequence " (step SP73).The method that the engagement of chip and lead frame in chip bonding process can choose suitable product, example Such as, the method for engaging or being engaged using adhesive tape is carried out using resin.Alternatively, it is also possible to which chip is engaged in insert (interposer) on substrate, without being engaged in lead frame.
Then, it carries out with the electrode on chip " drawing the lead of lead frame by what metal fine (wire) was electrically connected Line bonding (wire bonding) process " (step SP74).Silver wire or gold thread etc. can be used as metal fine.Wire bonding Ball bonding (ball bonding) can be used for example or Wedge Bond (wedge bonding) carries out.To the core after wire bonding Piece 7110 carries out " molding (molding) process " (the step SP75) by sealings such as epoxy resin.
Then, " lead electroplating processes " (step SP76) that electroplating processes are carried out to the lead of lead frame is carried out.It carries out " molding procedure " (the step SP77) of cutting and processing and forming is carried out to lead.It carries out implementing lettering processing to package surface (marking) " lettering process " (step SP78).Then, pass through the superiority and inferiority for face shaping of testing or having for job failure Electronic component is completed without equal inspection process (step SP79).
Figure 18 B is the stereoscopic schematic diagram for the electronic component completed.Electronic component is according to terminal removing direction or the shape of terminal Shape has multiple specifications and title.In Figure 18 B, as an example of electronic component, QFP (Quad Flat is shown Package: four side pin flat packages).
Electronic component 7000 shown in Figure 18 B includes lead 7001 and chip 7110.Basis is provided in chip 7110 The storage device of embodiment 1 or the processor for being equipped with this storage device.
Electronic component 7000 may include multiple chips 7110.Electronic component 7000 is for example installed on printed circuit board 7002.By combining multiple such electronic components 7000 and it being made to be electrically connected to each other on printed circuit board 7002, peace is completed Substrate (installation substrate 7004) equipped with electronic component.Substrate 7004 is installed for electronic equipment etc..
Since electronic component 7000 is equipped with the storage device of low-power consumption, so by the way that electronic component 7000 is assembled in electricity Sub- equipment can reduce the power consumption of electronic equipment.Then, illustrate the electronic equipment for having above-mentioned electronic component.
Information terminal 2010 shown in Figure 19 A further includes operation other than the display unit 2012 being mounted in shell 2011 Button 2013, external connection port 2014, loudspeaker 2015, microphone 2016.Here, the display area of display unit 2012 is curved Bent.Information terminal 2010 is to be used as plate information terminal or intelligent hand with battery-driven portable data assistance Machine.Information terminal 2010 has the function of phone, Email, notebook, online, music etc..By being touched with finger etc. Display unit 2012 can input information.By that with the touch display parts such as finger 2012, can be made a phone call, be inputted text, aobvious Show the various operations such as the panel switch operating in portion 2012.Information terminal can also be carried out by inputting sound from microphone 2016 2010 operation.It is cut by the panel of the operation of button 2013, unlatching/closing work, display unit 2012 that power supply can be carried out The various operations such as change jobs.
Notebook type PC (personal computer) 2050 shown in Figure 19 B includes shell 2051, display unit 2052, keyboard 2053, indicator device 2054.It, can be with this type of Operational Note PC2050 by the touch operation of display unit 2052.
Video camera 2070 shown in Figure 19 C includes shell 2071, display unit 2072, shell 2073, operation key 2074, lens 2075, interconnecting piece 2076.Display unit 2072 is arranged in shell 2071, and operation key 2074 and lens 2075 are arranged in shell 2073 In.Moreover, shell 2071 and shell 2073 are connected by interconnecting piece 2076, shell 2071 and shell can change by interconnecting piece 2076 Angle between 2073.Display can be switched using according to the angle between the shell 2071 at interconnecting piece 2076 and shell 2073 The structure of the image in portion 2072.By the touch operation of display unit 2072, the operation of the beginning and stopping that can recording a video is put The various operations such as the adjustment of multiplying power, change of image pickup scope greatly.
Portable game machine 2110 shown in Figure 19 D includes shell 2111, display unit 2112, loudspeaker 2113, LED light 2114, operation key button 2115, connection terminal 2116, camera 2117, microphone 2118, recording media reading section 2119.
Electric refrigeration freezer 2150 shown in Figure 19 E includes shell 2151, refrigerating-chamber door 2152 and refrigerating chamber door 2153 etc..
Automobile 2170 shown in Figure 19 F includes car body 2171, wheel 2172, instrument board 2173 and lamp 2174 etc..
(embodiment 3)
In the present embodiment, illustrate the semiconductor device being made of Si transistor and OS transistor.Here, with embodiment party Illustrate the structure of this semiconductor device for the storage device 100 of formula 1.
" laminated construction of storage device 100 "
Illustrate the structure of storage device 100 referring to Figure 20.Typically, transistor MT1, MO1, capacitor is shown in FIG. 20 C1.Storage device 100 includes the lamination of monocrystalline silicon piece 5500, layer LX1 to LX9.Layer LX1 to layer LX9 be provided with wiring, electrode, Plug etc..Note that Figure 20 is the sectional view for illustrating the laminated construction example of storage device 100, rather than by specify Cutting line cutting storage device 100 obtained from sectional view.
In layer LX1, it is provided with the Si transistor that transistor MT1 etc. constitutes storage device 100.The channel shape of Si transistor It is arranged in monocrystalline silicon piece 5500 at region.
Layer LX7 is provided with the OS transistor such as transistor MO1, MO2.The back-gate electrode of OS transistor is arranged in layer LX6.? This, the structure of OS transistor and aftermentioned OS transistor 5004 (referring to Figure 22 B) are same.Layer LX9 includes capacitor C1.It can incite somebody to action The lower layer of layer LX7 is arranged in capacitor C1.
Then, the configuration example of OS transistor is illustrated referring to Figure 21 A to Figure 22 B.OS is shown on the left of Figure 21 A to Figure 22 B The cross section structure of the orientation of transistor, right side show the cross section structure of the channel width dimension of OS transistor.
" configuration example 1 of OS transistor "
OS transistor 5001 shown in Figure 21 A is formed on insulating surface.Here, OS transistor 5001 is formed in insulating layer On 5021.
OS transistor 5001 is covered by insulating layer 5028 and 5029.OS transistor 5001 include insulating layer 5022 to 5027, 5030 to 5032, metal oxide layer 5011 to 5013 and conductive layer 5050 to 5054.
Insulating layer, metal oxide layer, conductive layer in attached drawing etc. can be single layer or lamination.When manufacturing these layer, Sputtering method, molecular beam epitaxy (MBE method), pulse laser ablation method (PLA method), chemical vapour deposition technique (CVD can be used Method), the various film build methods such as atomic layer deposition method (ALD method).CVD method includes plasma CVD method, thermal cvd and organic gold Belong to CVD method etc..
Metal oxide layer 5011 to 5013 is collectively referred to as oxide skin(coating) 5010.As shown in figure 21, metal oxide layer 5010 include the part for being sequentially laminated with metal oxide layer 5011, metal oxide layer 5012 and metal oxide layer 5013. When OS transistor 5001 is in the open state, channel is mainly formed in the metal oxide layer 5012 of oxide skin(coating) 5010.
The gate electrode of OS transistor 5001 is made of conductive layer 5050, and a pair of electrodes as source electrode or drain electrode is by leading Electric layer 5051,5052 is constituted.Conductive layer 5050 to 5052 is respectively by the covering of insulating layer 5030 to 5032 as barrier layer.Backgate Electrode is made of the lamination of conductive layer 5053 and conductive layer 5054.OS transistor 5001 can not also include back-gate electrode.It is aftermentioned OS transistor 5002 be also same.
The gate insulating layer of grid (normal-gate) side is made of insulating layer 5027, the gate insulating layer of back grid side by The lamination of insulating layer 5024 to 5026 is constituted.Insulating layer 5028 is interlayer insulating film.Insulating layer 5029 is barrier layer.
The covering of metal oxide layer 5013 is made of metal oxide layer 5011,5012 and conductive layer 5051,5052 Laminated body.Insulating layer 5027 covers metal oxide layer 5013.Conductive layer 5051,5052 has across metal oxide layer 5013 And the region that insulating layer 5027 is Chong Die with conductive layer 5050.
As the conductive material for conductive layer 5050 to 5054, following material can be used: doped with impurity such as phosphorus The polysilicon of element is the semiconductor of representative；The silicides such as nickel silicide；The metals such as molybdenum, titanium, tantalum, tungsten, aluminium, copper, chromium, neodymium, scandium Or using above-mentioned metal as metal nitride (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride) of ingredient etc..Alternatively, it is also possible to use Indium tin oxide, the indium oxide comprising tungsten oxide, the indium-zinc oxide comprising tungsten oxide, the indium oxide comprising titanium oxide, The conductive materials such as indium tin oxide, indium-zinc oxide comprising titanium oxide, the indium tin oxide for adding silica.
For example, conductive layer 5050 is the single layer of tantalum nitride or tantalum.Alternatively, there are double-layer structure and three layers in conductive layer 5050 It, can be using following combination: (aluminium, titanium) in the case where structure；(titanium nitride, titanium)；(titanium nitride, tungsten)；(tantalum nitride, tungsten)；(nitrogen Change tungsten, tungsten)；(titanium, aluminium, titanium)；(titanium nitride, aluminium, titanium)；(titanium nitride, aluminium, titanium nitride).The electric conductor wherein recorded above is set It sets in 5027 side of insulating layer.
5052 having the same layers of structure of conductive layer 5051 and conductive layer.For example, when conductive layer 5051 is single layer, it can be with Using the metal of aluminium, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum or tungsten etc. or with these metals alloy as main component.? It, can be using following combination: (titanium, aluminium) in the case that conductive layer 5051 has double-layer structure and three-decker；(tungsten, aluminium)； (tungsten, copper)；(copper-magnesium-aluminum alloy, copper)；(titanium, copper)；(titanium or titanium nitride, aluminium or copper, titanium or titanium nitride)；(molybdenum or molybdenum nitride, Aluminium or copper, molybdenum or molybdenum nitride).The electric conductor wherein recorded above is arranged in 5027 side of insulating layer.
For example, it is preferable that conductive layer 5053 is the conductive layer (for example, tantalum nitride layer) for having block to hydrogen, it is conductive The conductive layer (for example, tungsten layer) higher than conductive layer 5053 for its conductivity of layer 5054.By using the structure, 5053 He of conductive layer The lamination of conductive layer 5054 has the function of the function of being routed and hydrogen is inhibited to be diffused into oxide skin(coating) 5010.
As the insulating materials for insulating layer 5021 to 5032, there is a following material: aluminium nitride, aluminium oxide, aluminum oxynitride, Aluminium oxynitride, magnesia, silicon nitride, silica, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Lanthana, neodymia, hafnium oxide, tantalum oxide, alumina silicate etc..Insulating layer 5021 to 5032 is by the single layer including these insulating materials Or lamination is constituted.The layer for constituting insulating layer 5021 to 5032 may include a variety of insulating materials.
In this specification etc, oxynitride refers to that oxygen content is greater than the compound of nitrogen content, and nitrogen oxides refers to that nitrogen contains Amount is greater than the compound of oxygen content.
In OS transistor 5001, oxide skin(coating) 5010 is preferably had the insulating layer of block (hereinafter referred to as to oxygen and hydrogen For barrier layer) it surrounds.By using the structure, oxygen can be inhibited to release from oxide skin(coating) 5010 and hydrogen can be inhibited to invade Oxide skin(coating) 5010, it is possible thereby to improve the reliability and electrical characteristics of OS transistor 5001.
For example, insulating layer 5029 is used as barrier layer, at least one of insulating layer 5021,5022,5024 is used as hindering Barrier.Aluminium oxide, aluminium oxynitride, gallium oxide, oxynitriding gallium, yttrium oxide, oxynitriding yttrium, oxidation can be used in barrier layer The material of hafnium, oxynitriding hafnium, silicon nitride etc. is formed.Blocking can also be set between oxide skin(coating) 5010 and conductive layer 5050 Layer.Alternatively, also can be set has the metal oxide layer of block as metal oxide layer 5013 oxygen and hydrogen.
Insulating layer 5030 is preferably the barrier layer for preventing the oxidation of conductive layer 5050.Stop when insulating layer 5030 has oxygen Property when, can inhibit the oxygen from disengagings such as insulating layers 5028 make conductive layer 5050 aoxidize.For example, can make as insulating layer 5030 With metal oxides such as aluminium oxide.
The configuration example of insulating layer 5021 to 5032 is shown.In this example embodiment, insulating layer 5021,5022,5025,5029, 5030 to 5032 are all used as barrier layer.Insulating layer 5026 to 5028 is the oxide skin(coating) comprising excess oxygen.Insulating layer 5021 is Silicon nitride, insulating layer 5022 are aluminium oxide, and insulating layer 5023 is silicon oxynitride.Back grid side gate insulating layer (5024 to It 5026) is the lamination of silica, aluminium oxide and silica.The gate insulating layer (5027) of normal-gate side is silicon oxynitride.Layer Between insulating layer (5028) be silica.Insulating layer 5029,5030 to 5032 is aluminium oxide.
Figure 21 shows the example that oxide skin(coating) 5010 is three-decker, but not limited to this.Oxide skin(coating) 5010 is for example It can be the double-layer structure of no metal oxide layer 5011 or metal oxide layer 5013, it can also be by metal oxide layer Any one layer in 5011 to 5012 is constituted.In addition, oxide skin(coating) 5010 can also be by four layers or more of metal oxide layer structure At.
" configuration example 2 of OS transistor "
OS transistor 5002 shown in Figure 21 B is the version of OS transistor 5001.In OS transistor 5002, by gold The top surface and side for belonging to the lamination that oxide skin(coating) 5011 and 5012 is constituted are by by 5027 structure of metal oxide layer 5013 and insulating layer At lamination covering.Therefore, in OS transistor 5002, insulating layer 5031,5032 not have to be set.
" configuration example 3 of OS transistor "
OS transistor 5003 shown in Figure 22 A is the version of OS transistor 5001.It is in place of the main difference of the two The structure of gate electrode.
Metal oxide layer 5013, insulating layer 5027 and conductive layer are provided in the opening being formed in insulating layer 5028 5050.That is, by forming gate electrode in a self-aligned manner using the opening of insulating layer 5028.Therefore, in OS crystal In pipe 5003, gate electrode (5050) does not have across gate insulating layer (5027) and source electrode and drain electrode (5051,5052) weight Folded region.Thus, it is possible to the parasitic capacitance between gate-to-source and the parasitic capacitance between gate-to-drain are reduced, so as to To improve frequency characteristic.Further, since can use the width of the opening control grid electrode of insulating layer 5028, so can be easy Ground manufactures the short OS transistor of channel length.
" configuration example 4 of OS transistor "
The knot that gate electrode, oxide skin(coating) are a difference in that with OS transistor 5001 of OS transistor 5004 shown in Figure 22 B Structure.
The gate electrode (5050) of OS transistor 5004 is covered by insulating layer 5033,5034.OS transistor 5004 includes by gold Belong to the oxide skin(coating) 5009 that oxide skin(coating) 5011 and 5012 is constituted.Low resistance region is provided in metal oxide layer 5011 5011a, 5011b are provided with low resistance region 5012a, 5012b in metal oxide layer 5012, and replace conductive layer 5051, 5052.By selectively adding impurity element (for example, hydrogen, nitrogen) to oxide skin(coating) 5009, low resistance region can be formed 5011a, 5011b, 5012a and 5012b.
When adding impurity element to metal oxide layer, oxygen defect is formed in the region of addition impurity element, impurity Element invades oxygen defect and carrier density increases, and thus Adding Area is by low resistance.
The channel formation region of OS transistor is preferably CAC-OS (cloud-aligned composite metal oxide semiconductor)。
Function CAC-OS conductive in a part of material, with insulating properties in another part of material Function, the entirety as material have the function of semiconductor.In addition, CAC-OS or CAC-metal oxide is used for crystal In the case where the active layer of pipe, the function of electric conductivity is the function that the electronics (or hole) for making to be used as carrier flows through, insulation The function of property is the function of flowing through the electronics for being used as carrier.Pass through the mutual of the function of the function and insulating properties of electric conductivity Benefit effect, can make CAC-OS have the function of switching function (unlatching/closing).By separating each function in CAC-OS, Each function can be improved to the maximum extent.
CAC-OS includes conductive region and resistive regions.Conductive region has the function of above-mentioned electric conductivity, insulation Property region has the function of above-mentioned insulating properties.In addition, in the material, conductive region and resistive regions are sometimes with nanoparticle Grade separation.In addition, conductive region and resistive regions are unevenly distributed in the material sometimes.In addition, observing it sometimes Edge blurry and with cloud form connect conductive region.
In CAC-OS, conductive region and resistive regions are sometimes with 0.5nm or more and 10nm size below, preferably With 0.5nm or more and 3nm size dispersion below in the material.
In addition, CAC-OS is made of the ingredient with different band gap.For example, CAC-OS is by having due to resistive regions Wide gap ingredient and ingredient with the narrow gap due to conductive region constitute.In this configuration, when flowing through carrier When, carrier mainly flows through in the ingredient with narrow gap.Make in addition, the ingredient with narrow gap is complementary with having the wide ingredient of gap With carrier flows through in the ingredient with wide gap in linkage with the ingredient with narrow gap.Therefore, by using above-mentioned CAC-OS In the channel formation region of transistor, the OS transistor with high current driving force and high field-effect mobility may be implemented.
In addition, metal-oxide semiconductor (MOS) according to its crystallinity be divided into mono-crystalline metal oxide semiconductor and it is above-mentioned other than Non-monocrystal metal oxide semiconductor.As non-monocrystal metal oxide semiconductor, there is CAAC-OS (c-axis-aligned Crystalline metal oxide semiconductor), polycrystalline metal oxide semiconductor, nc-OS (nanocrystalline metal oxide semiconductor) and a-like OS (amorphous-like metal Oxide semiconductor) etc..
In addition, the channel formation region of OS transistor preferably includes the metal oxygen that CAAC-OS, nc-OS etc. have crystallization unit Compound.
CAAC-OS has c-axis orientation, and multiple nanocrystalline link on the direction of the face a-b and crystalline texture have distortion. Distortion refer in the region of multiple nanocrystalline connections the consistent region of lattice arrangement and the consistent region of other lattice arrangements it Between lattice arrangement direction change part.
Nanocrystalline is substantially hexagon, but is not limited to regular hexagon, is sometimes non-regular hexagon.In addition, nanometer It is brilliant that there are in distortion the lattice arrangements such as pentagon or hexagon sometimes.In addition, not observing near the distortion of CAAC-OS bright True crystal boundary (grain boundary).That is, the distortion of lattice arrangement inhibits the formation of crystal boundary.This may be due to CAAC-OS is tolerable because of the following resulting distortion of original: the low-density of the arrangement of the oxygen atom on the direction of the face a-b or because of gold Belong to element to be substituted and interatomic bonding distance is made to generate variation etc..
CAAC-OS, which has to have, is laminated with the layer (hereinafter referred to as In layers) comprising indium and oxygen and the layer comprising element M, zinc and oxygen The tendency of the layered crystal structure (also referred to as layer structure) of (hereinafter referred to as (M, Zn) layer).In addition, indium and element M each other can be with Replace, in the case where replacing the element M in (M Zn) layer with indium, which can also be expressed as to (In, M, Zn) layer.In addition, In the case where replacing the indium in In layers with element M, which can also be expressed as to (In, M) layer.
In nc-OS, small region (such as 1nm or more and the region below 10nm, especially 1nm or more and 3nm with Under region) in atomic arrangement have periodically.In addition, nc-OS it is different it is nanocrystalline between do not observe crystalline orientation Regularity.Therefore, orientation is not observed in film entirety.So sometimes nc-OS in certain analysis methods with a-like OS or amorphous oxide semiconductor do not have difference.
A-like OS is the metal oxide with the structure between nc-OS and amorphous metal oxide semiconductor Semiconductor.A-like OS includes cavity or density regions.The crystallinity ratio nc-OS and CAAC-OS of a-like OS is low.
In this specification etc, CAC indicates the function or material of metal-oxide semiconductor (MOS), and CAAC indicates metal oxide The crystalline texture of semiconductor.
[symbol description]
10,11,12,13: unit, 20,22: storage unit, 25: bistable circuit, 30,31: fallback circuit,
51,52,53: pre-charge circuit, 55: sense amplifier, 55a: latch cicuit, 56:RS latch cicuit, 57,58, 59: inverter circuit,
100,101: storage device,
105:PMU,
110,111: cell array,
120: peripheral circuit, 122: controller, 123: row circuit, 124: column circuits, 125: backup/restoration driver,
131: line decoder, 132: word line driver, 133: column decoder, 134: pre-charge circuit, 135: local bitline MUX, 135r, 135w:MUX, 136: sense amplifier, 137: write driver, 138: output driver,
150,151,152,153,154,155,156,157: power switch, 160,161,162,163: power supply localization,
300: processor, 305:PMU, 306: bus, 311: backup/restoration driver, 320: cache memory, 321: cell array, 322: peripheral circuit, 324: controller, 325: backup/restoration driver, 326: row circuit, 327: column electricity Road, 330:CPU core, 331: trigger, 332: cache memory,
335: sweep trigger, 335A: clock buffer circuit, 340: fallback circuit,
390,391,392,393,394,398,399: power switch,
2010: information terminal, 2011: shell, 2012: display unit, 2013: operation button, 2014: external connection port, 2015: loudspeaker, 2016: microphone, 2051: shell, 2052: display unit, 2053: keyboard, 2054: indicator device, 2070: taking the photograph Camera, 2071: shell, 2072: display unit,
2073: shell, 2074: operation key, 2075: lens, 2076: interconnecting piece, 2110: portable game machine, 2111: outer Shell, 2112: display unit, 2113: loudspeaker, 2114:LED lamp, 2115: operation button, 2116: connection terminal, 2117: photograph Machine, 2118: microphone, 2119: recording media reading section, 2150: electric refrigeration freezer, 2151: shell, 2152: refrigerating-chamber door, 2153: refrigerating chamber door, 2170: automobile, 2171: car body, 2172: wheel, 2173: instrument board, 2174: lamp,
5001,5002,5003,5004:OS transistor,
5009,5010: oxide skin(coating),
5011,5012,5013: metal oxide layer,
5021、5022、5023、5024、5025、5026、5027、5028、5029、5030、5031、5032、5033、 5034: insulating layer,
5050,5051,5052,5053,5054: conductive layer,
5500: monocrystalline silicon piece,
7000: electronic component, 7001: lead, 7002: printed circuit board, 7004: installation substrate,
BL, BL1, BL2, BLB, BLB1, BLB2: bit line,
LRBL, LRBLB, LWBL, LWBLB: local bitline,
WL, WL1, WL2: wordline,
OGL: wiring,
V_VDD, V_VDH, V_VDM, V_VSM: virtual voltage line,
Q, Qb, QS, QSb, SN1, SN2, SN3, SN11, D1, Q1, SD, SD_IN, SE, CK, CK1, CKB1, RT: node,
MN1、MN2、MN3、MP1、MP2、MP3、MP4、MO1、MO2、MO3、MO11、MO12、MO13、MT1、MT2、MT11、 MT12, MT13, MT14: transistor,
C1, C2, C3, C11: capacitor,
LX1, LX2, LX3, LX4, LX5, LX6, LX7, LX8, LX9: layer

Claims (25)

1. a kind of semiconductor device, comprising:
The peripheral circuit of first power supply localization is set；
The cell array of second source localization is set；And
For carry out the first power supply localization and the second source localization power management electric power controller,
Wherein, the cell array includes storage unit, fallback circuit, wordline and the position being made of the first bit line and the second bit line Line pair,
The storage unit include the bistable circuit with first node and second node, for control the first node and First transfering transistor of the on state between first bit line and for controlling the second node and the second Second transfering transistor of the on state between line,
The grid of first transfering transistor and second transfering transistor is electrically connected with the wordline,
The fallback circuit, the wordline and the bit line pair are electrically connected with the peripheral circuit,
By the control of the electric power controller, the peripheral circuit is carried out between the storage unit and the fallback circuit The write-in and reading of data,
The first to the 7th state is at least set as working condition,
The work for the cell array being written data is carried out in said first condition,
The work that data are read from the cell array is carried out in said second condition,
The third state is standby mode,
Under the 4th state, the bit line to be in quick condition,
Under first to fourth state, by the control of the electric power controller, the first power supply localization is supplied First voltage, and second voltage is supplied in the second source localization,
Under the 5th state, the bit line is to quick condition is in, by the control of the electric power controller, to described First power supply localization supplies the first voltage, and is lower than the third of the second voltage to second source localization supply Voltage,
Under the 6th state, the bit line is to quick condition is in, by the control of the electric power controller, described the The first voltage is supplied in one power supply localization, and carries out power gating to the second source localization,
Also, under the 7th state, by the control of the electric power controller, to the first power supply localization and described Second source localization carries out power gating.
2. semiconductor device according to claim 1,
Wherein under the 4th to the 6th state, by the control of the electric power controller, the peripheral circuit makes described Bit line is in quick condition.
3. semiconductor device according to claim 1,
Wherein by the control of the electric power controller,
And it executes from the 4th state and is transferred to the work sequence of the 5th state, be transferred to institute from the 5th state It states the work sequence of the 6th state and is transferred to the work sequence of the 7th state from the 6th state.
4. semiconductor device according to claim 1,
It is wherein controlled by the electric power controller, execution is transferred in the 4th to the 7th state from the third state Any one working condition work sequence and the work sequence of the third state is transferred to from the state that displaced.
5. semiconductor device according to claim 1,
Wherein being transferred to the work sequence of the 6th state or the 7th state from other states includes by the unit battle array The data of column are written to the work of the fallback circuit.
6. semiconductor device according to claim 1,
Wherein including from the work sequence that the 6th state or the 7th state are transferred to the third state will be described standby The data of part circuit are written to the work of the storage unit.
7. semiconductor device according to claim 1,
Wherein under described first to the third state, the peripheral circuit is to the bit line to inputting the first pre-charge voltage.
8. semiconductor device according to claim 1,
It is wherein transferred in the work sequence of the third state from the 7th state, the peripheral circuit is to described first Node and the second node input the second pre-charge voltage.
9. semiconductor device according to claim 1,
Wherein from the work sequence that other states are transferred to the 6th state or the 7th state, the peripheral circuit Carry out the precharge work that second pre-charge voltage is inputted to described first and the second node.
10. semiconductor device according to claim 1,
Wherein the fallback circuit only backs up the data of the first node.
11. it is a kind of including electric power controller, first to third power switch, the first power supply localization and second source localization half Conductor device,
Wherein, the electric power management circuit generates the first to the 7th control signal,
Described first to third control signal control respectively described first to third power switch opening and closing,
First power switch controls the supply of the first voltage to the first power supply localization,
Second power switch and the third power switch control respectively to the second source localization second voltage and The supply of tertiary voltage, the tertiary voltage are lower than the second voltage,
The first power supply localization is provided with row circuit, column circuits, controller and driver,
The second source localization is provided with cell array,
The cell array is provided with storage unit, the first fallback circuit, wordline and is made of the first bit line and the second bit line Bit line pair,
First fallback circuit include: the first holding node, second holding node, with it is described first keep node be electrically connected First capacitor device, the second capacitor being electrically connected with the second holding node keep node and institute for controlling described first It states the first transistor of the on state between the first node of storage unit and keeps node and institute for controlling described second The second transistor of the on state between the second node of storage unit is stated,
The channel formation region of the first transistor and the second transistor includes metal oxide,
The row circuit is electrically connected with the wordline,
The column circuits include by two be partially written first partial bit line that bit line is constituted to, by two local readout bit line structures At the second local bitline to, by the bit line to be pre-charged to the first pre-charge voltage the first pre-charge circuit, will be described Bit line to be pre-charged to the second pre-charge voltage the second pre-charge circuit, to the first partial bit line to write-in data write Enter driver, the sense amplifier of the data of detection second local bitline pair, the control bit line to the first game The first switch circuit and the control bit line of on state between bit line pair are between second local bitline pair The second switch circuit of on state,
The driver controls the opening and closing of first and second transistor according to the 4th control signal,
It is carried out by the controller or according to the control of row circuit described in the 5th control signal deciding by the power supply pipe Circuit is managed to carry out,
The column circuits control the work of first and second pre-charge circuit according to the 6th control signal,
Also, the column circuits control the opening and closing of first and second switching circuit according to the 7th control signal Work.
12. semiconductor device according to claim 11,
Wherein the cell array includes that the second fallback circuit replaces first fallback circuit,
Second fallback circuit is only written the data of the first node,
Second fallback circuit includes the third capacitor that third keeps node and keeps node to be electrically connected with the third And third transistor,
The third transistor controls the conducting shape between the third holding node and the first node of the storage unit State,
The channel formation region of the third transistor includes metal oxide,
And the driver controls the opening and closing of the third transistor according to the 4th control signal.
13. semiconductor device according to claim 11, comprising:
Processor core；
For transmitting the bus of data between the memory cell array and the processor core；And
For controlling the 4th power switch for supplying the processor core the 4th voltage,
Wherein the electric power controller generates the 8th control signal of the opening and closing of the 4th power switch.
14. a kind of electronic component, comprising:
Chip；And
Lead,
Wherein, the lead is electrically connected with the chip,
Also, semiconductor device described in claim 1 or 11 is arranged in the chip.
15. a kind of electronic component, comprising:
Electronic component described in claim 14；And
At least one of display unit, touch sensor, microphone, loudspeaker, operation key and shell.
16. a kind of semiconductor including carrying out the electric power controller of the power management of the first power supply localization and second source localization The working method of device,
Wherein, the first power supply localization is provided with peripheral circuit,
The second source localization is provided with cell array,
The cell array includes storage unit, the fallback circuit being electrically connected with the storage unit and peripheral circuit electricity The wordline of connection and the bit line pair for being constituted and being electrically connected with the peripheral circuit by the first bit line and the second bit line,
The storage unit includes the bistable circuit for including first node and second node, the control first node and described Leading between the first transfering transistor and the control second node and second bit line of the on state between the first bit line Second transfering transistor of logical state,
The grid of first transfering transistor and second transfering transistor is electrically connected with the wordline,
Under first to fourth state, by the control of the electric power controller to the first power supply localization and described second Power supply localization supplies first voltage, second voltage respectively,
In said first condition, the storage unit is write data by the peripheral circuit,
In said second condition, data are read from the storage unit by the peripheral circuit,
Under the third state, the storage device is in standby, and the electric power controller controls the column circuits And by the bit line to being pre-charged to tertiary voltage,
Under the 4th state, the electric power controller controls the peripheral circuit and makes the bit line in floating type State,
In a fifth state, by the control of the electric power controller, to the first power supply localization and the second source Localization supplies the first voltage, the 4th voltage, and the 4th voltage is lower than the second voltage,
Under the 6th state, by the control of the electric power controller, the first electricity described to the first power supply localization supply It presses and power gating is carried out to the second source localization,
Under the 7th state, by the control of the electric power controller, to the first power supply localization and the second source Localization carries out power gating,
Before being transferred to the 6th state from the third state or the 5th state, the electric power controller control The peripheral circuit and execute the first back-up job that the fallback circuit is written for the data to the memory cell array,
Also, before being transferred to the 7th state from the 6th state, the electric power controller controls the periphery Circuit and execute the second back-up job for the data of the fallback circuit are written again.
17. the working method of semiconductor device according to claim 16,
Wherein before being transferred to the third state from the 6th state, the electric power controller control periphery electricity Road and execute and the data from the fallback circuit are written to the first of the storage unit resume work,
And before being transferred to the third state from the 7th state, the electric power controller control periphery electricity Road and execute and the data of the fallback circuit are written to the second of the storage unit resume work.
18. the working method of semiconductor device according to claim 16,
Wherein under the 5th state, the electric power controller is supplying the 4th voltage to the second source localization Time when being more than the first setting time, it is fixed be supplied to for the voltage that will be less than the 4th voltage second source The control in domain.
19. the working method of semiconductor device according to claim 18,
Wherein when the time of the third state being more than the second setting time, the electric power controller control periphery electricity Working condition is transferred to the 4th state by road.
20. the working method of semiconductor device according to claim 19,
Wherein when the time of the 4th state being more than third setting time, the electric power controller control periphery electricity Road makes working condition be transferred to the 5th state.
21. the working method of semiconductor device according to claim 20,
Wherein when the time of the 5th state being more than four setting times, the electric power controller control periphery electricity Road executes first back-up job, working condition is made to be transferred to the 6th state.
22. the working method of semiconductor device according to claim 21,
Wherein when the time of the 6th state being more than five setting times, the electric power controller control periphery electricity Working condition is transferred to the 7th state after executing second back-up job by road.
23. the working method of semiconductor device according to claim 11,
Wherein the electric power controller generates the first to the 7th control signal, to switch the first to the 5th state,
The first state is standby mode, and described first is in the open state to third power switch, and the 4th power is opened Pass is in close state, and by first pre-charge circuit to the bit line to the first pre-charge voltage is inputted, described second is pre- Charging circuit is in close state, first and second described switching circuit is in the open state,
In order to be transferred to the second state from the first state, open first pre-charge circuit and described first and second Powered-down road is in close state,
In order to be transferred to the third state from second state, being in close state the third power switch and make described Four power switch are in the open state,
Under the 4th state, first and second described power switch is in the open state, and the third and the 4th power are opened Pass is in close state, first and second described pre-charge circuit and first and second described switching circuit are in and close shape State,
Under the 5th state, first to fourth switch is in close state,
The work sequence for being transferred to the 4th state from the third state includes: to be in the third power switch to open State；It is in close state the 4th power switch；Keep first and second described transistor in the open state；And The third power switch is in close state after being in close state first and second described transistor,
The work sequence for being transferred to the 5th state from the 4th state includes: to be in first and second described transistor to open State；Keep the third power switch in the open state；And it is in close state in first and second described transistor After be in close state first to fourth power switch.
24. the working method of semiconductor device according to claim 23,
It include: wherein to make first and second described transistor from the work sequence that the 4th state is transferred to the first state It is in the open state；Keep the third power switch in the open state；And it is in first and second described transistor After closed state by first pre-charge circuit to the bit line to the first pre-charge voltage is inputted, make described first and the Two switching circuits are in the open state.
25. the working method of semiconductor device according to claim 23,
It include: wherein to open first and second described power from the work sequence that the 5th state is transferred to the first state It closes in the open state；It is in close state first and second described switching circuit；By second pre-charge circuit to institute Rheme line is to input second pre-charge voltage；The row circuit makes the wordline be in choosing according to the 5th control signal Select state；Make first and second described transistor in the open state after making the wordline be in nonselection mode；Make institute It is in the open state to state third power switch；And by described after being in close state first and second described transistor First pre-charge circuit, to the first pre-charge voltage is inputted, is in first and second described switching circuit and opens to the bit line State.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112382326A (en) * 2020-12-11 2021-02-19 北京中科芯蕊科技有限公司 Sub-threshold dual-power SRAM reading auxiliary circuit

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10636470B2 (en) 2018-09-04 2020-04-28 Micron Technology, Inc. Source follower-based sensing scheme
JP7112060B2 (en) * 2018-12-26 2022-08-03 ルネサスエレクトロニクス株式会社 Semiconductor device and its power control method
US10796729B2 (en) * 2019-02-05 2020-10-06 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device
US10923185B2 (en) 2019-06-04 2021-02-16 Qualcomm Incorporated SRAM with burst mode operation
KR20210013387A (en) * 2019-07-24 2021-02-04 삼성전자주식회사 Memory system
CN114003079B (en) * 2020-07-28 2023-08-08 瑞昱半导体股份有限公司 Circuit applied to multiple power domains
US11437091B2 (en) * 2020-08-31 2022-09-06 Qualcomm Incorporated SRAM with robust charge-transfer sense amplification
CN118202413A (en) * 2021-11-12 2024-06-14 索尼半导体解决方案公司 Semiconductor circuit, driving method, and electronic apparatus
US11861233B2 (en) * 2021-12-22 2024-01-02 Micron Technology, Inc. Using duplicate data for improving error correction capability

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1905074A (en) * 2005-07-27 2007-01-31 松下电器产业株式会社 Semiconductor memory device
CN101295538A (en) * 2007-04-26 2008-10-29 日立超大规模集成电路系统株式会社 Semiconductor device
US20150269977A1 (en) * 2014-03-20 2015-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
TW201638949A (en) * 2015-01-26 2016-11-01 半導體能源研究所股份有限公司 Semiconductor device, electronic component, and electronic device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4353393B2 (en) 2001-06-05 2009-10-28 株式会社ルネサステクノロジ Semiconductor integrated circuit device
JP2003123479A (en) * 2001-10-12 2003-04-25 Matsushita Electric Ind Co Ltd Semiconductor memory
US8295079B2 (en) * 2007-08-31 2012-10-23 Tokyo Institute Of Technology Nonvolatile SRAM/latch circuit using current-induced magnetization reversal MTJ
WO2011102228A1 (en) * 2010-02-19 2011-08-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method of semiconductor device
JP6174899B2 (en) * 2012-05-11 2017-08-02 株式会社半導体エネルギー研究所 Semiconductor device
EP3182414B1 (en) * 2014-08-12 2021-01-13 Japan Science and Technology Agency Memory circuit
US9824749B1 (en) * 2016-09-02 2017-11-21 Arm Limited Read assist circuitry

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1905074A (en) * 2005-07-27 2007-01-31 松下电器产业株式会社 Semiconductor memory device
CN101295538A (en) * 2007-04-26 2008-10-29 日立超大规模集成电路系统株式会社 Semiconductor device
US20150269977A1 (en) * 2014-03-20 2015-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
TW201638949A (en) * 2015-01-26 2016-11-01 半導體能源研究所股份有限公司 Semiconductor device, electronic component, and electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112382326A (en) * 2020-12-11 2021-02-19 北京中科芯蕊科技有限公司 Sub-threshold dual-power SRAM reading auxiliary circuit
CN112382326B (en) * 2020-12-11 2023-11-17 北京中科芯蕊科技有限公司 Sub-threshold dual-power SRAM read auxiliary circuit

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