CN110166035B - Current compensation circuit and analog switch circuit - Google Patents
Current compensation circuit and analog switch circuit Download PDFInfo
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- CN110166035B CN110166035B CN201910562001.8A CN201910562001A CN110166035B CN 110166035 B CN110166035 B CN 110166035B CN 201910562001 A CN201910562001 A CN 201910562001A CN 110166035 B CN110166035 B CN 110166035B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
In the current compensation circuit and the analog switch circuit disclosed by the invention, when the third switch and the fourth switch are switched off and the first switch and the second switch are switched off, the compensation capacitor compensates charges required by the first parasitic capacitor and the second parasitic capacitor at two ends of the charging capacitor in the analog switch circuit. The invention utilizes the charge-discharge characteristic of the capacitor to independently establish the current compensation circuit for the parasitic capacitor, provides charges for the parasitic capacitors at two ends of the charging capacitor in the analog switch circuit through the compensation capacitor, and the charging capacitor in the analog switch circuit does not supply power for the parasitic capacitors at two ends when the analog switch is turned on, namely the charging capacitor provides grid source voltage for the N-type metal oxide semiconductor NMOS tube, thereby greatly reducing the generation of leakage current.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a current compensation circuit and an analog switch circuit.
Background
The analog switch is a commonly used circuit device, which is composed of an analog switch circuit and is mainly used for connecting and disconnecting a signal path connected with the analog switch circuit. In some application scenarios where signals are weak or impedance of the capacitive port is high, it is necessary that leakage current of the capacitive port of the analog switch in a conducting state is as small as possible, and transmission of the signals is not affected. If the analog switch has a large leakage current at the capacitive port in the conducting state, the transmitted signal will be changed or even completely wrong.
Specifically, the conventional analog switch circuit is composed of a main switch transistor NMOS, a capacitor C, and auxiliary switches S1, S2, S3, and S3. Among them, since the capacitance C is implemented in the chip, there are natural parasitic capacitances CA and CB from both ends thereof to the ground. And can hardly be eliminated. When S1 and S2 are closed and S3 and S4 are opened, the signal channels PA-M0-PB charge CA and CB through S1 and S2, charge leakage is caused, and external signals show a leakage current.
At present, no method for solving the problem of leakage current of the analog switch is found in the market.
Disclosure of Invention
The invention provides a current compensation circuit and an analog switch circuit, which can greatly reduce the leakage current of an analog switch and can adapt to various application scenes with strict requirements on the leakage current of an analog switch port.
In order to achieve the purpose, the invention provides the following technical scheme:
a current compensation circuit comprising:
an operational amplifier and a compensation capacitor;
the first switch is connected with the charging capacitor of the analog switch circuit at a first end and connected with the first end of the compensation capacitor at a second end; the charging capacitor is a capacitor for providing grid-source voltage for an N-type metal oxide semiconductor (NMOS) tube of the analog switch circuit;
the first end of the second switch is connected with the second end of the compensation capacitor, and the second end of the second switch is connected with the output end of the operational amplifier;
a third switch having a first end connected to the negative input terminal of the operational amplifier and a second end connected to the first end of the compensation capacitor;
the first end of the fourth switch is connected with the second end of the compensation capacitor, and the second end of the fourth switch is grounded;
the positive input end of the operational amplifier is connected with the source electrode of the N-type metal oxide semiconductor NMOS tube;
when the third switch and the fourth switch are turned off and the first switch and the second switch are turned off, the compensation capacitor compensates charges required by the first parasitic capacitor and the second parasitic capacitor.
Optionally, the compensation capacitor has a size equal to a sum of the first parasitic capacitor and the second parasitic capacitor.
Optionally, the size of the compensation capacitor is larger than the sum of the first parasitic capacitor and the second parasitic capacitor, and a difference between the compensation capacitor and the sum of the first parasitic capacitor and the second parasitic capacitor is within a preset threshold range.
An analog switching circuit, comprising:
an N-type metal oxide semiconductor NMOS tube;
a fifth switch, the first end of which is connected with the grid of the NMOS tube and the second end of which is connected with the first end of the charging capacitor; the charging capacitor is a capacitor for providing grid-source voltage for an N-type metal oxide semiconductor (NMOS) tube of the analog switch circuit;
the first end of the sixth switch is connected with the second end of the charging capacitor, and the second end of the sixth switch is connected with the source electrode of the N-type metal oxide semiconductor NMOS tube;
the first end of the seventh switch is connected with a power supply, and the second end of the seventh switch is connected with the first end of the charging capacitor;
the first end of the eighth switch is connected with the second end of the charging capacitor, and the second end of the eighth switch is grounded;
wherein when the seventh switch, the eighth switch, and the third switch and the fourth switch of the current compensation circuit are turned off, and the fifth switch, the sixth switch, and the first switch and the second switch of the current compensation circuit are turned off, the compensation capacitor of the current compensation circuit compensates for the charge required by the first parasitic capacitor and the second parasitic capacitor.
Optionally, the first switch, the second switch, the fifth switch, and the sixth switch are turned off or turned on simultaneously, and the third switch, the fourth switch, the seventh switch, and the eighth switch are turned off or turned on simultaneously.
Optionally, the compensation capacitor has a size equal to a sum of the first parasitic capacitor and the second parasitic capacitor.
Optionally, the size of the compensation capacitor is larger than the sum of the first parasitic capacitor and the second parasitic capacitor, and a difference between the compensation capacitor and the sum of the first parasitic capacitor and the second parasitic capacitor is within a preset threshold range.
According to the technical scheme, in the current compensation circuit and the analog switch circuit disclosed by the invention, when the third switch and the fourth switch are switched off and the first switch and the second switch are switched off, the compensation capacitor compensates charges required by the first parasitic capacitor and the second parasitic capacitor at two ends of the charging capacitor in the analog switch circuit. The invention utilizes the charge-discharge characteristic of the capacitor to independently establish the current compensation circuit for the parasitic capacitor, provides charges for the parasitic capacitors at two ends of the charging capacitor in the analog switch circuit through the compensation capacitor, and when the analog switch is turned on, namely the charging capacitor provides grid source voltage for the N-type metal oxide semiconductor NMOS tube, the charging capacitor in the analog switch circuit does not supply power for the parasitic capacitors at two ends of the charging capacitor, thereby greatly reducing the generation of leakage current.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a current compensation circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an analog switch circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a current compensation circuit and an analog switch circuit, which can greatly reduce the leakage current of an analog switch and can adapt to various application scenes with strict requirements on the leakage current of an analog switch port.
As shown in fig. 1, an embodiment of the present invention discloses a current compensation circuit, including:
an operational amplifier OP and a compensation capacitor C2.
A first switch S1 having a first end connected to the charging capacitor C1 of the analog switch circuit and a second end connected to the first end of the compensation capacitor C2; the charging capacitor C1 is a capacitor for supplying a gate-source voltage to an N-type Metal-Oxide-Semiconductor (NMOS) transistor of the analog switch circuit.
It should be noted that there are many structures of the analog switch circuit, but there are NMOS transistors as switches for switching on and off the circuit, and the characteristics of the NMOS transistor are that the circuit is turned on when the gate and the source are subjected to the gate-source voltage, and the circuit is turned off when the gate and the source are subjected to the voltage, so that the NMOS transistor is used as a switch device, and the manner of providing the gate-source voltage to the NMOS transistor is also various.
And the second switch S2 is connected with the first end of the compensation capacitor C2 and the second end of the compensation capacitor C2 and the output end of the operational amplifier OP.
And a third switch S3 having a first end connected to the negative input terminal of the operational amplifier OP and a second end connected to the first end of the compensation capacitor C2.
And the fourth switch S4 is connected with the second end of the compensation capacitor C2 at the first end and grounded at the second end.
And the positive input end of the operational amplifier OP is connected with the source electrode PB of the NMOS tube of the analog switch circuit.
When the third switch S3 and the fourth switch S4 are turned off and the first switch S1 and the second switch S2 are turned on, the compensation capacitor C2 compensates charges required by the first parasitic capacitor CA and the second parasitic capacitor CB.
It should be noted that, the operational amplifier OP is connected to the source PB of the NMOS transistor of the analog switch circuit, and when the charging capacitor C1 in the analog switch circuit applies a gate-source voltage to the NMOS transistor, a voltage is provided to the operational amplifier OP at the same time, as can be seen from the connection manner of the operational amplifier OP in fig. 1, the output voltage of the operational amplifier OP is the same as the input and output voltage, that is, the output voltage of the operational amplifier OP is the voltage of the source PB, and when the third switch S3 and the fourth switch S4 are closed and the first switch S1 and the second switch S2 are opened, the voltages at two ends of the compensation capacitor C2 are the output source PB voltage of the operational amplifier OP and the ground, so as to form a voltage difference, and charge the compensation capacitor C2.
It should be noted that, when a charging capacitor C1 in the analog switch circuit applies a gate-source voltage to an NMOS transistor, the third switch S3 and the fourth switch S4 in the current compensation circuit are turned off, the first switch S1 and the second switch S2 are turned on, and the compensation capacitor C2 compensates charges required by the first parasitic capacitor CA and the second parasitic capacitor CB; when the analog switch circuit charges the charging capacitor C1, the third switch S3 and the fourth switch S4 in the current compensation circuit are closed, and the first switch S1 and the second switch S2 are disconnected to charge the compensation capacitor C2.
In the current compensation circuit disclosed in this embodiment, when the third switch and the fourth switch are turned off and the first switch and the second switch are turned off, the compensation capacitor compensates charges required by the first parasitic capacitor and the second parasitic capacitor at both ends of the charging capacitor in the analog switch circuit. The invention utilizes the charge-discharge characteristic of the capacitor to independently establish the current compensation circuit for the parasitic capacitor, provides charges for the parasitic capacitors at two ends of the charging capacitor in the analog switch circuit through the compensation capacitor, and the charging capacitor in the analog switch circuit does not supply power for the parasitic capacitors at two ends when the analog switch is turned on, namely the charging capacitor provides grid source voltage for the N-type metal oxide semiconductor NMOS tube, thereby greatly reducing the generation of leakage current.
Optionally, the size of the compensation capacitor C2 is equal to the sum of the first parasitic capacitor CA and the second parasitic capacitor CB.
It should be noted that, since the compensation capacitor C2 only serves to fill the charges required by the first parasitic capacitor CA and the second parasitic capacitor CB to reduce the generation of the leakage current, the size of the compensation capacitor C2 only needs to be equal to the sum of the capacitances required by the first parasitic capacitor CA and the second parasitic capacitor CB, so as to avoid causing additional waste cost.
Optionally, the size of the compensation capacitor C2 is greater than the sum of the first parasitic capacitor CA and the second parasitic capacitor CB, and a difference between the compensation capacitor C2 and the sum of the first parasitic capacitor CA and the second parasitic capacitor CB is within a preset threshold range.
It should be noted that, because there will also be a pair of smaller parasitic capacitances at the two ends of the compensation capacitance C2, in order to ensure that the compensation capacitance C2 can completely supplement the charges required by the first parasitic capacitance CA and the second parasitic capacitance CB when performing charge compensation for the two parasitic capacitances, and reduce the generation of leakage current as much as possible, a capacitance slightly larger than the sum of the first parasitic capacitance CA and the second parasitic capacitance CB may be used as the compensation capacitance, the excess charges are used to provide charges for the small parasitic capacitances at the two ends of the compensation capacitance, and the specific difference threshold range may be determined with reference to the size of the small parasitic capacitances at the two ends of the compensation capacitance C2.
Based on the current compensation circuit disclosed in the above embodiment of the present invention, fig. 2 specifically discloses an analog switch circuit using the current compensation circuit.
As shown in fig. 2, another embodiment of the present invention discloses an analog switch circuit, including:
and an NMOS transistor M0.
A fifth switch S5 having a first end connected to the GATE of the NMOS transistor M0 and a second end connected to the first end of the charging capacitor C1; the charging capacitor C1 is a capacitor for providing grid-source voltage for an NMOS tube M0 of the analog switch circuit.
And the sixth switch S6 is connected with the first end of the charging capacitor C1 and the second end of the charging capacitor C1, and the source electrode PB of the NMOS tube M0.
And the first end of the seventh switch S7 is connected with a power supply VCC, and the second end of the seventh switch S7 is connected with the first end of the charging capacitor C1.
And the eighth switch S8 is connected with the second end of the charging capacitor C1 at the first end and grounded at the second end.
And a current compensation circuit.
Specifically, the current compensation circuit includes:
an operational amplifier OP and a compensation capacitor C2.
A first switch S1 having a first end connected to the charging capacitor C1 of the analog switch circuit and a second end connected to the first end of the compensation capacitor C2; the charging capacitor C1 is a capacitor for providing grid-source voltage for an NMOS tube of the analog switch circuit.
And the second switch S2 is connected with the first end of the compensation capacitor C2 and the second end of the compensation capacitor C2 and the output end of the operational amplifier OP.
And a third switch S3 having a first end connected to the negative input terminal of the operational amplifier OP and a second end connected to the first end of the compensation capacitor C2.
And the fourth switch S4 is connected with the second end of the compensation capacitor C2 at the first end and grounded at the second end.
And the positive input end of the operational amplifier OP is connected with the source electrode PB of the NMOS tube of the analog switch circuit.
When the seventh switch S7, the eighth switch S8, and the third switch S3 and the fourth switch S4 of the current compensation circuit are turned off, and the fifth switch S5, the sixth switch S6, and the first switch S1 and the second switch S2 of the current compensation circuit are turned on, the compensation capacitor C2 of the current compensation circuit compensates charges required by the first parasitic capacitor CA and the second parasitic capacitor CB.
In the analog switch circuit disclosed in this embodiment, when the seventh switch, the eighth switch, and the third switch and the fourth switch of the current compensation circuit are turned off, and the fifth switch, the sixth switch, and the first switch and the second switch of the current compensation circuit are turned off, the compensation capacitor of the current compensation circuit compensates charges required by the first parasitic capacitor and the second parasitic capacitor. The invention utilizes the charge-discharge characteristic of the capacitor to independently establish the current compensation circuit for the parasitic capacitor, provides charges for the parasitic capacitors at two ends of the charging capacitor in the analog switch circuit through the compensation capacitor, and the charging capacitor in the analog switch circuit does not supply power for the parasitic capacitors at two ends when the analog switch is turned on, namely the charging capacitor provides grid source voltage for the N-type metal oxide semiconductor NMOS tube, thereby greatly reducing the generation of leakage current.
Optionally, the first switch S1, the second switch S2, the fifth switch S5, and the sixth switch S6 are opened or closed at the same time, and the third switch S3, the fourth switch S4, the seventh switch S7, and the eighth switch S8 are opened or closed at the same time.
It should be noted that, when the fifth switch S5 and the sixth switch S6 are closed and the seventh switch S7 and the eighth switch S8 are opened, the charging capacitor C1 in the analog switch circuit applies a gate-source voltage to the NMOS transistor M0, and at the same time, the third switch S3 and the fourth switch S4 in the current compensation circuit are opened, the first switch S1 and the second switch S2 are closed, and the compensation capacitor C2 compensates charges required by the first parasitic capacitor CA and the second parasitic capacitor CB.
When the fifth switch S5 and the sixth switch S6 are switched off, and the seventh switch S7 and the eighth switch S8 are switched on, the analog switch circuit charges the charging capacitor C1, meanwhile, the third switch S3 and the fourth switch S4 in the current compensation circuit are switched on, and the first switch S1 and the second switch S2 are switched off to charge the compensation capacitor C2.
Optionally, the size of the compensation capacitor C2 is equal to the sum of the first parasitic capacitor CA and the second parasitic capacitor CB.
It should be noted that, since the compensation capacitor C2 only serves to fill the charges required by the first parasitic capacitor CA and the second parasitic capacitor CB to reduce the generation of the leakage current, the size of the compensation capacitor C2 only needs to be equal to the sum of the capacitances required by the first parasitic capacitor CA and the second parasitic capacitor CB, so as to avoid causing additional waste cost.
Optionally, the size of the compensation capacitor C2 is greater than the sum of the first parasitic capacitor CA and the second parasitic capacitor CB, and a difference between the compensation capacitor C2 and the sum of the first parasitic capacitor CA and the second parasitic capacitor CB is within a preset threshold range.
It should be noted that, because there will also be a pair of smaller parasitic capacitances at the two ends of the compensation capacitance C2, in order to ensure that the compensation capacitance C2 can completely supplement the charges required by the first parasitic capacitance CA and the second parasitic capacitance CB when performing charge compensation for the two parasitic capacitances, and reduce the generation of leakage current as much as possible, a capacitance slightly larger than the sum of the first parasitic capacitance CA and the second parasitic capacitance CB may be used as the compensation capacitance, the excess charges are used to provide charges for the small parasitic capacitances at the two ends of the compensation capacitance, and the specific difference threshold range may be determined with reference to the size of the small parasitic capacitances at the two ends of the compensation capacitance C2.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (7)
1. A current compensation circuit, comprising:
an operational amplifier and a compensation capacitor;
the first switch is connected with the charging capacitor of the analog switch circuit at a first end and connected with the first end of the compensation capacitor at a second end; the charging capacitor is a capacitor for providing grid-source voltage for an N-type metal oxide semiconductor (NMOS) tube of the analog switch circuit;
the first end of the second switch is connected with the second end of the compensation capacitor, and the second end of the second switch is connected with the output end of the operational amplifier;
the first end of the third switch is connected with the negative input end of the operational amplifier, and the second end of the third switch is connected with the first end of the compensation capacitor;
the first end of the fourth switch is connected with the second end of the compensation capacitor, and the second end of the fourth switch is grounded;
the positive input end of the operational amplifier is connected with the source electrode of the N-type metal oxide semiconductor NMOS tube;
when the third switch and the fourth switch are turned off and the first switch and the second switch are turned off, the compensation capacitor compensates charges required by the first parasitic capacitor and the second parasitic capacitor.
2. The current compensation circuit of claim 1, wherein the compensation capacitance is equal in magnitude to a sum of the first parasitic capacitance and the second parasitic capacitance.
3. The current compensation circuit of claim 1, wherein the compensation capacitor has a magnitude greater than a sum of the first parasitic capacitor and the second parasitic capacitor, and a difference between the compensation capacitor and the sum of the first parasitic capacitor and the second parasitic capacitor is within a predetermined threshold range.
4. An analog switching circuit, comprising:
an N-type metal oxide semiconductor NMOS tube;
the first end of the fifth switch is connected with the grid electrode of the N-type metal oxide semiconductor NMOS tube, and the second end of the fifth switch is connected with the first end of the charging capacitor; the charging capacitor is a capacitor for providing grid-source voltage for an N-type metal oxide semiconductor (NMOS) tube of the analog switch circuit;
the first end of the sixth switch is connected with the second end of the charging capacitor, and the second end of the sixth switch is connected with the source electrode of the N-type metal oxide semiconductor NMOS tube;
the first end of the seventh switch is connected with a power supply, and the second end of the seventh switch is connected with the first end of the charging capacitor;
the first end of the eighth switch is connected with the second end of the charging capacitor, and the second end of the eighth switch is grounded;
the current compensation circuit of claim 1;
wherein when the seventh switch, the eighth switch, and the third switch and the fourth switch of the current compensation circuit are turned off, and the fifth switch, the sixth switch, and the first switch and the second switch of the current compensation circuit are turned off, the compensation capacitor of the current compensation circuit compensates for the charge required by the first parasitic capacitor and the second parasitic capacitor;
the current compensation circuit includes: and the first switch is connected with the first end of the compensation capacitor at the second end.
5. The analog switch circuit of claim 4, wherein the first switch, the second switch, the fifth switch, and the sixth switch are open or closed at the same time, and wherein the third switch, the fourth switch, the seventh switch, and the eighth switch are open or closed at the same time.
6. The analog switch circuit of claim 4, wherein the compensation capacitance is equal in magnitude to a sum of the first parasitic capacitance and the second parasitic capacitance.
7. The analog switch circuit of claim 4, wherein the compensation capacitor has a magnitude greater than a sum of the first parasitic capacitor and the second parasitic capacitor, and a difference between the compensation capacitor and the sum of the first parasitic capacitor and the second parasitic capacitor is within a predetermined threshold.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910562001.8A CN110166035B (en) | 2019-06-26 | 2019-06-26 | Current compensation circuit and analog switch circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910562001.8A CN110166035B (en) | 2019-06-26 | 2019-06-26 | Current compensation circuit and analog switch circuit |
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| CN110166035A CN110166035A (en) | 2019-08-23 |
| CN110166035B true CN110166035B (en) | 2023-03-21 |
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| CN111650441B (en) * | 2020-06-11 | 2022-05-17 | 上海艾为电子技术股份有限公司 | Capacitance detection circuit, capacitance detection method and electronic equipment |
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| CN2598227Y (en) * | 2002-12-23 | 2004-01-07 | 陈国强 | Power capacitance intelligent compensator |
| CN101677022A (en) * | 2008-09-18 | 2010-03-24 | 电力集成公司 | Leakage compensation for sample and hold devices |
| CN107707103A (en) * | 2017-10-30 | 2018-02-16 | 电子科技大学 | A kind of sectional slope compensation circuit suitable for BUCK converters |
| CN109379070A (en) * | 2018-12-20 | 2019-02-22 | 上海艾为电子技术股份有限公司 | A kind of analog switch start-up circuit and method |
-
2019
- 2019-06-26 CN CN201910562001.8A patent/CN110166035B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2598227Y (en) * | 2002-12-23 | 2004-01-07 | 陈国强 | Power capacitance intelligent compensator |
| CN101677022A (en) * | 2008-09-18 | 2010-03-24 | 电力集成公司 | Leakage compensation for sample and hold devices |
| CN107707103A (en) * | 2017-10-30 | 2018-02-16 | 电子科技大学 | A kind of sectional slope compensation circuit suitable for BUCK converters |
| CN109379070A (en) * | 2018-12-20 | 2019-02-22 | 上海艾为电子技术股份有限公司 | A kind of analog switch start-up circuit and method |
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