CN110165917A - The single-phase double Buck full-bridge inverters of aspergillus ficuum and its control strategy - Google Patents
The single-phase double Buck full-bridge inverters of aspergillus ficuum and its control strategy Download PDFInfo
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- CN110165917A CN110165917A CN201910347284.4A CN201910347284A CN110165917A CN 110165917 A CN110165917 A CN 110165917A CN 201910347284 A CN201910347284 A CN 201910347284A CN 110165917 A CN110165917 A CN 110165917A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
Abstract
The invention discloses the single-phase double Buck full-bridge inverters of aspergillus ficuum and its control strategies, belong to converters technical field.The fixed acyclic flow control policy of frequency of unipolarity modulation proposed by the present invention for the double Buck full-bridge inverters of tradition, it solves the problems, such as that traditional double Buck full-bridge inverter control strategies cannot can determine frequency non-loop operation using unipolarity modulation, helps to improve inverter efficiency.The double Buck full-bridge inverters of dual input proposed by the present invention, can connect two direct current input sources simultaneously and generate plurality of level, improve the reliability and efficiency of inverter.The fixed acyclic flow control policy of frequency of the unipolarity modulation of the double Buck full-bridge inverters of dual input proposed by the present invention, is modulated using unipolarity, and the double Buck full-bridge inverters of dual input is made to determine frequency non-loop operation, further improves the double Buck full-bridge inverter efficiency of dual input.
Description
Technical field
The present invention relates to the single-phase double Buck full-bridge inverters of aspergillus ficuum and its control strategies, belong to power electronic technique neck
Domain particularly belongs to DC-AC transformation of electrical energy technical field.
Background technique
In recent years, the rapid development of more electric aircrafts and generation of electricity by new energy proposes the reliability and efficiency of inverter higher
Requirement.Conventional bridge inverter is since switching tube is connected with input power, and there are bridge arm direct pass risks.For this purpose, scholars mention
A variety of dual Buck inverters are gone out.While dual Buck inverter solves the problems, such as that conventional full bridge inverter leg is led directly to, due to
Without body diode afterflow, efficiency is also higher.In many dual Buck inverters, double Buck full-bridge inverters are due to DC voltage
Utilization rate is high, way traffic can be achieved is widely applied.But the control mode of existing double Buck full-bridge inverters or
Person cannot achieve the unipolarity non-loop operation of inverter, limit the efficiency of inverter；Or non-loop operation may be implemented,
But working frequency is not fixed, filter design difficult.Therefore, the fixed frequency of unipolarity modulation of double Buck full-bridge inverters how is realized
Non-loop operation further increases the efficiency of inverter, is current problem to be solved.
On the other hand, aerospace applications occasion needs multiple direct current input source power supplies, to improve the reliability of inverter；
Generation of electricity by new energy occasion, to make full use of multiple energy, it is also desirable to which inverter provides multiple direct-flow input end mouths.Therefore, how
Make inverter while connecting multiple direct current input sources, is another urgent problem.
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes the unipolarities of double Buck full-bridge inverters to modulate acyclic flow control
Strategy proposes the double Buck full-bridge inverters of dual input and its acyclic flow control policy of unipolarity modulation, current for solving
Deficiency of the Buck full-bridge inverter on topological structure and control strategy.
To achieve the above object, the technical solution adopted by the present invention are as follows:
The unipolarity of double Buck full-bridge inverters modulates acyclic flow control policy, it is characterised in that:
Double Buck full-bridge inverters are by input voltage source (Vin), first switch tube (S1), second switch (S2), third opens
Close pipe (S3), the 4th switching tube (S4), first diode (D1), the second diode (D2), third diode (D3), the 4th diode
(D4), forward filtering inductance (LP), inverse filtering inductance (LN), public filter inductance (Lf) and load (Z) composition.Wherein, direct current
Input voltage source (Vin) anode be connected in first switch tube (S1) collector, second switch (S2) collector, the three or two
Pole pipe (D3) cathode and the 4th diode (D4) cathode；First switch tube (S1) emitter be connected in forward filtering inductance
(LP) one end and first diode (D1) cathode；Forward filtering inductance (LP) the other end be connected in third diode (D3)
Anode, public filter inductance (Lf) one end and third switching tube (S3) collector；Public filter inductance (Lf) the other end connect
In one end of load (Z)；Second switch (S2) emitter be connected in inverse filtering inductance (LN) one end and the second diode
(D2) cathode；Inverse filtering inductance (LN) the other end be connected in the 4th diode (D4) anode, the 4th switching tube (S4) collection
The other end of electrode and load (Z)；Input voltage (Vin) cathode be connected in first diode (D1) anode, third switching tube
(S3) emitter, the 4th switching tube (S4) emitter and the second diode (D2) anode.
Its control system is made of outer voltage and current inner loop.Sampled voltage vosWith voltage reference vrefCompare to obtain electricity
Hold up difference.Voltage error value passes through outer voltage adjuster GVProcessing, exports as public filter inductance (Lf) current reference
iLf_ref.Public filter inductance (Lf) electric current sampled value iLfsWith current reference iLf_refCompare to obtain current error value.Electric current misses
Difference passes through current inner loop adjuster GIProcessing, exports as modulating wave vr.Here voltage regulator GVWith current regulator GIIt can
To be the common adjuster of any inverter, such as proportional-integral controller, proportional-integral-differential adjuster, ratio-resonance
Adjuster etc..
Public filter inductance (Lf) current reference iLf_refCompared with 0, work as iLf_refWhen >=0, output signal IPFor logic
High level 1, output signal INFor logic low 0；Work as iLf_refWhen < 0, output signal INFor logic high 1, output signal
IPFor logic low 0.Modulation system is modulated using unipolarity.vTriPBe positive triangular wave, vTriNBe negative triangular wave, the two amplitude
It is equal.
In public filter inductance (Lf) current reference iLf_refWhen >=0, second switch (S2) and third switching tube
(S3) be held off, first switch tube (S1) and the 4th switching tube (S4) modulation work:
Work as vr>=vTriPWhen, first switch tube (S1) and the 4th switching tube (S4) conducting, bridge arm midpoint APAnd BPBetween
Voltage is Vin；
Work as vTriP> vrWhen >=0, the 4th switching tube (S4) and first diode (D1) conducting, bridge arm midpoint APAnd BPBetween
Voltage be 0；
As 0 > vr>=vTriNWhen, first switch tube (S1) and the 4th diode (D4) conducting, bridge arm midpoint APAnd BPBetween
Voltage be 0；
Work as vTriN> vrWhen, first switch tube (S1) be connected and the 4th switching tube (S4) be not turned on, first diode (D1)
With the 4th diode (D4) conducting, bridge arm midpoint APAnd BPBetween voltage be-Vin。
In public filter inductance (Lf) current reference iLf_refWhen < 0, first switch tube (S1) and the 4th switching tube (S4)
It is held off, second switch (S2) and third switching tube (S3) modulation work:
Work as vr>=vTriPWhen, second switch (S2) and third switching tube (S3) be not turned on, the second diode (D2) and
Third diode (D3) conducting, bridge arm midpoint ANAnd BNBetween voltage be Vin；
Work as vTriP> vrWhen >=0, second switch (S2) and third diode (D3) conducting, bridge arm midpoint ANAnd BNBetween
Voltage be 0；
As 0 > vr>=vTriNWhen, third switching tube (S3) and the second diode (D2) conducting, bridge arm midpoint ANAnd BNBetween
Voltage be 0；
Work as vTriN> vrWhen, second switch (S2) and third switching tube (S3) conducting, bridge arm midpoint ANAnd BNBetween electricity
Pressure is-Vin。
A kind of double Buck full-bridge inverters of dual input input voltage source (V by high voltage direct currentH), low-voltage direct input electricity
Potential source (VL), first switch tube (S1), second switch (S2), third switching tube (S3), the 4th switching tube (S4), the 5th switching tube
(S5), the 6th switching tube (S6), first diode (D1), the second diode (D2), third diode (D3), the 4th diode
(D4), the 5th diode (D5), the 6th diode (D6), forward filtering inductance (LP), inverse filtering inductance (LN), public filtered electrical
Feel (Lf) and load (Z) composition.Wherein, the high voltage direct current inputs voltage source (VH) anode be connected in first switch tube (S1)
Collector, the 6th diode (D6) cathode, the 5th diode (D5) cathode and second switch (S2) collector；First
Switching tube (S1) emitter be connected in first diode (D1) cathode and third switching tube (S3) collector；Third switching tube
(S3) emitter be connected in forward filtering inductance (LP) one end and third diode (D3) cathode；Forward filtering inductance (LP)
The other end be connected in public filter inductance (Lf) one end, the 6th diode (D6) anode and the 6th switching tube (S6) current collection
Pole；Public filter inductance (Lf) the other end be connected in one end of load (Z)；Second switch (S2) emitter be connected in second
Diode (D2) cathode and the 4th switching tube (S4) collector；4th switching tube (S4) emitter be connected in inverse filtering electricity
Feel (LN) one end and the 4th diode (D4) cathode；Inverse filtering inductance (LN) the other end be connected in the 5th diode (D5)
Anode, the 5th switching tube (S5) collector and load (Z) the other end；Low-voltage direct input voltage source (VL) anode even
In first diode (D1) anode and the second diode (D2) anode；High voltage direct current inputs voltage source (VH) cathode be connected
In low-voltage direct input voltage source (VL) cathode, third diode (D3) anode, the 6th switching tube (S6) emitter,
Five switching tube (S5) emitter and the 4th diode (D4) anode.
Unipolarity based on the double Buck full-bridge inverters of dual input modulates acyclic flow control policy, it is characterised in that:
Sampled voltage vosWith voltage reference vrefCompare to obtain voltage error value.Voltage error value is adjusted by outer voltage
Device GVProcessing, exports as public filter inductance (Lf) current reference iLf_ref.Public filter inductance (Lf) electric current sampled value iLfs
With current reference iLf_refCompare to obtain current error value.Current error value passes through current inner loop adjuster GIProcessing exports to adjust
Wave v processedr.Here voltage regulator GVWith current regulator GIIt can be the common adjuster of any inverter, such as ratio-
Integral controller, proportional-integral-differential adjuster, ratio-resonant regulator etc..
Public filter inductance (Lf) current reference iLf_refCompared with 0, work as iLf_refWhen >=0, output signal IPFor logic
High level 1, output signal INFor logic low 0；Work as iLf_refWhen < 0, output signal INFor logic high 1, output signal
IPFor logic low 0.Modulation system is modulated using unipolarity.vTri1PAnd vTri2PBe positive triangular wave, vTri1NAnd vTri2NIt is negative three
Angle wave, vTri1PAnd vTri1NAmplitude is equal, is Δ vTri1。vTr2PAnd vTri2NAmplitude is equal, is Δ vTri2。ΔvTri1With Δ vTri2It is full
Foot:
Four triangular carriers are followed successively by v from top to bottomTri1P、vTri2P、vTri1NAnd vTri2N。vTri1PAnd vTri2PCut off value be
ΔvTri2, vTri2PAnd vTri1NCut off value be 0, vTri1NAnd vTri2NCut off value be-Δ vTri1。
In public filter inductance (Lf) current reference iLf_refWhen >=0, second switch (S2), the 4th switching tube (S4)
With the 6th switching tube (S6) be held off, first switch tube (S1), third switching tube (S3) and the 5th switching tube (S5) modulation work
Make:
Work as vr>=vTri1PWhen, first switch tube (S1), third switching tube (S3) and the 5th switching tube (S5) conducting, bridge arm
Midpoint APAnd BPBetween voltage be VH；
Work as vTri1P> vr>=vTri2PWhen, first diode (D1), third switching tube (S3) and the 5th switching tube (S5) lead
It is logical, bridge arm midpoint APAnd BPBetween voltage be VL；
Work as vTri2P> vrWhen >=0, third diode (D3) and the 5th switching tube (S5) conducting, bridge arm midpoint APAnd BPIt
Between voltage be 0；
As 0 > vr>=vTri1NWhen, first switch tube (S1), third switching tube (S3) and the 5th diode (D5) conducting, bridge
Arm midpoint APAnd BPBetween voltage be 0；
Work as vTri1N> vr>=vTri2NWhen, first diode (D1), third switching tube (S3) and the 5th diode (D5) lead
It is logical, bridge arm midpoint APAnd BPBetween voltage be VL-VH；
Work as vTri2N> vrWhen, third diode (D3) and the 5th diode (D5) conducting, bridge arm midpoint APAnd BPBetween electricity
Pressure is-VH。
In public filter inductance (Lf) current reference iLf_refWhen < 0, first switch tube (S1), third switching tube (S3) and
5th switching tube (S5) be held off, second switch (S2), the 4th switching tube (S4) and the 6th switching tube (S6) modulation work:
As (- vr) >=vTri1PWhen, second switch (S2), the 4th switching tube (S4) and the 6th switching tube (S6) conducting, bridge
Arm midpoint ANAnd BNBetween voltage be-VH；
Work as vTri1P> (- vr) >=vTri2PWhen, the second diode (D2), the 4th switching tube (S4) and the 6th switching tube (S6)
Conducting, bridge arm midpoint ANAnd BNBetween voltage be-VL；
Work as vTri2P> (- vr) >=0 when, the 4th diode (D4) and the 6th switching tube (S6) conducting, bridge arm midpoint ANAnd BN
Between voltage be 0；
As 0 > (- vr) >=vTri1NWhen, second switch (S2), the 4th switching tube (S4) and the 6th diode (D6) lead
It is logical, bridge arm midpoint ANAnd BNBetween voltage be 0；
Work as vTri1N> (- vr) >=vTri2NWhen, the second diode (D2), the 4th switching tube (S4) and the 6th diode (D6)
Conducting, bridge arm midpoint ANAnd BNBetween voltage be VH-VL；
Work as vTri2N> (- vr) when, the 4th diode (D4) and the 6th diode (D6) conducting, bridge arm midpoint ANAnd BNBetween
Voltage be VH。
Above-mentioned high voltage direct current inputs voltage source (VH) voltage must be not less than low-voltage direct input voltage source (VL) electricity
Pressure.
The utility model has the advantages that
(1) the single-phase double Buck full-bridge inverters of aspergillus ficuum of the present invention and its control strategy propose double Buck full-bridge invertings
The unipolarity of device modulates acyclic flow control policy, simplifies double Buck full-bridge inverter filter designs, improves inverter
Efficiency；
(2) it is complete to propose the double Buck of dual input for the single-phase double Buck full-bridge inverters of aspergillus ficuum of the present invention and its control strategy
Bridge inverter, retain traditional dual Buck inverter without bridge arm direct pass risk, restore advantage without body diode reverse on the basis of,
Two direct-flow input end mouths can be connected simultaneously and generate plurality of level, improve the reliability and efficiency of inverter；
(3) it is complete to propose the double Buck of dual input for the single-phase double Buck full-bridge inverters of aspergillus ficuum of the present invention and its control strategy
The unipolarity of bridge inverter modulates acyclic flow control policy, simplify the double Buck full-bridge inverter filters of dual input design,
Further improve the efficiency of inverter.
Detailed description of the invention
Attached drawing 1 is that the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy corresponding pair
The circuit diagram of Buck full-bridge inverter；
Attached drawing 2 is that the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy block diagram；
Attached drawing 3 be double Buck full-bridge inverters proposed by the present invention unipolarity modulate it is double under acyclic flow control policy
The key waveforms figure of Buck full-bridge inverter；
Attached drawing 4 is the circuit diagram of the double Buck full-bridge inverters of dual input proposed by the present invention；
Attached drawing 5 is that the unipolarity of the double Buck full-bridge inverters of dual input proposed by the present invention modulates acyclic flow control policy frame
Figure；
Attached drawing 6 is the acyclic flow control policy of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under the double Buck full-bridge inverters of dual input key waveforms figure；
Attached drawing 7 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in first quartile (io> 0, vo> 0) and DC input voitage source (Vin) when powering to the load etc.
Imitate circuit diagram；
Attached drawing 8 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in first quartile (io> 0, vo> 0) and load and DC input voitage source (Vin) between noenergy pass
Equivalent circuit diagram when passing；
Attached drawing 9 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in fourth quadrant (io> 0, vo< 0) and load and DC input voitage source (Vin) between noenergy pass
Equivalent circuit diagram when passing；
Attached drawing 10 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in fourth quadrant (io> 0, vo< 0) and load to DC input voitage source (Vin) feedback energy when
Equivalent circuit diagram；
Attached drawing 11 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in the second quadrant (io< 0, vo> 0) and load to DC input voitage source (Vin) feedback energy when
Equivalent circuit diagram；
Attached drawing 12 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in the second quadrant (io< 0, vo> 0) and load and DC input voitage source (Vin) between noenergy pass
Equivalent circuit diagram when passing；
Attached drawing 13 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in third quadrant (io< 0, vo< 0) and load and DC input voitage source (Vin) between noenergy pass
Equivalent circuit diagram when passing；
Attached drawing 14 be in the case where the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control policy, it is double
Buck full-bridge inverter works in third quadrant (io< 0, vo< 0) and DC input voitage source (Vin) when powering to the load etc.
Imitate circuit diagram；
Attached drawing 15 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in first quartile (io> 0, vo> 0) and high voltage direct current input voltage source (VH)
Equivalent circuit diagram when individually powering to the load；
Attached drawing 16 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in first quartile (io> 0, vo> 0) and low-voltage direct input voltage source (VL)
Equivalent circuit diagram when individually powering to the load；
Attached drawing 17 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in first quartile (io> 0, vo> 0) and high voltage direct current input voltage source
(VH), low-voltage direct input voltage source (VL) and load between noenergy transmitting when equivalent circuit diagram；
Attached drawing 18 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in fourth quadrant (io> 0, vo< 0) and load and high voltage direct current input voltage
Source (VH), low-voltage direct input voltage source (VL) between noenergy transmitting when equivalent circuit diagram；
Attached drawing 19 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in fourth quadrant (io> 0, vo< 0) and load and low-voltage direct input voltage
Source (VL) jointly to high voltage direct current potential source (VH) transmitting energy when equivalent circuit diagram；
Attached drawing 20 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in fourth quadrant (io> 0, vo< 0) and load individually to high voltage direct current input
Voltage source (VH) feedback energy when equivalent circuit diagram；
Attached drawing 21 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in third quadrant (io< 0, vo< 0) and high voltage direct current input voltage source (VH)
Equivalent circuit diagram when individually powering to the load；
Attached drawing 22 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in third quadrant (io< 0, vo< 0) and low-voltage direct input voltage source (VL)
Equivalent circuit diagram when individually transmitting from energy to load；
Attached drawing 23 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in third quadrant (io< 0, vo< 0) and load and high voltage direct current input voltage
Source (VH), low-voltage direct input voltage source (VL) between noenergy transmitting when equivalent circuit diagram；
Attached drawing 24 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in the second quadrant (io< 0, vo> 0) and load and high voltage direct current input voltage
Source (VH), low-voltage direct input voltage source (VL) between noenergy transmitting when equivalent circuit diagram；
Attached drawing 25 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in the second quadrant (io< 0, vo> 0) and load and low-voltage direct input voltage
Source (VL) jointly to high voltage direct current potential source (VH) transmitting energy when equivalent circuit diagram；
Attached drawing 26 is the acyclic flow control plan of unipolarity modulation in the double Buck full-bridge inverters of dual input proposed by the present invention
Under slightly, the double Buck full-bridge inverter work of dual input are in the second quadrant (io< 0, vo> 0) and load to high voltage direct current input voltage
Source (VH) independent feedback energy when equivalent circuit diagram；
Designation in the figures above:
It is modulated in acyclic flow control policy in double Buck full-bridge inverters and its unipolarity: VinFor DC input voitage source,
S1、S2、S3And S4Respectively the first, second, third and fourth switching tube, D1、D2、D3And D4Respectively the first, second, third He
4th diode, Lp、LNPoint and LfNot Wei positive, reversed and public filter inductance, Z be load, voFor load voltage, AP、AN、
BP、BNThe midpoint of respectively each bridge arm, vAFor bridge arm midpoint APOr ANCurrent potential, vBFor bridge arm midpoint BPOr BNCurrent potential, vAB
For vA-vB。vrefFor output voltage benchmark, vosFor output voltage sampled value, iLf_refFor public filter inductance (Lf) electric current benchmark
Value, iLfsFor public filter inductance (Lf) electric current sampled value, vrFor modulating wave, vTriPAnd vTriNRespectively amplitude it is equal just,
Negative triangular carrier, P, Z, N are respectively vrAnd vTriP、0、vTriNCompare the signal of generation,WithBe respectively and P, Z and N
Opposite logical signal, IPFor iLf_refThe signal of generation, I compared with 0 levelNFor with IPOpposite logical signal, vgs1、vgs2、
vgs3And vgs4Respectively switching tube S1~S4Driving signal.
It is modulated in acyclic flow control policy in the double Buck full-bridge inverters of dual input and its unipolarity: VHFor high-voltage dc transmission
Enter voltage source, VLFor low-voltage direct input voltage source, S1、S2、S3、S4、S5And S6Respectively first, second, third, fourth,
Five and the 6th switching tube, D1、D2、D3、D4、D5And D6The diode of respectively first, second, third, fourth, the 5th and the 6th, Lp、
LNPoint and LfNot Wei positive, reversed and public filter inductance, Z be load, voFor load voltage, AP、AN、BP、BNIt is respectively each
The midpoint of bridge arm, vAFor bridge arm midpoint APOr ANCurrent potential, vBFor bridge arm midpoint BPOr BNCurrent potential, vABFor vA-vB。vrefIt is defeated
Voltage reference out, vosFor output voltage sampled value, iLf_refTo export current reference value, iLfsFor public filter inductance (Lf) electric current
Sampled value, vrFor modulating wave, vTri1P、vTri2P、vTri1NAnd vTri2NFour triangular carriers respectively successively from top to bottom.P1P、
P2P、ZP、N1PAnd N2PRespectively vrAnd vTri1P、vTri2P、0、vTri1NAnd vTri2NCompare the signal of generation, P1N、P2N、ZN、N1NAnd N2N
Respectively-vrAnd vTri1P、vTri2P、0、vTri1NAnd vTri2NCompare the signal of generation, IPFor iLf_refThe letter of generation compared with 0 level
Number, INFor with IPOpposite logical signal, vgs1、vgs2、vgs3、vgs4、vgs5And vgs6Respectively switching tube S1~S6Driving letter
Number.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing.
The unipolarity of double Buck full-bridge inverters modulates acyclic flow control policy, it is characterised in that:
The circuit diagram of double Buck full-bridge inverters is as shown in Fig. 1: by input voltage source (Vin), first switch tube
(S1), second switch (S2), third switching tube (S3), the 4th switching tube (S4), first diode (D1), the second diode
(D2), third diode (D3), the 4th diode (D4), forward filtering inductance (LP), inverse filtering inductance (LN), public filtered electrical
Feel (Lf) and load (Z) composition.Wherein, DC input voitage source (Vin) anode be connected in first switch tube (S1) collector,
Second switch (S2) collector, third diode (D3) cathode and the 4th diode (D4) cathode；First switch tube
(S1) emitter be connected in forward filtering inductance (LP) one end and first diode (D1) cathode；Forward filtering inductance (LP)
The other end be connected in third diode (D3) anode, public filter inductance (Lf) one end and third switching tube (S3) current collection
Pole；Public filter inductance (Lf) the other end be connected in one end of load (Z)；Second switch (S2) emitter be connected in reversed filter
Wave inductance (LN) one end and the second diode (D2) cathode；Inverse filtering inductance (LN) the other end be connected in the 4th diode
(D4) anode, the 4th switching tube (S4) collector and load (Z) the other end；Input voltage (Vin) cathode be connected in first
Diode (D1) anode, third switching tube (S3) emitter, the 4th switching tube (S4) emitter and the second diode (D2)
Anode.
Attached drawing 2 and attached drawing 3 are respectively that the unipolarity of double Buck full-bridge inverters is modulated acyclic flow control policy block diagram and is somebody's turn to do
The key waveforms figure of tactful lower pair of Buck full-bridge inverter.
Its control system is made of outer voltage and current inner loop.Sampled voltage vosWith voltage reference vrefCompare to obtain electricity
Hold up difference.Voltage error value passes through outer voltage adjuster GVProcessing, exports as public filter inductance (Lf) current reference
iLf_ref.Public filter inductance (Lf) electric current sampled value iLfsWith current reference iLf_refCompare to obtain current error value.Electric current misses
Difference passes through current inner loop adjuster GIProcessing, exports as modulating wave vr.Here voltage regulator GVWith current regulator GIIt can
To be the common adjuster of any inverter, such as proportional-integral controller, proportional-integral-differential adjuster, ratio-resonance
Adjuster etc..
Public filter inductance (Lf) current reference iLf_refCompared with 0, work as iLf_refWhen >=0, output signal IPFor logic
High level 1, output signal INFor logic low 0；Work as iLf_refWhen < 0, output signal INFor logic high 1, output signal
IPFor logic low 0.Modulation system is modulated using unipolarity.vTriPBe positive triangular wave, vTriNBe negative triangular wave, the two amplitude
It is equal.
In public filter inductance (Lf) current reference iLf_refWhen >=0, second switch (S2) and third switching tube
(S3) be held off, first switch tube (S1) and the 4th switching tube (S4) modulation work:
Work as vr>=vTriPWhen, first switch tube (S1) and the 4th switching tube (S4) conducting, DC input voitage source (Vin) to
Load supplying, bridge arm midpoint APAnd BPBetween voltage be Vin, as shown in Fig. 7；
Work as vTriP> vrWhen >=0, the 4th switching tube (S4) and first diode (D1) conducting, direct current input source (Vin) with
Noenergy is transmitted between load, bridge arm midpoint APAnd BPBetween voltage be 0, as shown in Fig. 8；
As 0 > vr>=vTriNWhen, first switch tube (S1) and the 4th diode (D4) conducting, direct current input source (Vin) with
Noenergy is transmitted between load, bridge arm midpoint APAnd BPBetween voltage be 0, as shown in Fig. 9；
Work as vTriN> vrWhen, first switch tube (S1) be connected and the 4th switching tube (S4) be not turned on, first diode (D1)
With the 4th diode (D4) conducting, it loads to DC input voitage source (Vin) feedback energy, bridge arm midpoint APAnd BPBetween voltage
For-Vin, as shown in Fig. 10.
In public filter inductance (Lf) current reference iLf_refWhen < 0, first switch tube (S1) and the 4th switching tube (S4)
It is held off, second switch (S2) and third switching tube (S3) modulation work:
Work as vr>=vTriPWhen, second switch (S2) and third switching tube (S3) be not turned on, the second diode (D2) and
Third diode (D3) conducting, it loads to DC input voitage source (Vin) feedback energy, bridge arm midpoint ANAnd BNBetween voltage be
Vin, as shown in Fig. 11；
Work as vTriP> vrWhen >=0, second switch (S2) and third diode (D3) conducting, direct current input source (Vin) with
Noenergy is transmitted between load, bridge arm midpoint ANAnd BNBetween voltage be 0, as shown in Fig. 12；
As 0 > vr>=vTriNWhen, third switching tube (S3) and the second diode (D2) conducting, direct current input source (Vin) with
Noenergy is transmitted between load, bridge arm midpoint ANAnd BNBetween voltage be 0, as shown in Fig. 13；
Work as vTriN> vrWhen, second switch (S2) and third switching tube (S3) conducting, DC input voitage source (Vin) to negative
Carry power supply, bridge arm midpoint ANAnd BNBetween voltage be-Vin, as shown in Fig. 14.
As can be seen from the above analysis, the unipolarity of double Buck full-bridge inverters proposed by the present invention modulates acyclic flow control
Strategy, double Buck full-bridge inverters can be realized under unipolarity modulation determines frequency non-loop operation, simplifies filter design, mentions
The high efficiency of inverter.
A kind of double Buck full-bridge inverters of dual input are as shown in Fig. 4: inputting voltage source (V by high voltage direct currentH), it is low
Straightening stream input voltage source (VL), first switch tube (S1), second switch (S2), third switching tube (S3), the 4th switching tube
(S4), the 5th switching tube (S5), the 6th switching tube (S6), first diode (D1), the second diode (D2), third diode
(D3), the 4th diode (D4), the 5th diode (D5), the 6th diode (D6), forward filtering inductance (LP), inverse filtering inductance
(LN), public filter inductance (Lf) and load (Z) composition.Wherein, the high voltage direct current inputs voltage source (VH) anode be connected in
One switching tube (S1) collector, the 6th diode (D6) cathode, the 5th diode (D5) cathode and second switch (S2)
Collector；First switch tube (S1) emitter be connected in first diode (D1) cathode and third switching tube (S3) current collection
Pole；Third switching tube (S3) emitter be connected in forward filtering inductance (LP) one end and third diode (D3) cathode；It is positive
Filter inductance (LP) the other end be connected in public filter inductance (Lf) one end, the 6th diode (D6) anode and the 6th switch
Manage (S6) collector；Public filter inductance (Lf) the other end be connected in one end of load (Z)；Second switch (S2) transmitting
Pole is connected in the second diode (D2) cathode and the 4th switching tube (S4) collector；4th switching tube (S4) emitter connect
In inverse filtering inductance (LN) one end and the 4th diode (D4) cathode；Inverse filtering inductance (LN) the other end be connected in
Five diode (D5) anode, the 5th switching tube (S5) collector and load (Z) the other end；Low-voltage direct input voltage source
(VL) anode be connected in first diode (D1) anode and the second diode (D2) anode；High voltage direct current inputs voltage source
(VH) cathode be connected in low-voltage direct input voltage source (VL) cathode, third diode (D3) anode, the 6th switching tube
(S6) emitter, the 5th switching tube (S5) emitter and the 4th diode (D4) anode.
Unipolarity based on the double Buck full-bridge inverters of dual input modulates acyclic flow control policy block diagram and the strategy lower pair
The key waveforms figure of the double Buck full-bridge inverters of input is respectively as shown in attached drawing 5 and attached drawing 6:
Sampled voltage vosWith voltage reference vrefCompare to obtain voltage error value.Voltage error value is adjusted by outer voltage
Device GVProcessing, exports as public filter inductance (Lf) current reference iLf_ref.Public filter inductance (Lf) electric current sampled value iLfs
With current reference iLf_refCompare to obtain current error value.Current error value passes through current inner loop adjuster GIProcessing exports to adjust
Wave v processedr.Here voltage regulator GVWith current regulator GIIt can be the common adjuster of any inverter, such as ratio-
Integral controller, proportional-integral-differential adjuster, ratio-resonant regulator etc..
Public filter inductance (Lf) current reference iLf_refCompared with 0, work as iLf_refWhen >=0, output signal IPFor logic
High level 1, output signal INFor logic low 0；Work as iLf_refWhen < 0, output signal INFor logic high 1, output signal
IPFor logic low 0.Modulation system is modulated using unipolarity.vTri1PAnd vTri2PBe positive triangular wave, vTri1NAnd vTri2NIt is negative three
Angle wave, vTri1PAnd vTri1NAmplitude is equal, is Δ vTri1。vTr2PAnd vTri2NAmplitude is equal, is Δ vTri2。ΔvTri1With Δ vTri2It is full
Foot:
Four triangular carriers are followed successively by v from top to bottomTri1P、vTri2P、vTri1NAnd vTri2N。vTri1PAnd vTri2PCut off value be
ΔvTri2, vTri2PAnd vTri1NCut off value be 0, vTri1NAnd vTri2NCut off value be-Δ vTri1。
In public filter inductance (Lf) current reference iLf_refWhen >=0, second switch (S2), the 4th switching tube (S4)
With the 6th switching tube (S6) be held off, first switch tube (S1), third switching tube (S3) and the 5th switching tube (S5) modulation work
Make:
Work as vr>=vTri1PWhen, first switch tube (S1), third switching tube (S3) and the 5th switching tube (S5) conducting, high pressure
DC input voitage source (VH) individually power to the load, bridge arm midpoint APAnd BPBetween voltage be VH, as shown in Fig. 15；
Work as vTri1P> vr>=vTri2PWhen, first diode (D1), third switching tube (S3) and the 5th switching tube (S5) lead
It is logical, low-voltage direct input voltage source (VL) individually to the positive power supply of load, bridge arm midpoint APAnd BPBetween voltage be VL, such as attached
Shown in Figure 16；
Work as vTri2P> vrWhen >=0, third diode (D3) and the 5th switching tube (S5) conducting, high voltage direct current input voltage
Source (VH), low-voltage direct input voltage source (VL) and load between noenergy transmitting, bridge arm midpoint APAnd BPBetween voltage be 0,
As shown in Fig. 17；
As 0 > vr>=vTri1NWhen, first switch tube (S1), third switching tube (S3) and the 5th diode (D5) conducting, it is high
Straightening stream input voltage source (VH), low-voltage direct input voltage source (VL) and load between noenergy transmitting, bridge arm midpoint APAnd BP
Between voltage be 0, as shown in Fig. 18；
Work as vTri1N> vr>=vTri2NWhen, first diode (D1), third switching tube (S3) and the 5th diode (D5) lead
It is logical, load and low-voltage direct input voltage source (VL) voltage source (V is inputted to high voltage direct current jointlyH) transmitting energy, bridge arm midpoint AP
And BPBetween voltage be VL-VH, as shown in Fig. 19；
Work as vTri2N> vrWhen, third diode (D3) and the 5th diode (D5) conducting, load is individually to high voltage direct current input
Voltage source (VH) feedback energy, bridge arm midpoint APAnd BPBetween voltage be-VH, as shown in Fig. 20.
In public filter inductance (Lf) current reference iLf_refWhen < 0, first switch tube (S1), third switching tube (S3) and
5th switching tube (S5) be held off, second switch (S2), the 4th switching tube (S4) and the 6th switching tube (S6) modulation work:
As (- vr) >=vTri1PWhen, second switch (S2), the 4th switching tube (S4) and the 6th switching tube (S6) conducting, it is high
Straightening stream input voltage source (VH) individually power to the load, bridge arm midpoint ANAnd BNBetween voltage be-VH, as shown in Fig. 21；
Work as vTri1P> (- vr) >=vTri2PWhen, the second diode (D2), the 4th switching tube (S4) and the 6th switching tube (S6)
Conducting, low-voltage direct input voltage source (VL) individually power to the load, bridge arm midpoint ANAnd BNBetween voltage be-VL, such as attached drawing
Shown in 22；
Work as vTri2P> (- vr) >=0 when, the 4th diode (D4) and the 6th switching tube (S6) conducting, high voltage direct current input electricity
Potential source (VH), low-voltage direct input voltage source (VL) and load between noenergy transmitting, bridge arm midpoint ANAnd BNBetween voltage be
0, as shown in Fig. 23；
As 0 > (- vr) >=vTri1NWhen, second switch (S2), the 4th switching tube (S4) and the 6th diode (D6) lead
Logical, high voltage direct current inputs voltage source (VH), low-voltage direct input voltage source (VL) and load between noenergy transmitting, bridge arm midpoint
ANAnd BNBetween voltage be 0, as shown in Fig. 24；
Work as vTri1N> (- vr) >=vTri2NWhen, the second diode (D2), the 4th switching tube (S4) and the 6th diode (D6)
Conducting, load and low-voltage direct input voltage source (VL) voltage source (V is inputted to high voltage direct current jointlyH) transmitting energy, bridge arm midpoint
ANAnd BNBetween voltage be VH-VL, as shown in Fig. 25；
Work as vTri2N> (- vr) when, the 4th diode (D4) and the 6th diode (D6) conducting, it loads individually to high voltage direct current
Input voltage source (VH) feedback energy, bridge arm midpoint ANAnd BNBetween voltage be VH, as shown in Fig. 26.
Above-mentioned high voltage direct current inputs voltage source (VH) voltage must be not less than low-voltage direct input voltage source (VL) electricity
Pressure.
As can be seen from the above analysis, the double Buck full-bridge inverters of dual input proposed by the present invention and its unipolarity modulate nothing
Circulation control strategy, the double Buck full-bridge inverters of dual input can be realized under unipolarity modulation determines frequency non-loop operation, simplifies
Filter design, the efficiency for improving inverter；It can produce plurality of level and act on filter circuit, switch can be effectively reduced
Loss and harmonic component, and then improve inverter efficiency and reduce the volume and weight of filter.
Claims (3)
1. the unipolarity of double Buck full-bridge inverters modulates acyclic flow control policy, it is characterised in that:
Double Buck full-bridge inverters are by input voltage source (Vin), first switch tube (S1), second switch (S2), third switching tube
(S3), the 4th switching tube (S4), first diode (D1), the second diode (D2), third diode (D3), the 4th diode
(D4), forward filtering inductance (LP), inverse filtering inductance (LN), public filter inductance (Lf) and load (Z) composition.Wherein, direct current
Input voltage source (Vin) anode be connected in first switch tube (S1) collector, second switch (S2) collector, the three or two
Pole pipe (D3) cathode and the 4th diode (D4) cathode；First switch tube (S1) emitter be connected in forward filtering inductance
(LP) one end and first diode (D1) cathode；Forward filtering inductance (LP) the other end be connected in third diode (D3)
Anode, public filter inductance (Lf) one end and third switching tube (S3) collector；Public filter inductance (Lf) the other end connect
In one end of load (Z)；Second switch (S2) emitter be connected in inverse filtering inductance (LN) one end and the second diode
(D2) cathode；Inverse filtering inductance (LN) the other end be connected in the 4th diode (D4) anode, the 4th switching tube (S4) collection
The other end of electrode and load (Z)；Input voltage (Vin) cathode be connected in first diode (D1) anode, third switching tube
(S3) emitter, the 4th switching tube (S4) emitter and the second diode (D2) anode.
Its control system is made of outer voltage and current inner loop.Sampled voltage vosWith voltage reference vrefCompare to obtain voltage mistake
Difference.Voltage error value passes through outer voltage adjuster GVProcessing, exports as public filter inductance (Lf) current reference iLf_ref。
Public filter inductance (Lf) electric current sampled value iLfsWith current reference iLf_refCompare to obtain current error value.Current error value warp
Overcurrent inner ring adjuster GIProcessing, exports as modulating wave vr.Here voltage regulator GVWith current regulator GIIt can be and appoint
What common adjuster of inverter, such as proportional-integral controller, proportional-integral-differential adjuster, ratio-resonant regulator
Deng.
Public filter inductance (Lf) current reference iLf_refCompared with 0, work as iLf_refWhen >=0, output signal IPFor logically high electricity
Flat 1, output signal INFor logic low 0；Work as iLf_refWhen < 0, output signal INFor logic high 1, output signal IPFor
Logic low 0.Modulation system is modulated using unipolarity.vTriPBe positive triangular wave, vTriNBe negative triangular wave, and the two amplitude is equal.
In public filter inductance (Lf) current reference iLf_refWhen >=0, second switch (S2) and third switching tube (S3) protect
Hold shutdown, first switch tube (S1) and the 4th switching tube (S4) modulation work:
Work as vr>=vTriPWhen, first switch tube (S1) and the 4th switching tube (S4) conducting, bridge arm midpoint APAnd BPBetween voltage
For Vin；
Work as vTriP> vrWhen >=0, the 4th switching tube (S4) and first diode (D1) conducting, bridge arm midpoint APAnd BPBetween electricity
Pressure is 0；
As 0 > vr>=vTriNWhen, first switch tube (S1) and the 4th diode (D4) conducting, bridge arm midpoint APAnd BPBetween electricity
Pressure is 0；
Work as vTriN> vrWhen, first switch tube (S1) be connected and the 4th switching tube (S4) be not turned on, first diode (D1) and the
Four diode (D4) conducting, bridge arm midpoint APAnd BPBetween voltage be-Vin。
In public filter inductance (Lf) current reference iLf_refWhen > 0, first switch tube (S1) and the 4th switching tube (S4) keep
Shutdown, second switch (S2) and third switching tube (S3) modulation work:
Work as vr>=vTriPWhen, second switch (S2) and third switching tube (S3) be not turned on, the second diode (D2) and third
Diode (D3) conducting, bridge arm midpoint ANAnd BNBetween voltage be Vin；
Work as vTriP> vrWhen >=0, second switch (S2) and third diode (D3) conducting, bridge arm midpoint ANAnd BNBetween electricity
Pressure is 0；
As 0 > vr>=vTriNWhen, third switching tube (S3) and the second diode (D2) conducting, bridge arm midpoint ANAnd BNBetween electricity
Pressure is 0；
Work as vTriN> vrWhen, second switch (S2) and third switching tube (S3) conducting, bridge arm midpoint ANAnd BNBetween voltage be-
Vin。
2. a kind of double Buck full-bridge inverters of dual input input voltage source (V by high voltage direct currentH), low-voltage direct input voltage
Source (VL), first switch tube (S1), second switch (S2), third switching tube (S3), the 4th switching tube (S4), the 5th switching tube
(S5), the 6th switching tube (S6), first diode (D1), the second diode (D2), third diode (D3), the 4th diode
(D4), the 5th diode (D5), the 6th diode (D6), forward filtering inductance (LP), inverse filtering inductance (LN), public filtered electrical
Feel (Lf) and load (Z) composition.Wherein, the high voltage direct current inputs voltage source (VH) anode be connected in first switch tube (S1)
Collector, the 6th diode (D6) cathode, the 5th diode (D5) cathode and second switch (S2) collector；First
Switching tube (S1) emitter be connected in first diode (D1) cathode and third switching tube (S3) collector；Third switching tube
(S3) emitter be connected in forward filtering inductance (LP) one end and third diode (D3) cathode；Forward filtering inductance (LP)
The other end be connected in public filter inductance (Lf) one end, the 6th diode (D6) anode and the 6th switching tube (S6) current collection
Pole；Public filter inductance (Lf) the other end be connected in one end of load (Z)；Second switch (S2) emitter be connected in second
Diode (D2) cathode and the 4th switching tube (S4) collector；4th switching tube (S4) emitter be connected in inverse filtering electricity
Feel (LN) one end and the 4th diode (D4) cathode；Inverse filtering inductance (LN) the other end be connected in the 5th diode (D5)
Anode, the 5th switching tube (S5) collector and load (Z) the other end；Low-voltage direct input voltage source (VL) anode even
In first diode (D1) anode and the second diode (D2) anode；High voltage direct current inputs voltage source (VH) cathode be connected
In low-voltage direct input voltage source (VL) cathode, third diode (D3) anode, the 6th switching tube (S6) emitter,
Five switching tube (S5) emitter and the 4th diode (D4) anode.
3. the unipolarity of the double Buck full-bridge inverters of the dual input based on claim 2 modulates acyclic flow control policy, feature
It is:
Sampled voltage vosWith voltage reference vrefCompare to obtain voltage error value.Voltage error value passes through outer voltage adjuster GV
Processing, exports as public filter inductance (Lf) current reference iLf_ref.Public filter inductance (Lf) electric current sampled value iLfsWith electricity
Flow benchmark iLf_refCompare to obtain current error value.Current error value passes through current inner loop adjuster GIProcessing, exports as modulating wave
vr.Here voltage regulator GVWith current regulator GIIt can be the common adjuster of any inverter, such as proportional, integral
Adjuster, proportional-integral-differential adjuster, ratio-resonant regulator etc..
Public filter inductance (Lf) current reference iLf_refCompared with 0, work as iLf_refWhen >=0, output signal IPFor logically high electricity
Flat 1, output signal INFor logic low 0；Work as fLf_refWhen < 0, output signal INFor logic high 1, output signal IPFor
Logic low 0.Modulation system is modulated using unipolarity.vTri1PAnd vTri2PBe positive triangular wave, vTri1NAnd vTri2NBe negative triangle
Wave, vTri1PAnd vTri1NAmplitude is equal, is Δ vTri1。vTr2PAnd vTri2NAmplitude is equal, is Δ vTri2。ΔvTri1With Δ vTri2Meet:
Four triangular carriers are followed successively by v from top to bottomTri1P、vTri2P、vTri1NAnd vTri2N。vTri1PAnd vTri2PCut off value be Δ
vTri2, vTri2PAnd vTri1NCut off value be 0, vTri1NAnd vTri2NCut off value be-Δ vTri1。
In public filter inductance (Lf) current reference fLf_refWhen >=0, second switch (S2), the 4th switching tube (S4) and the
Six switching tube (S6) be held off, first switch tube (S1), third switching tube (S3) and the 5th switching tube (S5) modulation work:
Work as vr>=vTri1PWhen, first switch tube (S1), third switching tube (S3) and the 5th switching tube (S5) conducting, bridge arm midpoint AP
And BPBetween voltage be VH；
Work as vTri1P> vr>=vTri2PWhen, first diode (D1), third switching tube (S3) and the 5th switching tube (S5) conducting, bridge
Arm midpoint APAnd BPBetween voltage be VL；
Work as vTri2P> vrWhen >=0, third diode (D3) and the 5th switching tube (S5) conducting, bridge arm midpoint APAnd BPBetween electricity
Pressure is 0；
As 0 > vr>=vTri1NWhen, first switch tube (S1), third switching tube (S3) and the 5th diode (D5) be connected, in bridge arm
Point APAnd BPBetween voltage be 0；
Work as vTri1N> vr>=vTri2NWhen, first diode (D1), third switching tube (S3) and the 5th diode (D5) conducting, bridge
Arm midpoint APAnd BPBetween voltage be VL-VH；
Work as vTri2N> vrWhen, third diode (D3) and the 5th diode (D5) conducting, bridge arm midpoint APAnd BPBetween voltage be-
VH。
In public filter inductance (Lf) current reference iLf_refWhen < 0, first switch tube (S1), third switching tube (S3) and the 5th
Switching tube (S5) be held off, second switch (S2), the 4th switching tube (S4) and the 6th switching tube (S6) modulation work:
As (- vr) >=vTri1PWhen, second switch (S2), the 4th switching tube (S4) and the 6th switching tube (S6) be connected, in bridge arm
Point ANAnd BNBetween voltage be-VH；
Work as vTri1P> (- vr) >=vTri2PWhen, the second diode (D2), the 4th switching tube (S4) and the 6th switching tube (S6) conducting,
Bridge arm midpoint ANAnd BNBetween voltage be-VL；
Work as vTri2P> (- vr) >=0 when, the 4th diode (D4) and the 6th switching tube (S6) conducting, bridge arm midpoint ANAnd BNBetween
Voltage be 0；
As 0 > (- vr) >=vTri1NWhen, second switch (S2), the 4th switching tube (S4) and the 6th diode (D6) conducting, bridge
Arm midpoint ANAnd BNBetween voltage be 0；
Work as vTri1N> (- vr) >=vTri2NWhen, the second diode (D2), the 4th switching tube (S4) and the 6th diode (D6) conducting,
Bridge arm midpoint ANAnd BNBetween voltage be VH-VL；
Work as vTri2N> (- vr) when, the 4th diode (D4) and the 6th diode (D6) conducting, bridge arm midpoint ANAnd BNBetween voltage
For VH。
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