CN110164893A - 3D stack cmos image sensor and preparation method thereof - Google Patents
3D stack cmos image sensor and preparation method thereof Download PDFInfo
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- CN110164893A CN110164893A CN201910440475.5A CN201910440475A CN110164893A CN 110164893 A CN110164893 A CN 110164893A CN 201910440475 A CN201910440475 A CN 201910440475A CN 110164893 A CN110164893 A CN 110164893A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000012774 insulation material Substances 0.000 claims abstract description 97
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- 230000005855 radiation Effects 0.000 claims description 73
- 239000000758 substrate Substances 0.000 claims description 56
- 229910052710 silicon Inorganic materials 0.000 claims description 46
- 239000010703 silicon Substances 0.000 claims description 46
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 149
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 37
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
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- 239000010949 copper Substances 0.000 description 11
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 11
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 239000004411 aluminium Substances 0.000 description 10
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract
The present invention provides a kind of 3D stack cmos image sensor and preparation method thereof, and 3D stack cmos image sensor includes: logic wafer；Pixel wafer is bonded on logic wafer；Insulation material layer between logic wafer and pixel wafer, and covers the surface of pixel wafer；The heat that insulation material layer is used to that logic wafer to be prevented to generate is transmitted to pixel wafer.The present invention is by adding insulation material layer between pixel wafer and logic wafer, the heat that logic wafer can be prevented to generate is transmitted to pixel wafer, reduce the dark current on pixel wafer, to reduce the noise of 3D stack cmos image sensor, the performance of 3D stack cmos image sensor is improved.
Description
Technical field
The invention belongs to microelectronics technologies, more particularly to a kind of 3D stack cmos image sensor and its preparation
Method.
Background technique
Continuous pursuit with people to high quality image, 3D stack cmos image sensor are developed；3D heap
Stacked cmos image sensor layers of copper includes logic wafer and the pixel wafer that is bonded on logic wafer.Compared to traditional
Cmos image sensor (including cmos image sensor front-illuminated or back-illuminated cmos image sensors), 3D stack CMOS figure
As sensor has many advantages, such as smaller chip structure and faster processing speed.
However, existing 3D stack cmos image sensor is by pixel wafer direct bonding in the logic wafer
On, the heat that the logic chip generates when working can be transferred to the pixel wafer, and dark electricity is generated on the pixel wafer
It flows (generating white pixel on the pixel wafer), so that the 3D stack cmos image sensor generates noise, in institute
It states and generates spot on the screen of 3D stack cmos image sensor, influence the property of the 3D stack cmos image sensor
Energy.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of 3D stack cmos image biographies
Sensor and preparation method thereof is by pixel wafer direct key for solving 3D stack cmos image sensor in the prior art
Together on logic wafer and existing logic chip work when the heat that generates can be transferred to pixel wafer, in the pixel wafer
Upper generation dark current, so that 3D stack cmos image sensor generates noise, in the screen of 3D stack cmos image sensor
The problem of generating spot on curtain, influence the performance of 3D stack cmos image sensor.
In order to achieve the above objects and other related objects, the present invention provides a kind of 3D stack cmos image sensor, institute
Stating 3D stack cmos image sensor includes:
Logic wafer；
Pixel wafer is bonded on the logic wafer；
Insulation material layer between the logic wafer and the pixel wafer, and covers the table of the pixel wafer
Face；The heat that the insulation material layer is used to that the logic wafer to be prevented to generate is transmitted to the pixel wafer.
Optionally, the 3D stack cmos image sensor further includes heat radiation material layer, and the heat radiation material layer is located at
Between the insulation material layer and the logic wafer.
Optionally, the heat radiation material layer covers the part of the surface of the insulation material layer；The 3D stack CMOS figure
As sensor further includes bonding medium layer, the bonding medium layer is located at the logic wafer and the insulation material layer and described
Between heat radiation material layer.
Optionally, the insulation material layer includes low-k dielectric layers, and the heat radiation material layer includes metal layer；The 3D heap
Stacked cmos image sensor further includes metal adhesion layer, the metal adhesion layer be located at the heat radiation material layer with it is described heat-insulated
Between material layer.
Optionally, the logic wafer includes the first substrate, first medium layer and the first metal line layer；The first medium
Layer is located at the surface of first substrate, and first metal line layer is located in the first medium layer；
For the pixel wafer bonding on the first medium layer, the pixel wafer includes the second substrate, second medium
Layer and the second metal line layer；The second dielectric layer is located at the surface of second substrate, and is located at second substrate and institute
It states between first medium layer；Second metal line layer is located in the second dielectric layer；
The insulation material layer and the heat radiation material layer be respectively positioned on the first medium layer and the second dielectric layer it
Between.
Optionally, the 3D stack cmos image sensor further includes silicon through hole interconnection structure, the interconnecting silicon through holes
Structure through the pixel wafer, second metal line layer and the insulation material layer until first metal line layer, with
First metal line layer and second metal line layer are electrically connected；The silicon through hole interconnection structure and the heat radiation material layer
Between have gap.
Optionally, the 3D stack cmos image sensor further includes weld pad, and the weld pad is located at the second medium
Side of the layer far from the insulation material layer, and be electrically connected with second metal line layer.
Optionally, photodiode is formed in the pixel wafer.
Optionally, the logic wafer includes active area devices region and passive device region；The active area device region
Active device is formed in domain, the active device is electrically connected with first metal line layer；Shape in the passive device region
At there is passive device；The heat radiation material layer at least covers the active area device area and the passive device region.
The present invention also provides a kind of preparation method of 3D stack cmos image sensor, the 3D stack cmos image
The preparation method of sensor includes the following steps:
Pixel wafer is provided；
Insulation material layer is formed in the surface of the pixel wafer, the insulation material layer covers the table of the pixel wafer
Face；
Logic wafer is provided；
The pixel wafer bonding of the insulation material layer will be formed on the logic wafer；It is described after bonding
Insulation material layer is between the pixel wafer and the logic wafer.
Optionally, the surface of Yu Suoshu pixel wafer formed after the insulation material layer and provide the logic wafer it
Before further include following steps: Yu Suoshu insulation material layer far from the pixel wafer surface formed heat radiation material layer；The picture
For plain wafer bonding after on the logic wafer, the insulation material layer and the heat radiation material layer are respectively positioned on the pixel crystalline substance
It is round between the logic wafer.
Optionally, the heat radiation material layer covers the part of the surface of the insulation material layer；The heat-insulated material will be formed with
The bed of material and the pixel wafer bonding of the heat radiation material layer further include in the heat dissipation material before on the logic wafer
The step of surface of the bed of material and the surface of the exposed insulation material layer form bonding medium layer, the pixel wafer is via institute
Bonding medium layer is stated to be bonded on the logic wafer.
Optionally, the insulation material layer includes low-k dielectric layers, and the heat radiation material layer includes metal layer；In it is described every
It further includes remote in the insulation material layer that hot material layer is formed before the heat radiation material layer far from the surface of the pixel wafer
The step of surface from the pixel wafer forms metal adhesion layer, it is remote that the heat radiation material layer is formed in the metal adhesion layer
Surface from the insulation material layer.
Optionally, the logic wafer includes the first substrate, first medium layer and the first metal line layer；The first medium
Layer is located at the surface of first substrate, and first metal line layer is located in the first medium layer；
For the pixel wafer bonding on the first medium layer, the pixel wafer includes the second substrate, second medium
Layer and the second metal line layer；The second dielectric layer is located at the surface of second substrate, and is located at second substrate and institute
It states between first medium layer；Second metal line layer is located in the second dielectric layer；
The insulation material layer and the heat radiation material layer be respectively positioned on the first medium layer and the second dielectric layer it
Between.
Optionally, the pixel wafer bonding of the insulation material layer and the heat radiation material layer will be formed in described
Further include following steps after on logic wafer:
Through silicon via is formed, the through silicon via runs through the pixel wafer, second metal line layer and the heat-barrier material
Layer, and expose first metal line layer；There is gap between the through silicon via and the heat radiation material layer；
In forming silicon through hole interconnection structure in the through silicon via.
Optionally, forming the silicon through hole interconnection structure further includes later following steps:
Opening is formed far from the surface of the logic wafer in the pixel wafer, the opening exposes second gold medal
Belong to line layer；
In forming weld pad in the opening.
As described above, 3D stack cmos image sensor and preparation method thereof of the invention has the advantages that
The present invention can prevent logic wafer from generating by adding insulation material layer between pixel wafer and logic wafer
Heat to pixel wafer transmit, reduce pixel wafer on dark current, to reduce 3D stack cmos image sensor
Noise improves the performance of 3D stack cmos image sensor；
The present invention between insulation material layer and logic wafer by adding heat radiation material layer, the heat that logic wafer generates
Heat can be avoided in 3D stack CMOS along heat radiation material layer Quick diffusing to the outside of 3D stack cmos image sensor
It is accumulative in imaging sensor, improve performance and the service life of 3D stack cmos image sensor.
Detailed description of the invention
Fig. 1 is shown as the process of the preparation method of the 3D stack cmos image sensor provided in the embodiment of the present invention one
Figure.
Fig. 2 to Figure 11 is shown as the preparation method of the 3D stack cmos image sensor provided in the embodiment of the present invention one
In each step resulting structures cross section structure schematic diagram；Wherein, Figure 11 is shown as the 3D provided in the embodiment of the present invention two stacking
The cross section structure schematic diagram of formula cmos image sensor.
Component label instructions
1 pixel wafer
11 second substrates
12 second dielectric layer
13 second metal line layers
14 photodiodes
2 logic wafers
21 first substrates
22 first medium layers
23 first metal line layers
24 active area device areas
25 passive device regions
26 active devices
27 passive devices
3 insulation material layers
4 heat radiation material layers
5 bonding medium layers
6 through silicon vias
7 silicon through hole interconnection structure
8 openings
9 weld pads
Specific embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed by book is understood other advantages and efficacy of the present invention easily.
Fig. 1 is please referred to Figure 11.It should be clear that this specification structure depicted in this specification institute accompanying drawings, ratio, size etc., are only used
To cooperate the revealed content of specification, so that those skilled in the art understands and reads, being not intended to limit the invention can
The qualifications of implementation, therefore do not have technical essential meaning, the tune of the modification of any structure, the change of proportionate relationship or size
It is whole, in the case where not influencing the effect of present invention can be generated and the purpose that can reach, it should all still fall in disclosed skill
Art content obtains in the range of capable of covering.Meanwhile in this specification it is cited as "upper", "lower", "left", "right", " centre " and
The term of " one " etc. is merely convenient to being illustrated for narration, rather than to limit the scope of the invention, relativeness
It is altered or modified, under the content of no substantial changes in technology, when being also considered as the enforceable scope of the present invention.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of 3D stack cmos image sensor, the 3D stack
The preparation method of cmos image sensor includes the following steps:
1) pixel wafer is provided；
2) surface of Yu Suoshu pixel wafer forms insulation material layer, and the insulation material layer covers the pixel wafer
Surface；
3) logic wafer is provided；
4) the pixel wafer bonding of the insulation material layer and the heat radiation material layer will be formed in the logic
On wafer；After bonding, the insulation material layer and the heat radiation material layer be located at the pixel wafer and the logic wafer it
Between.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, pixel wafer 1 is provided.
As an example, the pixel wafer 1 may include the second substrate 11, second dielectric layer 12 and the second metal line layer
13；The second dielectric layer 12 is located at the surface of second substrate 11；Second metal line layer 13 is located at described second and is situated between
In matter layer 12.
As an example, second substrate 11 may include but be not limited only to silicon substrate, gallium nitride substrate or sapphire lining
Bottom etc..
As an example, several the first fleet plough groove isolation structure (not shown) are formed in second substrate 11, it is several
Second substrate 11 is isolated into several the first active areas by a first fleet plough groove isolation structure.
As an example, being formed with photodiode 14 (PD) in the pixel wafer 1, the photodiode 14 is located at institute
State the first active area；The grid of the photodiode 14 is located at the surface of second substrate 11, and the second dielectric layer
The grid of the 13 covering photodiodes 14.Specifically, the pixel wafer 1 includes pixel region (not shown), the light
Electric diode 14 is located in the pixel region；The region that i.e. photodiode 14 is distributed as shown in Figure 2 is institute
State pixel region.
As an example, the second dielectric layer 12 may include but be not limited only to silicon oxide layer, silicon nitride layer or nitrogen oxidation
Silicon layer etc..
As an example, the material of second metal line layer 13 may include in copper, aluminium, gold, silver, titanium, tin and nickel etc.
At least one.
In step 2), S2 step and Fig. 3 in Fig. 1 are please referred to, the surface of Yu Suoshu pixel wafer 1 forms heat-barrier material
Layer 3, the insulation material layer 3 covers the surface of the pixel wafer 1.
As an example, the heat-insulated material can be formed far from the surface of second substrate 11 in the second dielectric layer 12
The bed of material 3；Specifically, physical gas-phase deposition, chemical vapor deposition process or atomic layer deposition can be used but be not limited only to
Technique etc. forms the insulation material layer 3.
As an example, the insulation material layer 3 covers the second dielectric layer 12 far from the entire of second substrate 11
Surface.
As an example, the insulation material layer 3 can be any one material layer with preferable heat insulation, preferably
Ground, the insulation material layer 3 may include low-k dielectric layers；Specifically, the insulation material layer 3 may include dielectric constant k small
In 2.8 material layer.
As an example, referring to Fig. 4, further including after the surface of the pixel wafer 1 forms the insulation material layer 3
Following steps: Yu Suoshu insulation material layer 3 forms heat radiation material layer 4 far from the surface of the pixel wafer 1.
As an example, physical gas-phase deposition, chemical vapor deposition process or atom layer deposition process shape can be used
At the heat radiation material layer 4.The heat radiation material layer 4 can only cover the insulation material layer 3 far from the pixel wafer 1
Part of the surface.
As an example, the heat radiation material layer 4 may include the good material layer of any one heating conduction；Preferably,
The heat radiation material layer 4 may include metal layer；Specifically, the material of the heat radiation material layer 4 may include aluminium, tungsten, copper,
At least one of gold, silver, titanium and tin etc..
It should be noted that after step 2) and forming the heat sink material when the heat radiation material layer 4 is metal layer
It further include forming metal adhesion layer (not shown) far from the surface of the pixel wafer 1 in the insulation material layer 3 before layer 4
Step, at this point, the heat radiation material layer 4 is formed in surface of the metal adhesion layer far from the insulation material layer 3.Specifically
, the metal adhesion layer may include but be not limited only to TEOS (ethyl orthosilicate) layer.
As an example, further including in the surface of the heat radiation material layer 4 and exposed after forming the heat radiation material layer 4
The surface of the insulation material layer 3 forms the step of bonding medium layer 5, as shown in Figure 5；Specifically, can use but not only limit
The bonding medium layer 5 is formed in physical gas-phase deposition, chemical vapor deposition process or atom layer deposition process etc.；It is described
Bonding medium layer 5 may include but be not limited only to silicon oxide layer, silicon nitride layer or silicon oxynitride layer etc..
In step 3), S3 step and Fig. 6 in Fig. 1 are please referred to, logic wafer 2 is provided.
As an example, the logic wafer 2 may include the first substrate 21, first medium layer 22 and the first metal line layer
23；The first medium layer 22 is located at the surface of first substrate 21, and first metal line layer 23 is located at described first and is situated between
In matter layer 22.
As an example, first substrate 21 may include but be not limited only to silicon substrate, gallium nitride substrate or sapphire lining
Bottom etc..
As an example, several the second fleet plough groove isolation structure (not shown) are formed in first substrate 21, it is several
First substrate 21 is isolated into several the second active areas by a second fleet plough groove isolation structure.
As an example, the first medium layer 22 may include but be not limited only to silicon oxide layer, silicon nitride layer or nitrogen oxidation
Silicon layer etc..
As an example, the material of first metal line layer 13 may include in copper, aluminium, gold, silver, titanium, tin and nickel etc.
At least one.
As an example, the logic wafer 2 may include active area device area 24 and passive device region 25；It is described to have
Active device 26 is formed in active area devices region 24, the active device 26 is electrically connected with first metal line layer 23；Institute
It states and is formed with passive device 27 in passive device region 25；Specifically, the active device 26 may include but be not limited only to
At least one of NMOS device or PMOS device.
In step 4), S4 step and Fig. 7 in Fig. 1 are please referred to, the insulation material layer 3 and the heat dissipation will be formed with
The pixel wafer 1 of material layer 4 is bonded on the logic wafer 2；After bonding, the insulation material layer 3 and the heat dissipation
Material layer 4 is between the pixel wafer 1 and the logic wafer 2.
As an example, being formed with the institute of the insulation material layer 3 and the heat radiation material layer 4 in step 4) resulting structures
Pixel wafer 1 is stated to be bonded on the logic wafer 2 via the bonding medium layer 5；Specifically, being formed with the heat-barrier material
Layer 3 and the pixel wafer 1 of the heat radiation material layer 4 are bonded to the first medium layer 22 via the bonding medium layer 5
On surface far from first substrate 21；At this point, the insulation material layer 3 and the heat radiation material layer 4 are respectively positioned on described
Between one dielectric layer 22 and the second dielectric layer 12.
As an example, in the resulting bonding structure of step 4), first metal line layer 23 and second metal line layer
13 at least top and the bottom are overlapped；I.e. described first metal line layer 23 the 13 place plane of the second metal line layer orthographic projection extremely
It is few to coincide with part second metal line layer 13.
As an example, the heat radiation material layer 4 at least covers the active device region in the resulting bonding structure of step 4)
Domain 24 and the passive device region 25.
As an example, the pixel region in the pixel wafer 1 is located at described in the resulting bonding structure of step 4)
The surface of the active device area 24 and the passive device region 25 in logic wafer 2.
Further include following steps after step 5) as an example, please referring to Fig. 8 and Fig. 9:
5) formed through silicon via (Through Silicon Via, TSV) 6, the through silicon via 6 through the pixel wafer 1,
Second metal line layer 13 and the insulation material layer 3, and expose first metal line layer 23；The through silicon via 3 with
There is gap, as shown in Figure 8 between the heat radiation material layer 4；
6) silicon through hole interconnection structure 7 is formed in Yu Suoshu through silicon via 6, as shown in Figure 8.
As an example, the through silicon via 6 can be formed using lithographic etch process；The shape of the through silicon via 6 can root
It is configured according to actual needs, herein without limitation.
As an example, depositing operation can be used logical to form the silicon in filling conductive material layer in the through silicon via 6
First metal line layer 23 and second metal line layer 13 are electrically connected by hole interconnection structure 7, the silicon through hole interconnection structure 7
It connects.The material of the silicon through hole interconnection structure 7 may include but be not limited only to copper, aluminium, gold, silver, titanium, tin and nickel etc. in extremely
Few one kind.
Further include following steps after step 7) as an example, please referring to Figure 10 and Figure 11:
7) Yu Suoshu pixel wafer 1 forms opening 8 far from the surface of the logic wafer 2, and the opening 8 exposes described
Second metal line layer 13, as shown in Figure 10；
8) in forming weld pad 9 in the opening 8, as shown in figure 11.
As an example, the opening 8 can be formed using lithographic etch process；The shape of the opening 8 can be according to reality
Border needs to be configured, herein without limitation.
As an example, depositing operation can be used in filling conductive material layer in the opening 8 to form the weld pad 9,
The material of the weld pad 9 at least one of may include but be not limited only to copper, aluminium, gold, silver, titanium, tin and nickel etc..
As an example, the weld pad 9 can fill up the opening 8, it can also be with the unfilled opening 8.
First on the surface of the pixel wafer 1 in the preparation method of 3D stack cmos image sensor of the present invention
Form the insulation material layer 3 stacked, then by surface be formed with the pixel wafer 1 of the insulation material layer 3 with it is described
Logic wafer 2 is bonded together, and the insulation material layer 3 added between the pixel wafer 1 and the logic wafer 2 can
It is transmitted with the heat for preventing the logic wafer 2 from generating to the pixel wafer 1, reduces the dark current on the pixel wafer 1,
To reduce the noise of the 3D stack cmos image sensor, the property of the 3D stack cmos image sensor is improved
Energy；The heat radiation material layer 4 added between the insulation material layer 3 and logic wafer 2 can make the logic wafer 2
The heat of generation, to the outside of the 3D stack cmos image sensor, avoids heat along 4 Quick diffusing of heat radiation material layer
Amount is accumulative in the 3D stack cmos image sensor, and the property of the 3D stack cmos image sensor can be improved
Energy and service life.
Embodiment two
Please continue to refer to Figure 11, the present invention also provides a kind of 3D stack cmos image sensor, the 3D stack
Cmos image sensor includes: logic wafer 2；Pixel wafer 1, the pixel wafer 1 are bonded on the logic wafer 2；Every
Hot material layer 3, the insulation material layer 3 is between the logic wafer 2 and the pixel wafer 1, and the heat-barrier material
The surface of the 3 covering pixel wafer 1 of layer；The insulation material layer 3 is used to prevent the heat of the generation of logic wafer 2 to institute
State the transmitting of pixel wafer 1.
As an example, the 3D stack cmos image sensor further includes heat radiation material layer 4, the heat radiation material layer 4
Between the insulation material layer 3 and the logic wafer 2.
As an example, the logic wafer 2 may include the first substrate 21, first medium layer 22 and the first metal line layer
23；The first medium layer 22 is located at the surface of first substrate 21, and first metal line layer 23 is located at described first and is situated between
In matter layer 22.The pixel wafer 1 is bonded on the first medium layer 22.
As an example, first substrate 21 may include but be not limited only to silicon substrate, gallium nitride substrate or sapphire lining
Bottom etc..
As an example, several the second fleet plough groove isolation structure (not shown) are formed in first substrate 21, it is several
First substrate 21 is isolated into several the second active areas by a second fleet plough groove isolation structure.
As an example, the first medium layer 22 may include but be not limited only to silicon oxide layer, silicon nitride layer or nitrogen oxidation
Silicon layer etc..
As an example, the material of first metal line layer 13 may include in copper, aluminium, gold, silver, titanium, tin and nickel etc.
At least one.
As an example, the logic wafer 2 may include active area device area 24 and passive device region 25；It is described to have
Active device 26 is formed in active area devices region 24, the active device 26 is electrically connected with first metal line layer 23；Institute
It states and is formed with passive device 27 in passive device region 25；Specifically, the active device 26 may include but be not limited only to
At least one of NMOS device or PMOS device.
As an example, the pixel wafer 1 may include the second substrate 11, second dielectric layer 12 and the second metal line layer
13；The second dielectric layer 12 is located at the surface of second substrate 11；Second metal line layer 13 is located at described second and is situated between
In matter layer 12.
As an example, second substrate 11 may include but be not limited only to silicon substrate, gallium nitride substrate or sapphire lining
Bottom etc..
As an example, several the first fleet plough groove isolation structure (not shown) are formed in second substrate 11, it is several
Second substrate 11 is isolated into several the first active areas by a first fleet plough groove isolation structure.
As an example, being formed with photodiode 14 (PD) in the pixel wafer 1, the photodiode 14 is located at institute
State the first active area；The grid of the photodiode 14 is located at the surface of second substrate 11, and the second dielectric layer
The grid of the 13 covering photodiodes 14.Specifically, the pixel wafer 1 includes pixel region (not shown), the light
Electric diode 14 is located in the pixel region；The region that the photodiode 14 i.e. as shown in Figure 11 is distributed is institute
State pixel region.
As an example, the second dielectric layer 12 may include but be not limited only to silicon oxide layer, silicon nitride layer or nitrogen oxidation
Silicon layer etc..
As an example, the material of second metal line layer 13 may include in copper, aluminium, gold, silver, titanium, tin and nickel etc.
At least one.
As an example, the insulation material layer 3 covers the second dielectric layer 12 far from the entire of second substrate 11
Surface.
As an example, the insulation material layer 3 can be any one material layer with preferable heat insulation, preferably
Ground, the insulation material layer 3 may include low-k dielectric layers；Specifically, the insulation material layer 3 may include dielectric constant k small
In 2.8 material layer.
As an example, the insulation material layer 3 and the heat radiation material layer 4 be respectively positioned on the first medium layer 22 with it is described
Between second dielectric layer 12.
As an example, the heat radiation material layer 4 may include the good material layer of any one heating conduction；Preferably,
The heat radiation material layer 4 may include metal layer；Specifically, the material of the heat radiation material layer 4 may include aluminium, tungsten, copper,
At least one of gold, silver, titanium and tin etc..
It should be noted that the 3D stack cmos image sensor is also when the heat radiation material layer 4 is metal layer
Including metal adhesion layer (not shown), the metal adhesion layer be located at the heat radiation material layer 3 and the insulation material layer 4 it
Between.Specifically, the metal adhesion layer may include but be not limited only to TEOS (ethyl orthosilicate) layer.
As an example, the heat radiation material layer 4 covers the part of the surface of the insulation material layer 3；The 3D stack
Cmos image sensor further includes bonding medium layer 5, and the bonding medium layer 5 is located at the logic wafer 2 and the heat-insulated material
Between the bed of material 3 and the heat radiation material layer 4.
As an example, the bonding medium layer 5 may include but be not limited only to silicon oxide layer, silicon nitride layer or silicon oxynitride
Layer etc..
As an example, first metal line layer 23 is Chong Die at least top and the bottom of the second metal line layer 13；That is institute
State the first metal line layer 23 the 13 place plane of the second metal line layer orthographic projection at least with part second metal wire
Layer 13 coincides.
As an example, the heat radiation material layer 4 at least covers the active device area 24 and the passive device region
25。
As an example, the pixel region in the pixel wafer 1 is located at the active device in the logic wafer 2
Part region 24 and the surface of the passive device region 25.
As an example, the 3D stack cmos image sensor further includes silicon through hole interconnection structure 7, the through silicon via is mutual
Link structure 7 through the pixel wafer 1, second metal line layer 13 and the insulation material layer 3 until first metal
First metal line layer 23 and second metal line layer 13 are electrically connected by line layer 23；The silicon through hole interconnection structure 7 with
There is gap between the heat radiation material layer 3.
As an example, the material of the silicon through hole interconnection structure 7 may include but be not limited only to copper, aluminium, gold, silver, titanium, tin
And at least one of nickel etc..
As an example, the 3D stack cmos image sensor further includes weld pad 9, the weld pad 9 is located at described second
Side of the dielectric layer 12 far from the insulation material layer 3, and the weld pad 9 is electrically connected with second metal line layer 13.
As an example, during the material of the weld pad 9 may include but is not limited only to copper, aluminium, gold, silver, titanium, tin and nickel etc.
At least one.
The present invention, can be with by adding the insulation material layer 3 between the pixel wafer 1 and the 2 logic wafer
The heat for preventing the logic wafer 2 from generating is transmitted to the pixel wafer 1, reduces the dark current on the pixel wafer 1, from
And reduce the noise of the 3D stack cmos image sensor, improve the performance of the 3D stack cmos image sensor；
For the present invention by adding the heat radiation material layer 4 between the insulation material layer 3 and the logic wafer 2, the logic is brilliant
Circle 2 generate heats can along 4 Quick diffusing of heat radiation material layer to the outside of the 3D stack cmos image sensor,
It avoids heat accumulative in the 3D stack cmos image sensor, improves the 3D stack cmos image sensor
Performance and service life.
In conclusion the present invention provides a kind of 3D stack cmos image sensor and preparation method thereof, the 3D is stacked
Formula cmos image sensor includes: logic wafer；Pixel wafer is bonded on the logic wafer；Insulation material layer is located at institute
It states between logic wafer and the pixel wafer, and covers the surface of the pixel wafer；The insulation material layer is for preventing
The heat that the logic wafer generates is transmitted to the pixel wafer.The present invention between pixel wafer and logic wafer by increasing
If insulation material layer, the heat that logic wafer can be prevented to generate is transmitted to pixel wafer, reduces the dark current on pixel wafer,
To reduce the noise of 3D stack cmos image sensor, the performance of 3D stack cmos image sensor is improved；The present invention
By adding heat radiation material layer between insulation material layer and logic wafer, the heat that logic wafer generates can be along heat sink material
Layer Quick diffusing avoids heat in 3D stack cmos image sensor to the outside of 3D stack cmos image sensor
It is accumulative, improve performance and the service life of 3D stack cmos image sensor.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (16)
1. a kind of 3D stack cmos image sensor characterized by comprising
Logic wafer；
Pixel wafer is bonded on the logic wafer；
Insulation material layer between the logic wafer and the pixel wafer, and covers the surface of the pixel wafer；
The heat that the insulation material layer is used to that the logic wafer to be prevented to generate is transmitted to the pixel wafer.
2. 3D stack cmos image sensor according to claim 1, which is characterized in that the 3D stack CMOS figure
As sensor further includes heat radiation material layer, the heat radiation material layer is between the insulation material layer and the logic wafer.
3. 3D stack cmos image sensor according to claim 2, which is characterized in that the heat radiation material layer covering
The part of the surface of the insulation material layer；The 3D stack cmos image sensor further includes bonding medium layer, the bonding
Dielectric layer is between the logic wafer and the insulation material layer and the heat radiation material layer.
4. 3D stack cmos image sensor according to claim 2, which is characterized in that the insulation material layer includes
Low-k dielectric layers, the heat radiation material layer include metal layer；The 3D stack cmos image sensor further includes that metal sticks
Layer, the metal adhesion layer is between the heat radiation material layer and the insulation material layer.
5. 3D stack cmos image sensor according to claim 2, which is characterized in that
The logic wafer includes the first substrate, first medium layer and the first metal line layer；The first medium layer is located at described
The surface of first substrate, first metal line layer are located in the first medium layer；
The pixel wafer bonding on the first medium layer, the pixel wafer include the second substrate, second dielectric layer and
Second metal line layer；The second dielectric layer is located at the surface of second substrate, and is located at second substrate and described the
Between one dielectric layer；Second metal line layer is located in the second dielectric layer；
The insulation material layer and the heat radiation material layer are respectively positioned between the first medium layer and the second dielectric layer.
6. 3D stack cmos image sensor according to claim 5, which is characterized in that the 3D stack CMOS figure
As sensor further includes silicon through hole interconnection structure, the silicon through hole interconnection structure runs through the pixel wafer, second metal
Line layer and the insulation material layer are up to first metal line layer, by first metal line layer and second metal wire
Layer electrical connection；There is gap between the silicon through hole interconnection structure and the heat radiation material layer.
7. 3D stack cmos image sensor according to claim 6, which is characterized in that the 3D stack CMOS figure
As sensor further includes weld pad, the weld pad is located at side of the second dielectric layer far from the insulation material layer, and with institute
State the electrical connection of the second metal line layer.
8. 3D stack cmos image sensor according to claim 1, which is characterized in that formed in the pixel wafer
There is photodiode.
9. the 3D stack cmos image sensor according to any one of claim 2 to 8, which is characterized in that described to patrol
Collecting wafer includes active area devices region and passive device region；It is formed with active device in the active area device area, institute
Active device is stated to be electrically connected with first metal line layer；Passive device is formed in the passive device region；The heat dissipation
Material layer at least covers the active area device area and the passive device region.
10. a kind of preparation method of 3D stack cmos image sensor, which comprises the steps of:
Pixel wafer is provided；
Insulation material layer is formed in the surface of the pixel wafer, the insulation material layer covers the surface of the pixel wafer；
Logic wafer is provided；
The pixel wafer bonding of the insulation material layer will be formed on the logic wafer；It is described heat-insulated after bonding
Material layer is between the pixel wafer and the logic wafer.
11. the preparation method of 3D stack cmos image sensor according to claim 10, which is characterized in that Yu Suoshu
It further includes before following steps that the surface of pixel wafer, which forms after the insulation material layer and provides the logic wafer: in institute
It states insulation material layer and forms heat radiation material layer far from the surface of the pixel wafer；The pixel wafer bonding is brilliant in the logic
After on circle, the insulation material layer and the heat radiation material layer are respectively positioned between the pixel wafer and the logic wafer.
12. the preparation method of 3D stack cmos image sensor according to claim 11, which is characterized in that described to dissipate
Hot material layer covers the part of the surface of the insulation material layer；The insulation material layer and the heat radiation material layer will be formed with
The pixel wafer bonding further include before on the logic wafer in the heat radiation material layer surface and it is exposed described in
The surface of insulation material layer forms the step of bonding medium layer, and the pixel wafer is bonded to described via the bonding medium layer
On logic wafer.
13. the preparation method of 3D stack cmos image sensor according to claim 11, which is characterized in that it is described every
Hot material layer includes low-k dielectric layers, and the heat radiation material layer includes metal layer；It is brilliant far from the pixel in the insulation material layer
Round surface further includes in surface shape of the insulation material layer far from the pixel wafer before forming the heat radiation material layer
The step of at metal adhesion layer, the heat radiation material layer are formed in the table of the metal adhesion layer far from the insulation material layer
Face.
14. the preparation method of 3D stack cmos image sensor according to claim 11, which is characterized in that described to patrol
Collecting wafer includes the first substrate, first medium layer and the first metal line layer；The first medium layer is located at first substrate
Surface, first metal line layer are located in the first medium layer；
The pixel wafer bonding on the first medium layer, the pixel wafer include the second substrate, second dielectric layer and
Second metal line layer；The second dielectric layer is located at the surface of second substrate, and is located at second substrate and described the
Between one dielectric layer；Second metal line layer is located in the second dielectric layer；
The insulation material layer and the heat radiation material layer are respectively positioned between the first medium layer and the second dielectric layer.
15. the preparation method of 3D stack cmos image sensor according to claim 14, which is characterized in that will be formed
Having the pixel wafer bonding of the insulation material layer further includes following steps after on the logic wafer:
Through silicon via is formed, the through silicon via runs through the pixel wafer, second metal line layer and the insulation material layer, and
Expose first metal line layer；There is gap between the through silicon via and the heat radiation material layer；
In forming silicon through hole interconnection structure in the through silicon via.
16. the preparation method of 3D stack cmos image sensor according to claim 15, which is characterized in that form institute
Stating silicon through hole interconnection structure further includes later following steps:
Opening is formed far from the surface of the logic wafer in the pixel wafer, the opening exposes second metal wire
Layer；
In forming weld pad in the opening.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110544702A (en) * | 2019-08-30 | 2019-12-06 | 德淮半导体有限公司 | Semiconductor structure and forming method thereof, image sensor and forming method thereof |
| CN110571205A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
| CN110571206A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof and forming method of chip |
| CN112166499A (en) * | 2020-02-19 | 2021-01-01 | 深圳市汇顶科技股份有限公司 | Image sensor and electronic device |
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2019
- 2019-05-24 CN CN201910440475.5A patent/CN110164893A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110544702A (en) * | 2019-08-30 | 2019-12-06 | 德淮半导体有限公司 | Semiconductor structure and forming method thereof, image sensor and forming method thereof |
| CN110571205A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
| CN110571206A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof and forming method of chip |
| CN110571206B (en) * | 2019-09-12 | 2022-05-27 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof and forming method of chip |
| CN112166499A (en) * | 2020-02-19 | 2021-01-01 | 深圳市汇顶科技股份有限公司 | Image sensor and electronic device |
| WO2021163927A1 (en) * | 2020-02-19 | 2021-08-26 | 深圳市汇顶科技股份有限公司 | Image sensor and electronic apparatus |
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Application publication date: 20190823 |