CN110137197A - Cmos image sensor and its manufacturing method - Google Patents
Cmos image sensor and its manufacturing method Download PDFInfo
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- CN110137197A CN110137197A CN201910453879.8A CN201910453879A CN110137197A CN 110137197 A CN110137197 A CN 110137197A CN 201910453879 A CN201910453879 A CN 201910453879A CN 110137197 A CN110137197 A CN 110137197A
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- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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Abstract
This disclosure relates to cmos image sensor and its manufacturing method.Present disclose provides cmos image sensors, comprising: logic wafer is provided at least one first floating node in the first surface of the logic wafer；And pixel wafer, at least one second floating node and at least one photodiode are provided in the second surface of the pixel wafer, wherein, the first surface of the logic wafer and the second surface of the pixel wafer are by together with Intermediate Layer Bonding, and each first floating node at least one described first floating node is connected in series with the corresponding second floating node at least one described second floating node by the middle layer.
Description
Technical field
This disclosure relates to semiconductor field, in particular to cmos image sensor and its manufacturing method.
Background technique
Imaging sensor is the semiconductor devices for converting optical signals to electric signal, mainly includes charge-coupled device
(Charge Coupled Device, CCD) imaging sensor and complementary metal oxide semiconductor (Complementary
Metal Oxide Semiconductor, CMOS) imaging sensor.In recent years, cmos image sensor is by low cost, height
The advantages such as efficiency, transmission speed height gradually replace ccd image sensor as mainstream.
Cmos image sensor includes cmos image sensor and back-illuminated cmos image sensors front-illuminated.Back-illuminated type
Cmos image sensor is since with small power consumption, the advantages such as quantum efficiency height are widely used in mobile phone, video camera etc. at present and set
It is standby upper.Back-illuminated cmos image sensors advantage is to change the structure inside element, i.e., by the element side of turning of photosensitive layer
To allowing luminous energy from the back side, direct projection is entered, and avoiding light in cmos sensor structure front-illuminated will receive lenticule and photoelectricity two
The influence of metallic circuit and transistor between pole pipe improves the bat under low-light conditions to significantly improve the efficiency of light
Take the photograph effect.
Traditional back-illuminated cmos image sensors generally use 4T circuit structure, but 4T circuit structure is usually all integrated
Pixel region on same wafer, this may will affect the area of photosensitive region, and then influence imaging effect.With people
Demand to the imaging sensor with high pixel, exist improve back-illuminated cmos image sensors photosensitive region area with
And improve the needs of the imaging effect of back-illuminated cmos image sensors.
Summary of the invention
The first purpose of the disclosure is to provide a kind of novel cmos image sensor and its manufacturing method.
According to the disclosure in a first aspect, providing a kind of cmos image sensor characterized by comprising logic is brilliant
It is round, at least one first floating node is provided in the first surface of the logic wafer；And pixel wafer, the pixel are brilliant
At least one second floating node and at least one photodiode are provided in round second surface, wherein the logic is brilliant
Round first surface and the second surface of the pixel wafer by together with Intermediate Layer Bonding, and it is described at least one first
Each first floating node in floating node and the corresponding second floating node at least one described second floating node
It is connected in series by the middle layer.
According to the second aspect of the disclosure, a kind of method for manufacturing cmos image sensor is provided, feature exists
In, which comprises logic wafer is provided, at least one first floating section is set in the first surface of the logic wafer
Point；Pixel wafer is provided, at least one second floating node and at least one are set in the second surface of the pixel wafer
Photodiode；And the first surface of the logic wafer is bonded with the second surface of the pixel wafer by middle layer
Together, and by the middle layer by least one described first floating node each first floating node with it is described
Corresponding second floating node at least one second floating node is connected in series.
By the detailed description referring to the drawings to the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and together with the description for solving
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Fig. 1 instantiates the circuit diagram of the 4T dot structure of conventional CMOS image sensor.
Fig. 2 instantiates the electricity of the 4T dot structure of the cmos image sensor of some exemplary embodiments according to the disclosure
Road schematic diagram.
Fig. 3 instantiates the sectional view of the cmos image sensor of some exemplary embodiments according to the disclosure.
Fig. 4 instantiates the photodiode array of the cmos image sensor of some exemplary embodiments according to the disclosure
Layout top view.
Fig. 5 instantiates the vertical view of the RGB layout of the cmos image sensor of some exemplary embodiments according to the disclosure
Figure.
Fig. 6 instantiates the vertical view of the integral layout of the cmos image sensor of some exemplary embodiments according to the disclosure
Figure.
Fig. 7 instantiates the method for manufacturing cmos image sensor of some exemplary embodiments according to the disclosure
Flow chart.
Fig. 8 A to 8D instantiates the process of the manufacture cmos image sensor according to some exemplary embodiments of the disclosure
Sectional view.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below
It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
Multiple pixels are usually provided in cmos image sensor, the quality and performance of pixel are for cmos image sensor
Imaging effect have a significant impact.In recent years, 4T dot structure becomes current main-stream with lesser power consumption and superior performance
Dot structure.
Fig. 1 instantiates the circuit diagram of the 4T dot structure of conventional CMOS image sensor.Referring to Fig.1,4T pixel knot
Structure includes: photodiode PD, transmission switch TG, floating node FD, reset transistor RST, source follower SF, and selection
Transistor SEL.
Below with reference to the image sensing principle of Fig. 1 description tradition 4T dot structure.Firstly, making reset transistor RST
Conducting resets floating node FD using supply voltage VDD.It is then turned off reset transistor RST, makes to transmit switch TG conducting, warp
It can be shifted by the charge (electronics or hole) that photodiode PD carries out photoelectric conversion generation and be accumulated in floating node FD, from
And cause the bias voltage of source follower SF to change, and then influence the signal output of selection transistor SEL, to realize
Transformation from optical signal to electric signal.
However, the inventors of the present application found that 4T structure is often all integrated in same in above-mentioned cmos image sensor
In pixel region in wafer, this will limit the area of the photosensitive region of light sensitive diode PD, influence the raising of imaging effect.
In order to meet people for the pixel increasingly higher demands of imaging sensor, applicant proposed improved cmos image sensings
Device and its manufacturing method.Specifically, by the way that 4T structure to be arranged in two wafers and make improvements, photoelectricity two is improved
The area of the photosensitive region of pole pipe PD, reduces technology difficulty, improves image quality, in addition also achieves the two-stage tune of voltage
Section.
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.In the figure for ease of description, the thickness of layer and region has been zoomed in or out, shown size does not represent reality
Border size.Although these figures can not reflect to entirely accurate the actual size of device, they completely reflect
Upper and lower and neighbouring relations between mutual alignment between region and composed structure, especially composed structure.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the disclosure
And its application or any restrictions used.That is, method herein is to show in an exemplary fashion, to illustrate this public affairs
The different embodiments of structures and methods in opening.It will be understood by those skilled in the art, however, that they, which are merely illustrative, to be used to
The exemplary approach of the invention implemented, rather than mode exhausted.In addition, attached drawing is not necessarily drawn to scale, some features can
It can be amplified to show the details of specific component.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
In order to more comprehensively, the present invention is expressly understood, the novel skill according to the disclosure is illustrated below in conjunction with attached drawing
Art.
Fig. 2 instantiates the electricity of the 4T dot structure of the cmos image sensor of some exemplary embodiments according to the disclosure
Road schematic diagram.
As shown in Fig. 2, cmos image sensor includes two wafers, i.e., a piece of logic wafer and a piece of pixel wafer.It patrols
It collects and is provided with the first floating node FD1, reset transistor RST, source follower SF, selection transistor SEL on wafer and patrols
Collect circuit.The second floating node FD2, photodiode PD and transmission switch TG are provided on pixel wafer.
In this exemplary embodiment, the first floating node FD1 on logic wafer and the second floating on pixel wafer
Node FD2 is connected in series.By the way that a floating node is respectively arranged on logic wafer and pixel wafer and the two is connected, favorably
In transmitting electric signal between logic wafer and pixel wafer.In addition, by by the first floating node FD1 and the second floating node
FD2 is set as different capacitors, and the two-stage that can be realized voltage is adjusted.
In addition, in this exemplary embodiment, four adjacent photodiode PD are connected to the same second floating section
Point FD2, namely share the second floating node FD2.The case where sharing a floating node with usual two photodiodes phase
Than that can save the area occupied of the second floating node FD2 according to the structure of the exemplary embodiment, correspondingly increase photoelectricity two
The area in the region pole pipe PD, so as to improve image quality.In addition, the area of single second floating node FD2 can be set to compare
The area of floating node is big in traditional 4T structure, so can reduce technology difficulty, reduces manufacturing cost.
It is worth noting that, although illustrating only the example of limited FD1, FD2, PD, TG, RST, SF, SEL in Fig. 2,
It is that design of the invention is not limited to this, Fig. 2 is also not intended to limit the number of element.In some embodiments, cmos image
Sensor may include more FD1, FD2, PD, TG, RST, SF, SEL, and RST, SF, SEL can be total to by adjacent pixel
With so as to improve the integrated level of cmos image sensor.
In the following, with reference to Fig. 3 introduction according to the inside structure of the cmos image sensor of some exemplary embodiments of the disclosure
It makes.
Fig. 3 instantiates the sectional view of the cmos image sensor of some exemplary embodiments according to the disclosure.
As shown in figure 3, cmos image sensor includes: logic wafer 100, set in the first surface 110 of logic wafer 100
It is equipped at least one first floating node FD1；And pixel wafer 400, it is provided in the second surface 410 of pixel wafer 400
At least one second floating node FD2 and at least one photodiode PD, wherein the first surface 110 of logic wafer 100 with
The second surface 410 of pixel wafer 400 passes through Intermediate Layer Bonding together, and at least one first floating node FD1
Each first floating node is connected with the corresponding second floating node at least one second floating node FD2 by middle layer
Connection.
In some embodiments, pixel wafer 400 may include multiple pixels.Logic wafer 100 and pixel wafer 400 can
To be for example made of silicon.Pixel wafer 400 can be doped with impurity, such as n-type impurity (for example, aluminium, boron, indium, gallium).Some
In embodiment, pixel wafer 400 may include unitary semiconductor material or compound semiconductor materials (such as silicon carbide, SiGe,
GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide etc.) or combinations thereof.
In some embodiments, at least one source follower is provided on the first surface 110 of logic wafer 100
SF, at least one selection transistor SEL and at least one reset transistor RST.In some embodiments, in pixel wafer 400
Second surface 410 on be provided at least one transmission switch TG.
In some embodiments, middle layer may include the first metal interconnecting layer 200 and the second metal interconnecting layer 500.Such as
Shown in Fig. 3, the first metal interconnecting layer 200 is arranged on the first surface 110 of logic wafer 100, and the first metal interconnecting layer
First floating node FD1 is connected to source follower SF and reset transistor RST by 200, and source follower SF is connected to choosing
Select transistor SEL.Second metal interconnecting layer 500 is arranged on the second surface 410 of pixel wafer 400, and the second metal is mutual
Even photodiode PD is connected to transmission switch TG by layer 500, and transmission switch TG is connected to the second floating node FD2.Wherein,
First metal interconnecting layer 200 and the second metal interconnecting layer 500 can include more than one layer of metal connecting line.
In some embodiments, middle layer can also include bonding material layer 300, and bonding material layer 300 is located at the first gold medal
Belong among interconnection layer 200 and the second metal interconnecting layer 500, and by the first metal interconnecting layer 200 and the second metal interconnecting layer 500
It is bonded together.
Bonding material layer 300 can may be multilayer for one layer, can be for example by silicon nitride SiN, silica SiO2
It is made.In some embodiments, bonding material layer 300 may include the first bonding material layer 310 and the second bonding material layer
320.First bonding material layer 310 is arranged on the surface of separate logic wafer 100 of the first metal interconnecting layer 200, in Fig. 3
On shown namely the first metal interconnecting layer 200 upper surface.Second bonding material layer 320 is arranged in the second metal interconnecting layer 500
Separate pixel wafer 400 surface on, as shown in Figure 3 namely on the lower surface of the second metal interconnecting layer 500.Some
In embodiment, the first metal interconnecting layer 200 and the second metal interconnecting layer 500 pass through the first bonding material layer 310 and the second bonding
The bonding of material layer 320 and be bonded together.
In some embodiments, for the bonding being more advantageous between logic wafer 100 and pixel wafer 400, CMOS figure
As sensor can also can reduce alignment on bonding material layer 300 including metal gasket 330, the setting of metal gasket 330
Error bring adverse effect.In some embodiments, metal gasket 330 may include the first metal gasket 331 and the second gold medal
Belong to liner 332.First metal gasket 331 is arranged on the first bonding material layer 310, and the second metal gasket 332 is arranged second
On bonding material layer 320, and the first metal gasket 331 and the second metal gasket 332 are aligned with each otherly by bonding surface BI
Bonding.In some embodiments, the first metal gasket 331 and the second metal gasket 332 are preferably dimensioned to be 0.2um or more.
In some embodiments, cmos image sensor can also include first medium layer 600, and first medium layer 600 is set
It sets on surface of the pixel wafer 400 far from second metal interconnecting layer 500, as shown in Figure 3 namely pixel wafer 400
On upper surface.In some embodiments, cmos image sensor can also include multiple grids 700, each in multiple grids 700
A grid is evenly provided in first medium layer 600, to different pixels be separated, to prevent the string between different pixels
It disturbs.
In some embodiments, cmos image sensor can also include filter arrays 800, and filter arrays 800 are set
Set on the surface of the separate pixel wafer 400 of first medium layer 600, as shown in Figure 3 namely first medium layer 600 it is upper
On surface.Each optical filter in filter arrays 800 is evenly spaced apart by multiple grids 700.
In some embodiments, cmos image sensor can also include microlens array 900, and microlens array 900 is set
Set on the side of the separate pixel wafer 400 of filter arrays 800, as shown in Figure 3 namely filter arrays 800 it is upper
On surface.Each lenticule in microlens array 900 is arranged in correspondence on each optical filter in filter arrays 800.
Microlens array 900 plays the role of optically focused.
In some embodiments, cmos image sensor can also include liner through-silicon-via structure.Such as institute in Fig. 3
Show, liner through-silicon-via structure may include through-silicon-via TSV1001 and TSV liner 1002.Through-silicon-via TSV
1001 pass through first medium layer 600, pixel wafer 400 and the second metal interconnecting layer 500 and in the second metal interconnecting layer 500
Metal connecting line connection.The surface of the separate pixel wafer 400 of first medium layer 600 is arranged in (namely in Fig. 3 in TSV liner 1002
The upper surface of first medium layer 600) on, and contacted with TSV 1001.
In some embodiments, cmos image sensor can also include periphery loop area, and periphery loop area may include
Logic circuit 210.Logic circuit 210 is arranged on the first surface 110 of logic wafer 100, and logic circuit 210 is by the
One metal interconnecting layer 200, the second metal interconnecting layer 500, TSV 1001 and be connected to TSV liner 1002.
In some embodiments, cmos image sensor can also include photodiode array, photodiode array
Including at least four adjacent photodiode PD.Fig. 4 is instantiated to scheme according to the CMOS of some exemplary embodiments of the disclosure
As the top view of the layout of the photodiode array of sensor.As shown in Figure 4, under the visual angle of vertical view, according to the disclosure
The second floating node FD2 of each of exemplary embodiment be located at adjacent four photodiode in photodiode array
The center point of intersection of the diagonal line of PD, and four adjacent photodiode PD share the center point of intersection of its diagonal line
The second floating node FD2.Each photodiode PD is connect by metal connecting line MW with a transmission switch TG, each transmission
Switch TG is connect with the second shared floating node FD2.
In some embodiments, the size of photodiode PD is preferably 0.7um~1.2um, the second floating node FD2
Size be preferably 0.1um~0.3um.In addition, although only showing the example that the second floating node FD2 is diamond shape in Fig. 4,
It is that the shape of the second floating node FD2 is not limited to this, can have any shape, such as square, rectangle, polygon
Deng.
In some embodiments, filter arrays 800 are it is so structured that any one in permission red, green, blue passes through
And prevent the light of other colors from passing through, as long as adjacent optical filter allow by light color it is different.Fig. 5 is instantiated
The top view being laid out according to the RGB of the cmos image sensor of some exemplary embodiments of the disclosure.In some embodiments,
As shown in figure 5, filter arrays 800 and microlens array 900 can be Bayer array form.As an example, filter arrays
The optical filter in 800 upper left corner only allows feux rouges to pass through, and the optical filter in the upper right corner and the lower left corner only allows green light to pass through, the lower right corner
Optical filter only blue light is allowed to pass through, adjacent optical filter allow by light color it is different.In microlens array 900
Each lenticule accordingly covers on the corresponding optical filter in filter arrays 800.
Fig. 6 instantiates the vertical view of the integral layout of the cmos image sensor of some exemplary embodiments according to the disclosure
Figure.As shown in fig. 6, cmos image sensor includes pixel region and logic region under the visual angle of vertical view, logic region includes
Periphery loop area and liner through-silicon-via.In Fig. 6, pixel region, periphery loop area and liner through-silicon-via from a left side to
The right side is sequentially arranged.
Fig. 2 to Fig. 6 is had been combined above to describe according to the cmos image of some exemplary embodiments of disclosure sensing
The specific structure of device.Next, Fig. 7 to Fig. 8 D introduction will be combined to be used to manufacture according to some exemplary embodiments of the disclosure
The process of cmos image sensor.
Fig. 7 instantiates the method for manufacturing cmos image sensor of some exemplary embodiments according to the disclosure
Flow chart.Fig. 8 A to 8D instantiates the process of the manufacture cmos image sensor according to some exemplary embodiments of the disclosure
Sectional view.Note that Fig. 8 A to Fig. 8 D is illustrated by taking the structure of cmos image sensor shown in Fig. 3 as an example, but this field
The skilled person will understand that, a variety of imaging sensor knots may be implemented by the method 700 for manufacturing cmos image sensor
Structure, cmos image sensor including but not limited to shown in Fig. 3.
It is illustrated below in conjunction with Fig. 7 and Fig. 8 A to Fig. 8 D.
As shown in fig. 7, in step 720, providing logic wafer, it is arranged at least in the first surface of the logic wafer
One the first floating node.In some embodiments, the sectional view of cmos image sensor corresponding to step 710 can be such as figure
Shown in 8A.With reference to Fig. 8 A, provide logic wafer 100, be arranged in the first surface 110 of logic wafer 100 at least one first
Floating node FD1.Next, at least one source follower SF, at least is arranged on the first surface 110 of logic wafer 100
One selection transistor SEL and at least one reset transistor RST.As shown in Figure 8 A, the first floating node FD1, source electrode follow
Device SF, selection transistor SEL and reset transistor RST bit are in the pixel region of cmos image sensor.
Then, the first metal interconnecting layer 200 is set on the first surface 110 of logic wafer 100, it is mutual using the first metal
Even the first floating node FD1 is connected to source follower SF and reset transistor RST by layer 200, and by source follower SF
It is connected to selection transistor SEL.Next, logic circuit 210 is arranged on the first surface 110 of logic wafer 100, such as Fig. 8 A
Shown, logic circuit 210 is located in the periphery loop area of the logic region of cmos image sensor.Next, as an example,
The surface of the separate logic wafer 100 of first metal interconnecting layer 200 is (in fig. 8 a namely the upper table of the first metal interconnecting layer 200
Face) on the first bonding material layer 310 is set.It in some embodiments, can also be first in order to be more advantageous to the bonding of wafer
Metal gasket 331 is set on bonding material layer 310.
Return to Fig. 7, next, in step 720, provide pixel wafer, be arranged in the second surface of pixel wafer to
A few second floating node and at least one photodiode.In some embodiments, cmos image corresponding to step 720
The sectional view of sensor can be as shown in Figure 8 B.With reference to Fig. 8 B, pixel wafer 400 is provided, in the second surface of pixel wafer 400
At least one second floating node FD2 and at least one photodiode PD is set in 410.
In some embodiments, photodiode array, photoelectricity two are set in the second surface 410 of pixel wafer 400
Pole pipe array includes at least four adjacent photodiode PD.Under the visual angle of vertical view, each second floating node FD2 is set
The center point of intersection of the diagonal line of adjacent four photodiode PD in photodiode array, so that adjacent four
A photodiode PD shares the second floating node FD2 of the center point of intersection of its diagonal line.
Next, at least one transmission switch TG is arranged on the second surface 410 of pixel wafer 400.As shown in Figure 8 B,
Second floating node FD2, photodiode PD and transmission switch TG are located in the pixel region of cmos image sensor.Then,
Second metal interconnecting layer 500 is set on the second surface 410 of pixel wafer 400, using the second metal interconnecting layer 500 by photoelectricity
Diode PD is connected to transmission switch TG, and transmission switch TG is connected to the second floating node FD2.Next, as showing
Example, the surface of the separate pixel wafer 400 of the second metal interconnecting layer 500 (in the fig. 8b namely the second metal interconnecting layer 500
Upper surface) on the second bonding material layer 320 is set.It in some embodiments, can be in order to be more advantageous to the bonding of wafer
Metal gasket 332 is set on the second bonding material layer 320.
With continued reference to Fig. 7, next, in step 730, it is by middle layer that the first surface of logic wafer and pixel is brilliant
Round second surface is bonded together, and passes through middle layer for each first floating section at least one first floating node
Point is connected in series with the corresponding second floating node at least one second floating node.In some embodiments, step 730
The sectional view of corresponding cmos image sensor can be as shown in Figure 8 C.With reference to Fig. 8 C, pixel wafer 400 is overturn, in
The first surface 110 of logic wafer 100 and the second surface 410 of pixel wafer 400 be bonded together by interbed, and passes through
Interbed will be in each first floating node and at least one second floating node FD2 at least one first floating node FD1
Corresponding second floating node be connected in series.
As an example, middle layer includes the first metal interconnecting layer 200, the first bonding material layer 310, second in Fig. 8 C
Bonding material layer 320, metal gasket 331 and 332 and the second metal interconnecting layer 500.Although illustrating only middle layer packet here
The example of two layers of bonding material layer and double layer of metal liner is included, it should be appreciated to those skilled in the art that middle layer can also be with
It only include any one layer of bonding material layer and metal gasket in the first bonding material layer 310 and the second bonding material layer 320
Any one layer of metal gasket in 331 and 332.In some embodiments, there are one layer of bonding material layer,
Bonding material layer 300 is set among one metal interconnecting layer 200 and the second metal interconnecting layer 500, and passes through bonding material layer 300
First metal interconnecting layer 200 and the second metal interconnecting layer 500 are bonded together.In some embodiments, there are two layers of keys
In the case where condensation material layer, first metal is interconnected by the bonding of the first bonding material layer 310 and the second bonding material layer 320
Layer 200 and the second metal interconnecting layer 500 are bonded together.
It in some embodiments, such as can be by copper-copper bonding technology by 400 key of logic wafer 100 and pixel wafer
It is combined.In some embodiments, by after bonding logic wafer 100 and pixel wafer 400 be thinned to certain thickness, with suitable
In the subsequent manufacture for carrying out cmos image sensor.In some embodiments it may be preferred that reduction processing can use CMP processing
It is carried out with wet-cleaning.
Next, with reference to Fig. 8 D, pixel wafer 400 far from the second metal interconnecting layer 500 surface (in Fig. 8 D,
Namely the upper surface of pixel wafer 400) on be arranged first medium layer 600, and in first medium layer 600 equably be arranged it is more
A grid 700, to different pixels be separated, to prevent that crosstalk occurs between different pixels.
Next, construction liner through-silicon-via structure, liner penetrate silicon in the logic region of cmos image sensor
Through-hole structure includes through-silicon-via TSV 1001 and TSV liner 1002.Through-silicon-via TSV 1001 may include in logic
In region pass through first medium layer 600,400 second metal interconnecting layer 500 of pixel wafer and in the second metal interconnecting layer
The through-hole of metal connecting line connection.In some embodiments, (scheming on the surface of the separate pixel wafer 400 of first medium layer 600
In the 8D namely upper surface of first medium layer 600) on setting TSV pad 1002, and make TSV liner 1002 with TSV 1001
Contact.
In some embodiments, through-silicon-via TSV1001 can be formed by deep silicon etching technique.In some embodiments
In, contact can be filled in through-silicon-via TSV 1001, contact contacts the second metal interconnecting layer 500, the second metal
Interconnection layer 500 is connect by the first metal interconnecting layer 200 with logic circuit 210, so that logic circuit 210 can pass through
1002 connection of TSV1001 and TSV liner comes out.
In some embodiments, contact, the first metal connecting line layer 200 and the second metal interconnecting layer 400 may include copper.
In some embodiments, the forming step of the first metal connecting line layer 200 and the second metal interconnecting layer 400 can wrap
It includes: depositing a layers of copper on wafer, and handled using lithography and etching and the layers of copper is patterned, to form first
Metal connecting line layer 200 and the second metal interconnecting layer 400.
In some embodiments, next, first medium layer 600 separate pixel wafer 400 surface (in Fig. 8 D
In namely first medium layer 600 upper surface) on filter arrays 800, each optical filter in filter arrays 800 are set
It is evenly spaced apart by multiple grids 700.Then, in some embodiments, in the separate pixel wafer of filter arrays 800
Microlens array 900 is set on 400 side, and each lenticule in microlens array 900 is arranged in correspondence in optical filter battle array
On each optical filter in column 800.
In addition, it will be appreciated by those skilled in the art that the flow example is not intended to be construed as limiting the invention.Although
The present invention illustrates only the thinned die after wafer bonding and remanufactures through-silicon-via, but it is to be understood that the present invention can also
To manufacture through-silicon-via immediately after wafer bonding, subsequent technique processing is then carried out again, it can also be in all subsequent techniques
Through-silicon-via is made again after the completion of processing, makes through-silicon-via again after can also carrying out some processes after bonding.
Finally, bonded wafer can be subjected to slicing treatment after the completion of the manufacturing process of entire cmos image sensor,
To form individual cmos image sensor one by one.
It will be understood by those skilled in the art that the disclosure further includes being formed other than process and structure as illustrated
Other any process and structures necessary to cmos image sensor.
In addition, in some embodiments, the present invention also provides the imaging devices including the cmos image sensor.
In conclusion 4T structure is arranged in two wafers by the cmos image sensor of embodiment according to the present invention,
To improve the area of the photosensitive region of photodiode, improve imaging effect.In addition, embodiment according to the present invention
A floating node is respectively arranged in cmos image sensor on logic wafer and pixel wafer, is conducive between two wafers
Electric signal is transmitted, and the two-stage that can be realized voltage is adjusted.In addition, the cmos image sensor of embodiment according to the present invention
So that four photodiodes share a second floating node, the number of the second floating node can be so saved, to increase
The area of big photodiode area, improves image quality, can also increase the area of single second floating node, to reduce
Technology difficulty reduces manufacturing cost.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can in this institute
It is operated in those of description show or other other different orientations of orientation.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
It is preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technique, summary of the invention or specific embodiment
Given in go out theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
In addition, middle certain term of use can also be described below, and thus not anticipate just to the purpose of reference
Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this
Class number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
It can be combined into single operation, single operation can be distributed in additional operation, and operating can at least portion in time
Divide and overlappingly executes.Moreover, alternative embodiment may include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
It should be understood that the embodiment of present invention disclosed is not limited to specific structure disclosed herein, processing step
Rapid or material, but its equivalent is expanded to as those of ordinary skill in the related art will be recognized.It should also be understood that
, terminology employed herein is used only for the purpose of describing specific embodiments, is not intended to limit.
In addition, described feature, structure or feature can in any suitable manner in one or more embodiments
Combination.In the above description, numerous details and example are provided, to provide the thorough understanding to the embodiment of the present invention.
But one skilled in the relevant art will recognize that, the present invention can be in the feelings of one or more of no detail
It practices, or can be practiced with other methods, component, material etc. under condition.In other cases, well-known structure, material
Material or operation are not shown or described in detail, to avoid fuzzy each aspect of the present invention.
In addition, embodiment of the present disclosure can also include following example:
1) a kind of cmos image sensor characterized by comprising
Logic wafer is provided at least one first floating node in the first surface of the logic wafer；And
Pixel wafer is provided at least one second floating node and at least one in the second surface of the pixel wafer
Photodiode,
Wherein, the second surface of the first surface of the logic wafer and the pixel wafer is by Intermediate Layer Bonding one
It rises, and each first floating node at least one described first floating node and at least one described second floating node
In corresponding second floating node be connected in series by the middle layer.
2) cmos image sensor according to 1 characterized by comprising
Photodiode array, including at least four adjacent photodiodes,
Wherein, under the visual angle of vertical view, each second floating node is located at adjacent in the photodiode array
The center point of intersection of the diagonal line of four photodiodes, and four adjacent photodiodes share its diagonal line
Second floating node of center point of intersection.
3) cmos image sensor according to 1, which is characterized in that further include:
At least one source follower, at least one selection transistor on the first surface of the logic wafer are set
With at least one reset transistor；And
At least one transmission switch on the second surface of the pixel wafer is set.
4) cmos image sensor according to 3, which is characterized in that the middle layer includes:
First metal interconnecting layer, first metal interconnecting layer are arranged on the first surface of logic wafer, and described first
First floating node is connected to source follower and reset transistor by metal interconnecting layer, and source follower is connected to choosing
Select transistor；
Second metal interconnecting layer, second metal interconnecting layer are arranged on the second surface of pixel wafer, and described second
Photodiode is connected to transmission switch by metal interconnecting layer, and transmission switch is connected to the second floating node.
5) cmos image sensor according to 4, which is characterized in that the middle layer further include:
Bonding material layer, the bonding material layer are located in first metal interconnecting layer and second metal interconnecting layer
Between, and first metal interconnecting layer and second metal interconnecting layer are bonded together.
6) cmos image sensor according to 5, which is characterized in that the bonding material layer includes:
Patrolling far from described for first metal interconnecting layer is arranged in first bonding material layer, first bonding material layer
On the surface for collecting wafer；And
The separate picture of second metal interconnecting layer is arranged in second bonding material layer, second bonding material layer
On the surface of plain wafer,
Wherein, first metal interconnecting layer and second metal interconnecting layer pass through first bonding material layer and institute
It states the bonding of the second bonding material layer and is bonded together.
7) cmos image sensor according to 6, which is characterized in that further include:
Metal gasket, the metal gasket are arranged on first bonding material layer and second bonding material layer.
8) cmos image sensor according to 4, which is characterized in that further include:
Separate second metal interconnecting layer of the pixel wafer is arranged in first medium layer, the first medium layer
On surface；And
Multiple grids, each grid in the multiple grid are evenly provided in the first medium layer.
9) cmos image sensor according to 8, which is characterized in that further include:
The surface far from the pixel wafer of the first medium layer is arranged in filter arrays, the filter arrays
On, and each optical filter in the filter arrays is evenly spaced apart by the multiple grid；And
The side far from the pixel wafer of the filter arrays is arranged in microlens array, the microlens array
On, and each lenticule in the microlens array is arranged in correspondence with each optical filter in the filter arrays
On.
10) cmos image sensor according to 8, which is characterized in that further include:
Through-silicon-via structure is padded, the liner through-silicon-via structure includes through-silicon-via TSV and TSV liner,
The TSV is mutual with second metal across the first medium layer, the pixel wafer and second metal interconnecting layer
Even the surface far from the pixel wafer of the first medium layer is arranged in the metal connecting line connection in layer, the TSV liner
Above and with the TSV contact.
11) cmos image sensor according to 10, which is characterized in that further include:
Periphery loop area, the periphery loop area includes logic circuit, and the logic circuit is arranged in the logic wafer
First surface on, and the logic circuit is by first metal interconnecting layer, second metal interconnecting layer, described
TSV and be connected to TSV liner.
12) a kind of method for manufacturing cmos image sensor characterized by comprising
Logic wafer is provided, at least one first floating node is set in the first surface of the logic wafer；
Pixel wafer is provided, at least one second floating node and at least is set in the second surface of the pixel wafer
One photodiode；And
The first surface of the logic wafer and the second surface of the pixel wafer are bonded together by middle layer,
And by the middle layer by each first floating node and described at least one at least one described first floating node
Corresponding second floating node in a second floating node is connected in series.
13) method according to 12 for manufacturing cmos image sensor characterized by comprising
Photodiode array is set in the second surface of the pixel wafer, and the photodiode array includes extremely
Few four adjacent photodiodes；And
Under the visual angle of vertical view, adjacent four that each second floating node are placed in the photodiode array
The center point of intersection of the diagonal line of photodiode, so that four adjacent photodiodes share the center of its diagonal line
Second floating node of point of intersection.
14) method according to 12 for manufacturing cmos image sensor characterized by comprising
Be arranged on the first surface of the logic wafer at least one source follower, at least one selection transistor and
At least one reset transistor；And
At least one transmission switch is set on the second surface of the pixel wafer.
15) method according to 14 for manufacturing cmos image sensor, which is characterized in that further include:
The first metal interconnecting layer is set on the first surface of the logic wafer, it will using first metal interconnecting layer
First floating node is connected to source follower and reset transistor, and source follower is connected to selection transistor；With
And
The second metal interconnecting layer is set on the second surface of the pixel wafer, it will using second metal interconnecting layer
Photodiode is connected to transmission switch, and transmission switch is connected to the second floating node.
16) method according to 15 for manufacturing cmos image sensor, which is characterized in that further include:
Bonding material layer is set among first metal interconnecting layer and second metal interconnecting layer, and passes through institute
It states bonding material layer first metal interconnecting layer and second metal interconnecting layer are bonded together.
17) method according to 16 for manufacturing cmos image sensor, which is characterized in that further include:
The first bonding material layer is set on the surface far from the logic wafer of first metal interconnecting layer；
The second bonding material layer is set on the surface far from the pixel wafer of second metal interconnecting layer；And
By the bonding of first bonding material layer and second bonding material layer by first metal interconnecting layer
It is bonded together with second metal interconnecting layer.
18) method according to 17 for manufacturing cmos image sensor, which is characterized in that further include:
Metal gasket is set on first bonding material layer and second bonding material layer.
19) method according to 15 for manufacturing cmos image sensor, which is characterized in that further include:
First medium layer is set on the surface far from second metal interconnecting layer of the pixel wafer；And
Multiple grids are equably set in the first medium layer.
20) method according to 19 for manufacturing cmos image sensor, which is characterized in that further include:
Filter arrays, the optical filter battle array are set on the surface far from the pixel wafer of the first medium layer
Each optical filter in column is evenly spaced apart by the multiple grid；And
Microlens array, the lenticule battle array are set on the side far from the pixel wafer of the filter arrays
Each lenticule in column is arranged in correspondence on each optical filter in the filter arrays.
21) method according to 19 for manufacturing cmos image sensor, which is characterized in that further include:
Construction liner through-silicon-via structure, the liner through-silicon-via structure include through-silicon-via TSV and TSV lining
Pad；
By the TSV structure be across the first medium layer, the pixel wafer and second metal interconnecting layer and
It is connect with the metal connecting line in second metal interconnecting layer；And
The TSV liner is set on the surface far from the pixel wafer of the first medium layer, and is made described
TSV liner is contacted with the TSV.
22) method according to 21 for manufacturing cmos image sensor, which is characterized in that further include:
Periphery loop area is constructed, the periphery loop area includes logic circuit；
The logic circuit is set on the first surface of the logic wafer, and by the logic circuit be configured to through
Cross first metal interconnecting layer, second metal interconnecting layer, the TSV and be connected to TSV liner.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of cmos image sensor characterized by comprising
Logic wafer is provided at least one first floating node in the first surface of the logic wafer；And
Pixel wafer is provided at least one second floating node and at least one photoelectricity in the second surface of the pixel wafer
Diode,
Wherein, the first surface of the logic wafer and the second surface of the pixel wafer be by together with Intermediate Layer Bonding,
And in each first floating node at least one described first floating node and at least one described second floating node
Corresponding second floating node be connected in series by the middle layer.
2. cmos image sensor according to claim 1 characterized by comprising
Photodiode array, including at least four adjacent photodiodes,
Wherein, under the visual angle of vertical view, each second floating node is located at adjacent four in the photodiode array
The center point of intersection of the diagonal line of photodiode, and four adjacent photodiodes share the center of its diagonal line
Second floating node of point of intersection.
3. cmos image sensor according to claim 1, which is characterized in that further include:
At least one source follower on the first surface of the logic wafer, at least one selection transistor and extremely are set
A few reset transistor；And
At least one transmission switch on the second surface of the pixel wafer is set.
4. cmos image sensor according to claim 3, which is characterized in that the middle layer includes:
First metal interconnecting layer, first metal interconnecting layer are arranged on the first surface of logic wafer, first metal
First floating node is connected to source follower and reset transistor by interconnection layer, and source follower is connected to selection crystalline substance
Body pipe；
Second metal interconnecting layer, second metal interconnecting layer are arranged on the second surface of pixel wafer, second metal
Photodiode is connected to transmission switch by interconnection layer, and transmission switch is connected to the second floating node.
5. cmos image sensor according to claim 4, which is characterized in that the middle layer further include:
Bonding material layer, the bonding material layer are located among first metal interconnecting layer and second metal interconnecting layer,
And first metal interconnecting layer and second metal interconnecting layer are bonded together.
6. cmos image sensor according to claim 5, which is characterized in that the bonding material layer includes:
The brilliant far from the logic of first metal interconnecting layer is arranged in first bonding material layer, first bonding material layer
On round surface；And
The brilliant far from the pixel of second metal interconnecting layer is arranged in second bonding material layer, second bonding material layer
On round surface,
Wherein, first metal interconnecting layer and second metal interconnecting layer pass through first bonding material layer and described the
The bonding of two bonding material layers and be bonded together.
7. cmos image sensor according to claim 6, which is characterized in that further include:
Metal gasket, the metal gasket are arranged on first bonding material layer and second bonding material layer.
8. cmos image sensor according to claim 4, which is characterized in that further include:
The surface far from second metal interconnecting layer of the pixel wafer is arranged in first medium layer, the first medium layer
On；And
Multiple grids, each grid in the multiple grid are evenly provided in the first medium layer.
9. cmos image sensor according to claim 8, which is characterized in that further include:
Filter arrays, the filter arrays are arranged on the surface far from the pixel wafer of the first medium layer,
And each optical filter in the filter arrays is evenly spaced apart by the multiple grid；And
Microlens array, the microlens array are arranged on the side far from the pixel wafer of the filter arrays,
And each lenticule in the microlens array is arranged in correspondence on each optical filter in the filter arrays.
10. cmos image sensor according to claim 8, which is characterized in that further include:
Through-silicon-via structure is padded, the liner through-silicon-via structure includes through-silicon-via TSV and TSV liner, described
TSV pass through the first medium layer, the pixel wafer and second metal interconnecting layer and with second metal interconnecting layer
In metal connecting line connection, TSV liner is arranged on the surface far from the pixel wafer of the first medium layer simultaneously
And it is contacted with the TSV.
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| CN112002717A (en) * | 2020-07-31 | 2020-11-27 | 深圳奥比中光科技有限公司 | Image sensor pixel array structure and manufacturing method |
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