CN110137175A - Three dimensional NAND memory and forming method thereof - Google Patents
Three dimensional NAND memory and forming method thereof Download PDFInfo
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- CN110137175A CN110137175A CN201810129089.XA CN201810129089A CN110137175A CN 110137175 A CN110137175 A CN 110137175A CN 201810129089 A CN201810129089 A CN 201810129089A CN 110137175 A CN110137175 A CN 110137175A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The present invention provides a kind of three dimensional NAND memories and forming method thereof, the forming method includes: to provide a substrate, sacrificial layer and the alternately stacked stacked structure of wall are formed on the substrate, multiple grooves are formed in the first layer sacrificial layer of the substrate in the stacked structure, the groove exposes the substrate, and support portion is formed in the groove, the support portion is used to support each interlayer interlayer disposed thereon, can prevent collapsing for memory.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of three dimensional NAND memory and forming method thereof.
Background technique
With the development of semiconductor technology, have developed various semiconductor storage units, such as or non-(NOR) flash memory, with it is non-
(NAND) flash memory etc..Relative to conventional memory devices such as magnetic memory device, semiconductor storage unit is fast with access speed, stores
The advantages that density is high.Wherein, NAND structure just receives more and more attention.Further to promote storage density, occur three
Tie up (3D) nand memory.
Three dimensional NAND memory is a kind of novel product based on plane nand memory, and the main characteristics of this product are
Stereochemical structure is converted by plane result, silicon area is greatly saved, reduces manufacturing cost.
The forming method of three dimensional NAND memory is usually to be formed on the substrate to be staggeredly stacked by sacrificial layer and wall
Then stacked structure forms channel structure in stacked structure, forms groove in stacked structure later, removed by groove sacrificial
Domestic animal layer, then forms metal layer between wall, is finally etched back to metal layer.But metal layer carve
The metal layer that will lead to stacked structure bottommost during erosion is etched completely, and stacked structure only passes through channel structure and propped up
Support, is easy to cause collapsing for memory.
Summary of the invention
The present invention provides a kind of three dimensional NAND memory and forming method thereof, close to the first layer of substrate in stacked structure
Support portion is formed in metal layer, avoids collapsing for three dimensional NAND memory.
The forming method of three dimensional NAND memory provided by the invention, comprising:
One substrate is provided；
Sacrificial layer and the alternately stacked stacked structure of wall are formed on the substrate, it is close in the stacked structure
Multiple grooves are formed in the first layer sacrificial layer of the substrate, the groove exposes the substrate, and shape in the groove
At support portion.
Further, the method for forming the support portion includes:
An insulating layer is formed on the first layer sacrificial layer, the insulating layer fills up the groove and covers described first
Layer sacrificial layer；
The insulating layer is planarized, until exposing the first layer sacrificial layer, forms support in the groove
Portion.
Further, the method for forming the support portion includes: to form an interval insulant on the first layer sacrificial layer
Layer, the layer of spacer material fill up the groove and cover the first layer sacrificial layer, form support portion in the groove；
The layer of spacer material is planarized, first layer wall is formed.
Further, before forming the stacked structure, the forming method of the three dimensional NAND memory further include:
Initial spacer layer is formed in the substrate.
Further, it is formed after the stacked structure, the forming method of the three dimensional NAND memory further include:
Multiple channel holes are formed, the stacked structure is run through in the channel hole, and stops in the substrate；
Channel structure is formed in the channel hole.
Further, multiple grooves in the first layer sacrificial layer are arranged in two rows, and the channel hole is located at
Between groove described in two rows, and the channel hole is arranged in two rows, and capable extending direction is first direction.
Further, the groove mutually staggers in a second direction with the channel hole, the second direction with it is described
First direction is vertical.
Further, the groove is consistent with the shape of the cross section in the channel hole and size.
Further, it is formed after the channel structure, the forming method of the three dimensional NAND memory further include:
The stacked structure and the part substrate are performed etching, form groove, it is remote that the groove is located at the groove
Side from the channel hole；
The sacrificial layer in the stacked structure is removed by the groove；
Metal layer is filled between the adjacent wall.
Further, after filling the metal layer, the forming method of the three dimensional NAND memory further include:
The metal layer is etched back, so that aperture of the groove in the metal layer is greater than at the interval
Aperture in layer.
Further, the groove is in a strip shape, extends in a first direction.
Further, the material of the wall is silica, and the material of the sacrificial layer is silicon nitride, the support portion
Material be silica.
Correspondingly, the present invention also provides a kind of three dimensional NAND memories, comprising:
Substrate, the stacked structure in the substrate；
Wherein, the stacked structure includes alternately stacked metal layer and wall, and close to the first of the substrate
Multiple support portions are formed in layer metal layer.
Further, the three dimensional NAND memory further include: through the ditch of the stacked structure and the part substrate
Road structure.
Further, multiple support portions in the first layer metal layer are arranged in two rows, the channel structure position
Between the support portion described in two rows, and the channel structure is arranged in two rows, and capable extending direction is first direction.
Further, the support portion mutually staggers in a second direction with the channel structure, the second direction with
The first direction is vertical.
In three dimensional NAND memory provided by the invention and forming method thereof, sacrificial layer is formed on the substrate and wall is handed over
For the stacked structure of stacking, multiple grooves, institute are formed in the first layer sacrificial layer of the substrate in the stacked structure
It states groove and exposes the substrate, and form support portion in the groove, the support portion is used to support disposed thereon each
Interlayer interlayer can prevent collapsing for memory.
Further, after sacrificial layer of the removal between each interlayer interlayer, metal is formed between each interlayer interlayer
Layer is provided with support portion in the first layer metal layer of substrate, during being etched back to metal layer, first layer gold
Belong to layer inevitably by over etching, the supporting layer being now placed in first layer metal layer is played a supporting role, so as to keep away
Exempt from collapsing for the memory as caused by the over etching of first layer metal layer.
Detailed description of the invention
Fig. 1 a~1c is a kind of each step the schematic diagram of the section structure of the forming method of three dimensional NAND memory.
Fig. 2 is the flow diagram of the forming method of three dimensional NAND memory provided by one embodiment of the invention.
Fig. 3 a~3l is each step section of the forming method of three dimensional NAND memory provided by one embodiment of the invention
Structural schematic diagram.
Fig. 4 is the top view of three dimensional NAND memory provided by one embodiment of the invention.
Specific embodiment
Fig. 1 a~1c is each step the schematic diagram of the section structure of the forming method of three dimensional NAND memory in the prior art, such as
Shown in Fig. 1 a~1c, in the manufacturing process of three dimensional NAND memory in the prior art, initial gap is formed on the substrate 10
Layer 11 and stacked structure 20, the stacked structure 20 are staggeredly stacked by sacrificial layer 12 and wall 13, as shown in Figure 1a (
Three-decker is illustrated only in Fig. 1 a)；Etching forms channel hole in stacked structure 20, initial spacer layer 11 and part of substrate 10
(not identifying) forms channel structure 22, as shown in Figure 1 b in channel hole；Groove 23 is formed in 22 two sides of channel structure, it is described
Groove 23 runs through the stacked structure 20, initial spacer layer 11, and is located in part of substrate 10, removes institute by the groove 23
Sacrificial layer 12 is stated, and fills metal layer 14 at the position of the sacrificial layer 12, then the metal layer 14 is etched back,
So that the groove 23 is less than the aperture in the wall 13 in the aperture in the metal layer 14, the gold of different layers is avoided
Belong to layer 14 to connect.
But to the process that the metal layer 14 is etched back, will lead in stacked structure 20 close to the base
The first layer metal layer at bottom 10 is etched completely, and as illustrated in figure 1 c, i.e., stacked structure 20 is only supported by channel structure 22,
There is the risk collapsed so as to cause the three dimensional NAND memory.
In view of the above-mentioned problems, present inventor proposes a kind of forming method of three dimensional NAND memory, comprising: provide one
Substrate；Sacrificial layer and the alternately stacked stacked structure of wall are formed on the substrate, close to institute in the stacked structure
It states and forms multiple grooves in the first layer sacrificial layer of substrate, the groove exposes the substrate, and is formed in the groove
Support portion.
In three dimensional NAND memory provided by the invention and forming method thereof, sacrificial layer is formed on the substrate and wall is handed over
For the stacked structure of stacking, multiple grooves, institute are formed in the first layer sacrificial layer of the substrate in the stacked structure
It states groove and exposes the substrate, and form support portion in the groove, the support portion is used to support disposed thereon each
Interlayer interlayer can prevent collapsing for memory.
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are done into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replacement well known to those skilled in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, in detail that example of the present invention, for the ease of saying
Bright, schematic diagram is not partially enlarged in proportion to the general scale, should not be to this as restriction of the invention.
Fig. 2 is the flow diagram of the forming method of three dimensional NAND memory provided by one embodiment of the invention, such as Fig. 2
It is shown, a kind of forming method of three dimensional NAND memory proposed by the present invention, comprising the following steps:
Step S100: a substrate is provided；
Step S200: sacrificial layer and the alternately stacked stacked structure of wall are formed on the substrate, in the stacking
Multiple grooves are formed in structure in the first layer sacrificial layer of the substrate, the groove exposes the substrate, and in institute
It states and forms support portion in groove.
Fig. 3 a~3l is each step section of the forming method of three dimensional NAND memory provided by one embodiment of the invention
Structural schematic diagram, Fig. 4 are the top view of three dimensional NAND memory provided by one embodiment of the invention, are please referred to shown in Fig. 2, and
In conjunction with Fig. 3 a~Fig. 3 l and Fig. 4, the forming method for the three dimensional NAND memory that the present invention will be described in detail proposes:
In the step s 100, a substrate 100 is provided, as shown in Figure 3a.
In the present embodiment, the substrate 100 be semiconductor base, such as can for silicon (Si) substrate, germanium (Ge) substrate,
SiGe (SiGe) substrate, silicon-on-insulator (SOI, Silicon On Insulator) or germanium on insulator (GOI, Germanium
On Insulator) etc..In other embodiments, the substrate 100 can also be include other elements semiconductor or compound
Substrate of semiconductor, such as GaAs (GaAs), indium phosphide (InP) or silicon carbide (SiC) etc. can also be laminated construction, example
Such as silicon/SiGe (Si/SiGe) can also be other epitaxial structures, such as SGOI (silicon germanium on insulator) etc..In the present embodiment
In, the substrate 100 is silicon substrate.Doped region or semiconductor structure etc. can also be formed in the substrate 100, the present invention
It does not limit this.
In the present embodiment, initial spacer layer 110 is also formed in the substrate 100, it is preferred that the initial spacer layer
110 be silicon oxide layer.It can be formed in the substrate 100 using the methods of the method for thermal oxide or chemical vapor deposition
Initial spacer layer 110.The thickness of the initial spacer layer 110 cannot be too thick, if too thick, will lead to entire three dimensional NAND storage
The volume of device is larger, in addition, each layer in the stacked structure being formed thereon 200 can be also easy to cause to misplace.Preferably,
The thickness of the initial spacer layer 110 generally exists
In step s 200, sacrificial layer and the alternately stacked stacked structure 200 of wall are formed in the substrate 100,
Multiple grooves 121, the groove are formed in the first layer sacrificial layer 120 of the substrate 100 in the stacked structure 200
121 expose the substrate 100, and support portion 131 is formed in the groove 121, as shown in Fig. 3 b~3f.
The stacked structure 200 is by sacrificial layer and the alternately laminated formation of wall.Wherein, one layer of sacrificial layer with it is adjacent thereon
Wall constitute stacked structure one layer of structure.Heap is determined according to the number of the storage unit of formation required in vertical direction
The number of plies of lamination, the number of plies of stacked structure 200 for example can be 8 layers, 32 layers, 64 layers etc., and the number of plies of stack layer is more, can more mention
High integration.It is specific as follows with the number of plies of stack layer for 3 layers of progress example in the present embodiment:
Step S201 is first carried out, first layer sacrificial layer 120 is formed in the initial spacer layer 110, as an example, can
To form the first layer sacrificial layer 120 using chemical vapor deposition, atomic layer deposition or other suitable deposition methods, formed
Structure as shown in Figure 3a.
Then step S202 is executed, forms multiple grooves 121 in the first layer sacrificial layer 120, the groove 121 is sudden and violent
Expose the initial spacer layer 110, as shown in Figure 3b.
Specifically, form a photoresist layer on the first layer sacrificial layer 120, to the photoresist layer be exposed with
Development, forms patterned photoresist layer, exposes the first layer sacrificial layer at the predetermined position for forming the groove
110, then the first layer sacrificial layer 120 is performed etching using the patterned photoresist layer as exposure mask, until exposing
The initial spacer layer 110 forms multiple grooves 121.
It please refers to shown in Fig. 3 b and Fig. 4, (position in Fig. 4 is equivalent to the support being subsequently formed to multiple grooves 121
Position where portion 131) it is located at the first layer sacrificial layer 120 (position that the position in Fig. 4 is equivalent to the substrate 100)
An opposite sides.Preferably, multiple grooves 121 of either side are arranged in 110 opposite sides of first layer sacrificial layer
Align, i.e., the described groove 121 are arranged in two rows, are located at the two sides of the first layer sacrificial layer 110, wherein row prolongs
Stretching direction is first direction, and the extending direction of 110 opposite sides of first layer sacrificial layer is second direction, the first direction and institute
It is perpendicular to state second direction.It should be noted that the substrate 100 can be on first direction shown in Fig. 4 and second direction
Extend, i.e., the described first layer sacrificial layer 110 can be upwardly extended with second party in a first direction, when the first layer sacrificial layer
110 when the first direction extends, and the quantity of the groove 121 increases, and along the place of groove 121 described in Fig. 4
The arrangement of two line disciplines.When the first layer sacrificial layer 110 extends in a second direction, the quantity of the groove 121 also increases, but
It is two rows groove arranged in the first direction, arrangement mode and knot shown in Fig. 4 are increased with existing structure repeated arrangement
Structure is identical.The extension of the i.e. described substrate 100 in a first direction is that the extension of same storage unit (certainly, meets storage unit
After size, the repeated arrangement of different storage units can also be, or the arrangement of different semiconductor device structures), described the
One substrate 100 is the repeated arrangement of different storage units in the extension of second direction, wherein between different storage unit by every
It is isolated (groove 230 in such as Fig. 4 can form isolation structure in the trench and form isolation structure) from structure, it certainly, can also
To be arranged with other semiconductor device structures.
Then execute step S203, form support portion 131 in the groove 121, the first layer sacrificial layer 120 with
First layer wall 140 is formed on the support portion 131, as shown in Figure 3 e.
Specifically, the insulating layer 130 fills up firstly, forming an insulating layer 130 on the first layer sacrificial layer 120
The groove 121 simultaneously covers the first layer sacrificial layer 120, as shown in Figure 3c.Then, the insulating layer 130 is carried out flat
Change, such as chemical mechanical grinding, until exposing the first layer sacrificial layer 120, is formed and be located in the first layer sacrificial layer 120
Support portion 131.
Preferably, the material of the insulating layer 130 includes but is not limited to silica.As an example, can be using chemical gas
Mutually deposition, atomic layer deposition or other suitable deposition methods form the insulating layer 130.
Then, it in the first layer sacrificial layer 110 and formation first layer wall 140 on the support portion 131, is formed such as
Structure shown in Fig. 3 e.The material of the first layer wall 140 is preferably silicon oxide layer.It preferably, can be using chemical gas
Mutually deposition, atomic layer deposition or other suitable deposition methods form the first layer wall 140.
It is understood that the support portion 121 can be formed with the first layer wall 140 in same step.
For example, directly forming the first layer of spacer material on the first layer sacrificial layer 110, first layer of spacer material is filled up described
Groove 121 simultaneously covers the first layer sacrificial layer 110 and has certain thickness, then carries out to first interval insulant flat
Change, retain first layer of spacer material of segment thickness as first layer wall 140, and is located in the groove 121
First layer of spacer material is as support portion.
Then step S204 is executed, sequentially forms second layer sacrificial layer 150 and second on the first layer wall 140
Interlayer interlayer 160, as illustrated in figure 3f.Material, thickness, the shape of the second layer sacrificial layer 150 and the first layer sacrificial layer 120
Can be identical at method etc., it is of course also possible to different, can also it is therein certain is one or more identical, need to illustrate
, do not need to form support portion in the second layer sacrificial layer 150.Likewise, the second layer wall 160 and institute
Material, thickness, the forming method etc. for stating first layer wall 140 can be identical, can also be with it is of course also possible to different
It is therein that certain is one or more identical.
Then step S205 is executed, sequentially forms third layer sacrificial layer 170 and third on the second layer wall 160
Interlayer interlayer 180 forms structure as illustrated in figure 3f.
Likewise, material, thickness, the forming method etc. of the third layer sacrificial layer 170 and the second layer sacrificial layer 150
Can be identical, it, can also therein certain be one or more identical it is of course also possible to different, it should be noted that in institute
It states and does not need to form support portion in third layer sacrificial layer 170.Likewise, the third layer wall 180 and the second layer
Material, thickness, forming method of wall 160 etc. can be identical, it is of course also possible to different, can also it is therein certain
It is one or more identical.
In finally formed structure as illustrated in figure 3f, support portion 131 is formed in first layer sacrificial layer 110, rear
Continuous removal sacrificial layer, forms metal layer in each wall, and during being etched back to metal layer, is located at bottom (i.e.
At first layer sacrificial layer position) first layer metal layer etched completely after, the support portion 131 is still located at described initial
Between wall 110 and first layer wall 140, it is used to support first layer wall 140 and each interlayer interlayer thereon, it can
Prevent collapsing for finally formed memory.
It is formed after the stacked structure 200, the forming method of the three dimensional NAND memory further includes forming channel junction
Structure forms groove, removes sacrificial layer by the groove, then forms metal layer between the wall and to the metal
Layer, which is etched back, waits subsequent steps, and the present invention is not defined subsequent step, introduces subsequent step simply below with clear
Chu illustrates the effect of the support portion 131.The subsequent step is specific as follows:
First step: performing etching the stacked structure 200, initial spacer layer 110 and the part substrate 100,
Multiple channel holes 210 are formed, as shown in figure 3g, channel structure 220 is then formed in the channel hole 210, forms such as Fig. 3 h
Shown in structure.
Specifically, forming a photoresist layer on the stacked structure 200, the photoresist layer is exposed and is shown
Shadow forms patterned photoresist layer, exposes the third wall 180 at the predetermined position for forming channel hole, then
Using the patterned photoresist layer as exposure mask, successively to described in the stacked structure 200, initial spacer layer 110 and part
Substrate 100 performs etching, and forms multiple channel through-holes 210.Preferably, dry etch process such as reactive plasma can be used
Etching technics etches the stacked structure 200, initial spacer layer 110 and the part substrate 100, to be formed through described
The channel hole 210 of stacked structure 200, initial spacer layer 110 and the part substrate 100, the channel hole 210 is perpendicular to institute
State substrate 100.Then channel structure 220 is formed in the channel hole 210.
It please refers to shown in Fig. 4 and Fig. 3 g, the channel structure 220 (that is, described channel hole 210), which is located at described in two rows, props up
Between support part 131 (that is, described groove 121), and the channel structure 220 is arranged in two rows.Preferably, the support portion 131
It is mutually staggered in this second direction with the channel structure 220.
Optionally, the groove 121 and the shape and size uniformity of the cross section in the channel hole 210 cause.The present embodiment
In, the groove 121 and the cross section in the channel hole 210 are square, a diameter of 60nm.
Second step performs etching the stacked structure 200, initial spacer layer 110 and the part substrate 100, shape
At multiple grooves 230, the groove 230 is located at side of the support portion 131 far from the channel 230, as shown in figure 3i；It is logical
It crosses the groove 230 and removes all sacrificial layers in the stacked structure 200, as shown in Fig. 3 j；The adjacent wall it
Between fill metal layer, form structure as shown in figure 3k.
Specifically, forming a photoresist layer on the stacked structure 200, the photoresist layer is exposed and is shown
Shadow forms patterned photoresist layer, exposes the third layer wall 180 at the predetermined position for forming groove, then
Using the patterned photoresist layer as exposure mask, successively to described in the stacked structure 200, initial spacer layer 110 and part
Substrate 100 performs etching, and forms groove 230.Preferably, dry etch process such as reactive plasma etching technics can be used
The stacked structure 200, initial spacer layer 110 and the part substrate 100 are etched, runs through the stacked structure to be formed
200, the groove 230 of initial spacer layer 110 and the part substrate 100, forms structure as shown in figure 3i.
It please refers to shown in Fig. 4 and Fig. 3 i, it is separate that the groove 230 is located at the groove 121 (that is, described support portion 131)
The side of the channel 220.Preferably, the groove 230 is in a strip shape, extends along the first direction.
Then, all sacrificial layers in the stacked structure 200 are removed using wet-etching technology.Wet etching solution is logical
It crosses the groove 230 in stacked structure 200 to enter inside stacked structure, be contacted with each layer sacrificial layer, to occur with it chemical anti-
It answers, is etched away, to form the hollow out stacked structure by wall interval, support portion 131 is located at the initial spacer layer
Between 110 and first layer wall 140, as shown in Fig. 3 j.
In the present embodiment, because the wet etching solution selected in wet-etching technology can touch sacrificial layer and interval
Layer, therefore, the wet etching solution of selection are different to the etch rate of sacrificial layer with wall, and preferably sacrificial layer is to wall
Select than be high selectivity ratio etching solution, i.e., silicon nitride to silica select ratio for high selectivity ratio etching solution.Together
When, wet etching solution is also required to difference, and preferably choosing of the sacrificial layer to support portion to the etch rate of sacrificial layer and support portion
It selects than the etching solution for high selectivity ratio, that is, silicon nitride selects than the etching solution for high selectivity ratio silica.For example,
Phosphoric acid solution.
Finally, filling metal layer between the adjacent wall, i.e., gold is filled to the hollowed out area of hollow out stacked structure
Belong to medium, forms each layer metal layer.It, can be by chemical vapor deposition method or Atomic layer deposition method to engraving in the present embodiment
Fill metal medium in the hollowed out area of empty stacked structure.In addition, generally using low temperature to improve the filling capacity of metal medium
Chemical vapor deposition method fills metal medium.Preferably, metal medium can be tungsten.
In the present embodiment, first layer gold is formed between the initial spacer layer 110 and the first layer wall 140
Belong to layer 191, forms second layer metal layer 192 between the first layer wall 140 and the second layer wall 160,
Third layer metal layer 193 is formed between the second layer wall 160 and third layer wall 180, and in the support portion
131 are located in the first layer metal layer 191.
Third step is etched back the metal layer, so that aperture of the groove 230 in the metal layer is big
In the aperture in the wall, as shown in Fig. 3 l.
Preferably, each layer metal layer is etched back using wet-etching technology, is sent out to avoid between each layer metal layer
Raw contact.Wet etching solution is entered inside stacked structure by groove 230, is contacted with each layer metal layer, to occur with it
Chemical reaction, etched portions metal layer.But it is tied since wet etching solution can be largely gathered in the stacking by gravity
Structure bottom, so that inevitably over etching is caused to the first layer metal layer 191 of bottom, in order to guarantee that the groove 230 exists
Aperture in every layer of metal layer is all larger than the aperture in the wall, it is possible to will cause the first layer metal layer 191
It is etched completely, as shown in Fig. 3 l.
In this case, it due to the supporting role of the support portion 131, can be supported to avoid stacked structure due to lacking
Collapse caused by and, to avoid collapsing for memory.
Certainly, after carrying out being etched back to of metal layer, further includes: the encapsulant layer in the groove 230, due to this
Step and subsequent step belong to the prior art, and the present invention repeats no more this.
The forming method of three dimensional NAND memory provided by the present invention forms sacrificial layer and wall in substrate 100
Alternately stacked stacked structure 200, the shape in the first layer sacrificial layer 120 of the close substrate 100 in the stacked structure 200
At multiple grooves 121, the groove 121 exposes the substrate 100, and support portion 131, institute are formed in the groove 121
It states support portion 131 and is used to support each interlayer interlayer disposed thereon, collapsing for memory can be prevented.
Further, after sacrificial layer of the removal between each interlayer interlayer, metal is formed between each interlayer interlayer
Layer is provided with support portion 131 in the first layer metal layer 191 of substrate 100, in the process being etched back to metal layer
In, the first layer metal layer 191 positioned at bottom is inevitably by over etching, the branch being now placed in first layer metal layer 191
Support layer 131 is played a supporting role, so as to avoid falling for the memory as caused by the over etching of first layer metal layer 191
It collapses.
Correspondingly, being formed using method as described above the present invention also provides a kind of three dimensional NAND memory, please referring to figure
Shown in 3l and Fig. 4, the three dimensional NAND memory includes:
Substrate 100, the stacked structure 200 in the substrate 100；
Wherein, the stacked structure 200 includes alternately stacked metal layer and wall, and close to the substrate 100
First layer metal layer 191 in be formed with multiple support portions 131.
Further, the three dimensional NAND memory further include: be located at the substrate 100 and the stacked structure 200 it
Between initial spacer layer 110.
Further, the three dimensional NAND memory further include: through the stacked structure 200, initial spacer layer 110 and
The channel structure 220 of the part substrate.
Further, multiple support portions 131 in the first layer metal layer 191 arrange in a row, the ditch
Road structure 220 is located between support portion 131 described in two rows, and the channel structure 220 is arranged in two rows, and capable extending direction is
First direction.
Further, the support portion 131 mutually staggers in this second direction with the channel structure 220, described
Second direction is vertical with the first direction.
In conclusion sacrificial layer is formed on the substrate in three dimensional NAND memory provided by the invention and forming method thereof
With the alternately stacked stacked structure of wall, formed in the first layer sacrificial layer of the substrate in the stacked structure more
A groove, the groove exposes the substrate, and forms support portion in the groove, and the support portion, which is used to support, to be located at
Each interlayer interlayer thereon, can prevent collapsing for memory.
Further, after sacrificial layer of the removal between each interlayer interlayer, metal is formed between each interlayer interlayer
Layer is provided with support portion in the first layer metal layer of substrate, during being etched back to metal layer, first layer gold
Belong to layer inevitably by over etching, the supporting layer being now placed in first layer metal layer is played a supporting role, so as to keep away
Exempt from collapsing for the memory as caused by the over etching of first layer metal layer.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (16)
1. a kind of forming method of three dimensional NAND memory characterized by comprising
One substrate is provided；
Sacrificial layer and the alternately stacked stacked structure of wall are formed on the substrate, close to described in the stacked structure
Multiple grooves are formed in the first layer sacrificial layer of substrate, the groove exposes the substrate, and forms branch in the groove
Support part.
2. the forming method of three dimensional NAND memory as described in claim 1, which is characterized in that form the side of the support portion
Method includes:
Form an insulating layer on the first layer sacrificial layer, the insulating layer fills up the groove and to cover the first layer sacrificial
Domestic animal layer；
The insulating layer is planarized, until exposing the first layer sacrificial layer, forms support portion in the groove.
3. the forming method of three dimensional NAND memory as described in claim 1, which is characterized in that form the side of the support portion
Method includes: that a layer of spacer material is formed on the first layer sacrificial layer, and the layer of spacer material is filled up the groove and covered
The first layer sacrificial layer, forms support portion in the groove；
The layer of spacer material is planarized, first layer wall is formed.
4. the forming method of three dimensional NAND memory as described in claim 1, which is characterized in that forming the stacked structure
Before, the forming method of the three dimensional NAND memory further include: form initial spacer layer on the substrate.
5. the forming method of three dimensional NAND memory as described in claim 1, which is characterized in that formed the stacked structure it
Afterwards, the forming method of the three dimensional NAND memory further include:
Multiple channel holes are formed, the stacked structure is run through in the channel hole, and stops in the substrate；
Channel structure is formed in the channel hole.
6. the forming method of three dimensional NAND memory as claimed in claim 5, which is characterized in that be located at the first layer sacrifice
Multiple grooves in layer are arranged in two rows, and the channel hole is located between groove described in two rows, and the channel hole is arranged in
Two rows, capable extending direction are first direction.
7. the forming method of three dimensional NAND memory as claimed in claim 6, which is characterized in that the groove and the channel
Hole mutually staggers in a second direction, and the second direction is vertical with the first direction.
8. the forming method of three dimensional NAND memory as claimed in claim 7, which is characterized in that the groove and the channel
The shape and size of the cross section in hole are consistent.
9. the forming method of three dimensional NAND memory as claimed in claim 7, which is characterized in that formed the channel structure it
Afterwards, the forming method of the three dimensional NAND memory further include:
The stacked structure and the part substrate are performed etching, groove is formed, the groove is located at the groove far from institute
State the side in channel hole；
The sacrificial layer in the stacked structure is removed by the groove；
Metal layer is filled between the adjacent wall.
10. the forming method of three dimensional NAND memory as claimed in claim 9, which is characterized in that fill the metal layer it
Afterwards, the forming method of the three dimensional NAND memory further include:
The metal layer is etched back, so that the groove is greater than in the wall in the aperture in the metal layer
Aperture.
11. the forming method of three dimensional NAND memory as claimed in claim 10, which is characterized in that the groove is in a strip shape,
It is extended in a first direction.
12. the forming method of the three dimensional NAND memory as described in any one of claim 1~11, which is characterized in that described
The material of wall is silica, and the material of the sacrificial layer is silicon nitride, and the material of the support portion is silica.
13. a kind of three dimensional NAND memory characterized by comprising
Substrate, the stacked structure in the substrate；
Wherein, the stacked structure includes alternately stacked metal layer and wall, and close to the first layer of substrate gold
Belong in layer and is formed with multiple support portions.
14. the forming method of three dimensional NAND memory as claimed in claim 13, which is characterized in that the three dimensional NAND storage
Device further include: through the channel structure of the stacked structure and the part substrate.
15. the forming method of three dimensional NAND memory as claimed in claim 14, which is characterized in that be located at the first layer gold
The multiple support portions belonged in layer are arranged in two rows, and the channel structure is located between support portion described in two rows, and the channel junction
Structure is arranged in two rows, and capable extending direction is first direction.
16. the forming method of three dimensional NAND memory as claimed in claim 15, which is characterized in that the support portion with it is described
Channel structure mutually staggers in a second direction, and the second direction is vertical with the first direction.
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Application publication date: 20190816 |