CN110136911A - Loop construction and preparation method thereof - Google Patents
Loop construction and preparation method thereof Download PDFInfo
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- CN110136911A CN110136911A CN201810106958.7A CN201810106958A CN110136911A CN 110136911 A CN110136911 A CN 110136911A CN 201810106958 A CN201810106958 A CN 201810106958A CN 110136911 A CN110136911 A CN 110136911A
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- 238000010276 construction Methods 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000010410 layer Substances 0.000 claims description 77
- 238000000034 method Methods 0.000 claims description 27
- 238000005516 engineering process Methods 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000005422 blasting Methods 0.000 claims description 9
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 8
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 5
- 239000001569 carbon dioxide Substances 0.000 claims description 5
- 239000002356 single layer Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- -1 polyethylene terephthalate Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004698 Polyethylene Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
- H01F41/042—Printed circuit coils by thin film techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F5/00—Coils
- H01F5/003—Printed circuit coils
Abstract
The present invention provides a kind of loop construction and preparation method thereof, and the loop construction includes substrate and first coil circuit.Substrate has first surface.First coil loop configuration is on the first surface of substrate, and wherein first coil circuit includes being connected with each other with multiple coils of forming circuit, and substrate of the conducting wire section of each coil between up-narrow and down-wide trapezoidal and adjacent coil is recessed with V word.
Description
Technical field
The present invention relates to a kind of loop constructions and preparation method thereof.
Background technique
With scientific and technological continuous progress, on the market the mobile phone such as digital camera or with camera function, electronic game Game device,
PDA ... waits image acquiring devices increasingly universalness, and having can be with clapping the facilitating functions that see, it has also become masses are in daily life
It is used to record the portable tool of things in living or work.
However, in order to easy to carry, consumer requires towards light and short the size of photographic means, thus how into
The rigidity of coil dimension and maintenance substrate that one step reduces in photographic means is still this field problem to be solved.
Summary of the invention
The present invention provides a kind of loop construction, with lesser line width and line-spacing.
The present invention provides a kind of production method of loop construction, can produce the coil knot with lesser line width and line-spacing
Structure.
Loop construction of the invention includes substrate and first coil circuit.Substrate has first surface.First coil circuit
It is configured on the first surface of substrate, wherein first coil circuit includes being connected with each other with multiple coils of forming circuit, each line
Substrate of the conducting wire section of circle between up-narrow and down-wide trapezoidal and adjacent coil is recessed with V word.
In one embodiment of this invention, the size difference between above-mentioned trapezoidal top and bottom is between 5%-
25%.
In one embodiment of this invention, the depth of above-mentioned V word recess is greater than 3 microns.
In one embodiment of this invention, further include the first protective layer, be configured on first coil circuit.
It in one embodiment of this invention, further include the second wire loop, wherein the second wire loop is configured at substrate
On the second surface being oppositely arranged with first surface, and first coil circuit and the second wire loop are electrically connected.
It in one embodiment of this invention, further include the through-hole being configured in substrate, wherein first coil circuit and second
Wire loop is electrically connected via through-hole.
In one embodiment of this invention, further include the second protective layer, be configured on the second wire loop.
The production method of loop construction of the invention includes the following steps.It is conductive that first is formed on the first surface of the substrate
Layer.The second conductive layer is formed on the second surface of substrate, wherein second surface is opposite with first surface.It is formed in a substrate logical
Hole.Blasting craft, laser technology or plasma process are carried out to the first conductive layer, to remove the first conductive layer of part and part
Substrate, so that the first left conductive layer includes first coil circuit.Blasting craft, laser technology are carried out to the second conductive layer
Or plasma process, to remove the second conductive layer of part and part substrate, so that the second left conductive layer includes second
Wire loop, wherein first coil circuit is electrically connected with the second wire loop via through-hole.
In one embodiment of this invention, above-mentioned laser technology includes carbon dioxide (CO2) laser technology, ultraviolet light
(UV) laser technology or picosecond (PICO) laser technology.
In one embodiment of this invention, above-mentioned the first left conductive layer further includes and first coil circuit electrical property
First nubbin of insulation.
In one embodiment of this invention, above-mentioned the second left conductive layer further includes and the second wire loop electrical property
Second nubbin of insulation.
It in one embodiment of this invention, further include that the first protective layer is formed on first coil circuit.
It in one embodiment of this invention, further include that the second protective layer is formed on the second wire loop.
In one embodiment of this invention, the forming method of above-mentioned through-hole includes: to form perforation in a substrate;And
Through-hole is formed in perforation.
In one embodiment of this invention, above-mentioned first coil circuit includes being connected with each other with multiple lines of forming circuit
Circle, the conducting wire section of each coil are up-narrow and down-wide trapezoidal.
In one embodiment of this invention, above-mentioned first coil circuit includes being connected with each other with multiple lines of forming circuit
It encloses, the substrate between adjacent coil is recessed with V word.
In one embodiment of this invention, the second above-mentioned wire loop includes being connected with each other with multiple lines of forming circuit
Circle, the conducting wire section of each coil are up-narrow and down-wide trapezoidal.
In one embodiment of this invention, the second above-mentioned wire loop includes being connected with each other with multiple lines of forming circuit
It encloses, the substrate between adjacent coil is recessed with V word.
Based on above-mentioned, in embodiments of the present invention, pass through blasting craft, laser technology or plasma process and remove part
Conductive layer, there is the wire loop of smaller line width and line-spacing in formation on substrate.In this way, can substantially reduce wire loop
Volume, with limited substrate surface product under increase coil circle number.In addition, above-mentioned technique is also other than forming wire loop
It can be further in the remaining conductive layer retained on substrate and wire loop insulate.In this way, the rigidity of substrate can be promoted, with
It avoids occurring phenomena such as warpage (warpage) occurs.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Figure 1A to Fig. 1 D is the diagrammatic cross-section according to a kind of production method of loop construction of one embodiment of the invention;
Fig. 2A and Fig. 2 B is the upper schematic diagram according to a kind of loop construction of one embodiment of the invention respectively;
Fig. 3 is the upper schematic diagram according to a kind of loop construction of one embodiment of the invention;
Fig. 4 is the upper schematic diagram according to a kind of loop construction of one embodiment of the invention.
Specific embodiment
Figure 1A to Fig. 1 D is the diagrammatic cross-section according to a kind of production method of loop construction of one embodiment of the invention.
Fig. 2A and Fig. 2 B is the upper schematic diagram according to a kind of loop construction of one embodiment of the invention respectively.Figure 1A is please referred to,
The first conductive layer 104 is formed on the first surface 102a of substrate 102.In the present embodiment, substrate 102 is, for example, flexible base plate
Or hard substrate, wherein the material of flexible base plate is, for example, polyethylene terephthalate (Polyethylene
Terephthalate, PET), polyethylene (polyethylene, PE), polyimides (polyimide, PI) or other are suitable
Material, the material of hard substrate is for example including metal base, ceramics, FR-4, FR-5 or bismaleimide
(Bismaleimide-Triazine, BT), epoxy resin, glass fibre or other suitable materials.The thickness example of substrate 102
25 microns to 150 microns in this way.In the present embodiment, the material of the first conductive layer 104 for example including titanium copper composite layer, copper, titanium,
Palladium, silver, nickel, tin etc. or one of its Suo Zu group.The thickness of first conductive layer 104 is, for example, 12 microns -35 microns.First is conductive
The forming method of layer 104 is, for example, chemical plating, plating or other suitable methods.
It in the present embodiment, further include that the second conductive layer 106 is formed on the second surface 102b of substrate 102, wherein
Two surface 102b are opposite with first surface 102a.Material, thickness and the forming method of second conductive layer 106 are referred to first
Described in conductive layer 104, do not repeated in this.In other embodiments, substrate 102 is also possible to be formed with the first conductive layer
104 and second conductive layer 106 (metal foils such as copper foil) commercially available substrate.
Figure 1B is please referred to, then, forms through-hole 112, in substrate 102 to be electrically connected the first conductive layer 104 and second
Conductive layer 106.In the present embodiment, the method for forming through-hole 112 includes the following steps.Firstly, perforation 110 is formed, to run through
First conductive layer 104, the second conductive layer 106 and positioned at substrate 102 between the two.In the present embodiment, the shape of perforation 110
It is, for example, machine drilling, laser drill or other suitable methods at method.The diameter of perforation 110 is, for example, 50 microns to 200
Micron.Then, electroplating technology is carried out to substrate 102, in formation through-hole 112 on the side wall of perforation 110.In the present embodiment,
Through-hole 112 be, for example, through-hole ring, formed perforation 110 side wall in but unfilled perforation 110.In the present embodiment, through-hole
The thickness of ring is, for example, to be greater than 3 microns.The material of through-hole 112 for example including titanium copper composite layer, copper, titanium, palladium, silver, nickel, tin etc. or
One of its Suo Zu group.
In the present embodiment, electroplating technology can for example increase the thickness of the first conductive layer 104 and the second conductive layer 106 simultaneously
Degree, in other words, the first conductive layer of part 104, the second conductive layer of part 106 and through-hole 112 are formed together.In another embodiment
Middle (not shown) can apply mask layer on the first conductive layer 104 and the second conductive layer 106, such as when forming through-hole 112
This can be acted on the first conductive layer 104 and the second conductive layer 106 simultaneously to avoid electroplating technology, to keep the first conductive layer
104 and second conductive layer 106 script thickness.In the present embodiment, be with prior to formed on substrate 102 first conductive layer 104,
Second conductive layer 106, for re-forming perforation 110, but invention is not limited thereto, in other embodiments, can also be prior to
Perforation 110 is formed in substrate 102, then is formed simultaneously the first conductive layer 104, the second conductive layer 106 and through-hole 112.
Referring to Fig. 1 C and Fig. 2A, then, to the first conductive layer 104 carry out blasting craft, laser technology or wait from
Plasma process, to remove the first conductive layer of part 104, so that the first left conductive layer 104 includes first coil circuit
120.Specifically, pattern definition trace is initially formed, between this pattern definition trace is formed between subsequent first coil circuit 120
It is conductive then to remove first according to pattern definition trace with blasting craft, laser technology or plasma process by gap g (spacer)
Layer 104 and substrate 102 below, so that the first left conductive layer 104 includes first coil circuit 120.In this implementation
In example, laser technology includes carbon dioxide (CO2) laser technology, ultraviolet light (UV) laser technology or picosecond (PICO) laser work
Skill.First coil circuit 120 and through-hole 112 are electrically connected.In the present embodiment, first coil circuit 120 has beginning point
120a and end point 120b, and including being connected with each other with multiple coils 122 of forming circuit.In the present embodiment, beginning point
120a is, for example, the outside for being located at first coil circuit 120, and end point 120b is, for example, the inside for being located at first coil circuit 120
And it is located on through-hole 112, but invention is not limited thereto.It furthermore in the present embodiment, further include being formed and first coil circuit
120 weld pads 128 being electrically connected.
In the present embodiment, as shown in Figure 2 A, the conducting wire section of coil 122 is up-narrow and down-wide trapezoidal and adjacent
Substrate 102 between coil 122 has V word recess 124.In the present embodiment, the top 122a and bottom 122b of coil 122 it
Between size difference between 5%-25%.The line width w of coil 122 is, for example, 20 microns -35 microns.The V word recess of substrate 102
Depth d is, for example, to be greater than 3 microns.Line-spacing g between coil 122 is, for example, less than 13 microns.
In the present embodiment, the first left conductive layer 104 e.g. further includes electrically exhausted with first coil circuit 120
First nubbin 126 of edge.In the present embodiment, the first nubbin 126 can be located at the outermost of first coil circuit 120
There is gap on the outside of coil 122 and between top outer coil 122.Similarly, the first nubbin 126 can also be located at First Line
It encloses 122 inside of most interior loop in circuit 120 and there is gap between most interior loop 122.In addition, in the present embodiment, first
Nubbin 126 may be located between most interior loop 122 and through-hole 112, and the first nubbin 126 and most interior loop 122
Between and the first nubbin 126 and through-hole 112 between all have gap.Wherein, the substrate 102 below aforementioned gap also has
V word recess 124.It should be noted that the present invention does not limit position, area, the shape etc. of the first nubbin 126.
In addition, in other embodiments, also can be omitted the configuration of the first nubbin 126.
Referring to Fig. 1 C and Fig. 2 B, in the present embodiment, blasting craft, laser work are carried out to the second conductive layer 106
Skill or plasma process, to remove the second conductive layer of part 106, so that the second left conductive layer 106 includes the second line
Circuit 130 is enclosed, wherein first coil circuit 120 and the second wire loop 130 are electrically connected via through-hole 112.Second coil returns
The forming method on road 130 can be identical as first coil circuit 120, does not repeat in this.In the present embodiment, the second wire loop
130 have beginning point 130a and end point 130b, and including being connected with each other with multiple coils 132 of forming circuit.In this implementation
In example, beginning point 130a is, for example, to be located at the inside of the second wire loop 130 and be located under through-hole 112, therefore the second coil returns
The beginning point 130a on road 130 is electrically connected by through-hole 112 and the end point 120b in first coil circuit 120.End point 130b
E.g. it is located at the outside of the second wire loop 130, but invention is not limited thereto.In the present embodiment, the conducting wire of coil 132
Substrate 102 of the section between up-narrow and down-wide trapezoidal and adjacent coil 132 has V word recess 134.In the present embodiment
In, be by taking the coil 132 of the coil 122 in first coil circuit 120 and the second wire loop 130 is partially overlapped by each other as an example, but
Invention is not limited thereto, and in other embodiments, coil 122 can also be interlaced with each other with coil 132 or be aligned, similarly, V
Word recess 124 and V word be recessed 134 can also it is interlaced with each other, be aligned or partly overlap.The line width of coil 132, line-spacing and V word are recessed
Sunken depth is referred to described previously, does not repeat in this.It furthermore in the present embodiment, further include forming and the second line
Enclose the weld pad 138 that circuit 130 is electrically connected.
In the present embodiment, the second left conductive layer 106 e.g. further includes electrically exhausted with the second wire loop 130
Second nubbin 136 of edge.The forming method of second nubbin 136 is referred to residual described previously for first with configuration mode
Described in remaining part point 126, do not repeated in this.It should be noted that the present invention not position to the second nubbin 136, area, shape
Shape etc. limits.In addition, in other embodiments, also can be omitted the configuration of the second nubbin 136.
It illustrates, in order to which attached drawing understands and illustrates that conveniently the present embodiment is with the only shape on a surface of substrate
For a wire loop and a weld pad, but invention is not limited thereto, in other words, can according to demand, on substrate
The wire loop and weld pad of number and required density needed for being formed.
Fig. 1 D is please referred to, in the present embodiment, forms the first protective layer 140 on first coil circuit 120 to cover
One wire loop 120 forms the second protective layer 141 to cover the second wire loop 130, so on the second wire loop 130
Complete the production of two-sided inductance single layer substrate 100.The forming method of first protective layer 140 and the second protective layer 141 includes coating
Method.The material of first protective layer 140 and the second protective layer 141 can be polyimides or other suitable insulating materials.At other
In embodiment, the first protective layer 140 and the second protective layer 141 can be inserted in through-hole 112.In other words, through-hole 112 can be kept
It is hollow or at least partly insert insulating materials.Then, it can be formed and electrically be connected with the beginning in first coil circuit 120 point 120a respectively
The terminal (not shown) that the end point 130b of the terminal (not shown) and the second wire loop 130 that connect is electrically connected.
It in the above-described embodiment, is to be with duolateral coil circuit (referred to as two-sided inductance single layer substrate) with single layer substrate
Example, but invention is not limited thereto.It in other embodiments, can also be only in forming wire loop on a surface of substrate.This
Outside, in order to achieve the purpose that more high inductance value, the two-sided inductance single layer substrate above-mentioned of stackable multi-disc.For example, such as Fig. 3
It is shown (difference of the two-sided inductance single layer substrate 100 of two-sided inductance single layer substrate 100A, 100B and Fig. 1 D in Fig. 3 be in
The nubbin 126,136) that configuration edge is omitted in two-sided inductance single layer substrate 100A, 100B, can stack above and below with aforementioned
Two-sided inductance single layer substrate 100A, 100B of structure and in wherein configure insulating layer 150, then it is pressed to patch.And
Afterwards, through-hole 152 can be formed in insulating layer 150, make the second wire loop 130 and two-sided electricity of two-sided inductance single layer substrate 100A
The first coil circuit 120 for feeling single layer substrate 100B is connected to be electrically connected to each other.Similarly, it can be formed in insulating layer 150
Through-hole 153 makes the First Line of the second wire loop 120 and two-sided inductance single layer substrate 100B of two-sided inductance single layer substrate 100A
The conducting of circuit 130 is enclosed to be electrically connected to each other.Wherein, through-hole 152,153 can be the conducting structures such as connection pad, conducting wire.Furthermore not
Two-sided 100 number of inductance single layer substrate of stacking is limited, abovementioned steps can be repeated until reaching requirement
Until.In one embodiment, insulating layer 150 is possible to insert into through-hole 112.In one embodiment, pass through above-mentioned stacking
The overall thickness of line layer is formed by e.g. less than 200 microns, or less than 150 microns.
On the other hand, route increasing layer can also be carried out to two-sided inductance single layer substrate 100.In detail, as shown in figure 4,
Can press on the first protective layer 140 of two-sided inductance single layer substrate 100 and the second protective layer 141 respectively has conductive layer
164,166 pressing glue 160,162.Then, wire loop technique above-mentioned can be carried out to conductive layer 164,166, to form line
Enclose circuit 168,170.Wherein, first coil circuit 120 and wire loop 168 e.g. is connected with each other by through-hole 172
It is electrically connected, and, for example, is that the second wire loop 130 is connected electrically to connect each other with wire loop 170
It connects.Furthermore the number of increasing layer is not limited, can repeat abovementioned steps up to reaching required route layer number is
Only.In one embodiment, pressing glue 160,162 is possible to insert into through-hole 112.In one embodiment, pass through above-mentioned line
Road increasing layer is formed by the overall thickness of line layer e.g. less than 200 microns, or less than 150 microns.
In conclusion in embodiments of the present invention, removing part by blasting craft, laser technology or plasma process
Conductive layer, there is the wire loop of smaller line width and line-spacing in formation on substrate.In this way, can substantially reduce wire loop
Volume, with limited substrate surface product under increase coil circle number.In addition, above-mentioned technique is also other than forming wire loop
It can be further in the remaining conductive layer retained on substrate and wire loop insulate.In this way, the rigidity of substrate can be promoted, with
It avoids occurring phenomena such as warpage (warpage) occurs.Furthermore it can be by stacking the substrate with above-mentioned wire loop either
Increasing layer step is carried out to the substrate with above-mentioned wire loop, required loop construction can be so formed, to be widely used in
Camera etc. needs in the device of small size coil.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention
Range is subject to view as defined in claim.
Claims (18)
1. a kind of loop construction characterized by comprising
Substrate has first surface;And
First coil circuit is configured on the first surface of the substrate, wherein the first coil circuit includes each other
Multiple coils in circuit are connected to form, the conducting wire section of each coil is the up-narrow and down-wide trapezoidal and adjacent line
The substrate between circle is recessed with V word.
2. loop construction according to claim 1, wherein size difference between the trapezoidal top and bottom between
5%-25%.
3. loop construction according to claim 1, wherein the depth of V word recess is greater than 3 microns.
4. loop construction according to claim 1 further includes the first protective layer, it is configured on the first coil circuit.
5. loop construction according to claim 1 further includes the second wire loop, wherein second wire loop configures
In on the second surface of the substrate being oppositely arranged with the first surface, and the first coil circuit and second line
Circuit is enclosed to be electrically connected.
6. loop construction according to claim 5 further includes the through-hole being configured in the substrate, wherein the First Line
Circle circuit and second wire loop are electrically connected via the through-hole.
7. loop construction according to claim 5 further includes the second protective layer, it is configured on second wire loop.
8. a kind of production method of loop construction characterized by comprising
The first conductive layer is formed on the first surface of the substrate;
The second conductive layer is formed on the second surface of the substrate, wherein the second surface is opposite with the first surface;
Through-hole is formed in the substrate;
Blasting craft, laser technology or plasma process are carried out to first conductive layer, led with removing part described first
Electric layer and the part substrate, so that left first conductive layer includes first coil circuit;And
Blasting craft, laser technology or plasma process are carried out to second conductive layer, led with removing part described second
Electric layer and the part substrate, so that left second conductive layer includes the second wire loop, wherein the First Line
Circle circuit and second wire loop are electrically connected via the through-hole.
9. the production method of loop construction according to claim 8, wherein the laser technology includes carbon dioxide laser
Technique, ultraviolet laser technique or picosecond laser technique.
10. the production method of loop construction according to claim 8, wherein left first conductive layer further includes
The first nubbin being electrically insulated with the first coil circuit.
11. the production method of loop construction according to claim 8, wherein left second conductive layer further includes
The second nubbin being electrically insulated with second wire loop.
12. the production method of loop construction according to claim 8 further includes forming on the first coil circuit
One protective layer.
13. the production method of loop construction according to claim 8 further includes forming on second wire loop
Two protective layers.
14. the production method of loop construction according to claim 8, wherein the forming method of the through-hole includes:
Perforation is formed in the substrate;And
The through-hole is formed in the perforation.
15. the production method of loop construction according to claim 8, wherein the first coil circuit includes being connected with each other
With multiple coils of forming circuit, the conducting wire section of each coil is up-narrow and down-wide trapezoidal.
16. the production method of loop construction according to claim 8, wherein the first coil circuit includes being connected with each other
With multiple coils of forming circuit, the substrate between the adjacent coil is recessed with V word.
17. the production method of loop construction according to claim 8, wherein second wire loop includes being connected with each other
With multiple coils of forming circuit, the conducting wire section of each coil is up-narrow and down-wide trapezoidal.
18. the production method of loop construction according to claim 8, wherein second wire loop includes being connected with each other
With multiple coils of forming circuit, the substrate between the adjacent coil is recessed with V word.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201810106958.7A CN110136911A (en) | 2018-02-02 | 2018-02-02 | Loop construction and preparation method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201810106958.7A CN110136911A (en) | 2018-02-02 | 2018-02-02 | Loop construction and preparation method thereof |
Publications (1)
Publication Number | Publication Date |
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CN110136911A true CN110136911A (en) | 2019-08-16 |
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ID=67567298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201810106958.7A Pending CN110136911A (en) | 2018-02-02 | 2018-02-02 | Loop construction and preparation method thereof |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1459116A (en) * | 2001-03-08 | 2003-11-26 | 松下电器产业株式会社 | Inductor part, and method of producing the same |
CN1175716C (en) * | 1996-07-18 | 2004-11-10 | 纳格雷股份有限公司 | Method for making printed circuits and resulting printed circuit |
US20120086537A1 (en) * | 2010-10-07 | 2012-04-12 | Touch Micro-System Technology Corp. | Planar coil and method of making the same |
CN104105353A (en) * | 2014-07-02 | 2014-10-15 | 华中科技大学 | Preparation method of high-accuracy ceramic printed circuit board |
CN104244614A (en) * | 2013-06-21 | 2014-12-24 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board and manufacturing method thereof |
CN104733154A (en) * | 2013-12-18 | 2015-06-24 | 三星电机株式会社 | Chip electronic component and manufacturing method thereof |
CN106252037A (en) * | 2013-08-02 | 2016-12-21 | 乾坤科技股份有限公司 | Method for manufacturing multilayer coil and magnetic device |
-
2018
- 2018-02-02 CN CN201810106958.7A patent/CN110136911A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1175716C (en) * | 1996-07-18 | 2004-11-10 | 纳格雷股份有限公司 | Method for making printed circuits and resulting printed circuit |
CN1459116A (en) * | 2001-03-08 | 2003-11-26 | 松下电器产业株式会社 | Inductor part, and method of producing the same |
US20120086537A1 (en) * | 2010-10-07 | 2012-04-12 | Touch Micro-System Technology Corp. | Planar coil and method of making the same |
CN104244614A (en) * | 2013-06-21 | 2014-12-24 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board and manufacturing method thereof |
CN106252037A (en) * | 2013-08-02 | 2016-12-21 | 乾坤科技股份有限公司 | Method for manufacturing multilayer coil and magnetic device |
CN104733154A (en) * | 2013-12-18 | 2015-06-24 | 三星电机株式会社 | Chip electronic component and manufacturing method thereof |
CN104105353A (en) * | 2014-07-02 | 2014-10-15 | 华中科技大学 | Preparation method of high-accuracy ceramic printed circuit board |
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