CN110112271A - A kind of bottom has the LED epitaxial structure and preparation method thereof of recessed nano graph - Google Patents
A kind of bottom has the LED epitaxial structure and preparation method thereof of recessed nano graph Download PDFInfo
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- CN110112271A CN110112271A CN201910516550.1A CN201910516550A CN110112271A CN 110112271 A CN110112271 A CN 110112271A CN 201910516550 A CN201910516550 A CN 201910516550A CN 110112271 A CN110112271 A CN 110112271A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
Abstract
The application provides a kind of LED epitaxial structure and preparation method thereof of the bottom with recessed nano graph, the bottom has the LED epitaxial structure of recessed nano graph, including Sapphire Substrate and the buffer layer set gradually positioned at the sapphire substrate surface, concave nano graph layer, non-doped layer, the first type semiconductor layer, multiple quantum well layer and the second type semiconductor layer；Wherein, due to the presence of concave nano graph layer, the stress due to lattice mismatch and the big generation of thermal mismatching between GaN and Sapphire Substrate can be discharged, epitaxy defect is reduced to improve the lattice quality of LED and increases the internal quantum efficiency of LED.In addition, concave nano graph layer part covers buffer layer, in concave nano graph layer manufacturing process, it is formed using nanometer embossing, is stamped into exposed local buffer layer, the direction of the light issued from multiple quantum well layer can be changed in this way, total reflection is reduced, to improve the external quantum efficiency of LED.
Description
Technical field
The present invention relates to the LED extensions that semiconductor devices production field more particularly to a kind of bottom have recessed nano graph
Structure and preparation method thereof.
Background technique
LED is a kind of energy-conserving light source, and with the continuous improvement of light emitting diode (LED) luminous efficiency, LED can replace white
The status of vehement lamp.LED has been widely used for mobile phone backlight, LCD screen backlight, signal lamp, construction landscape, special lighting
Equal fields, and increasingly expanded to fields such as general lighting, automotive lightings.
GaN and its alloy are one of current most promising semiconductor materials, forbidden bandwidth distribution from 1.95eV to
6.2eV, can prepare the photophore from visible light to ultraviolet band, and group Ⅱ-Ⅵ compound semiconductor is full because of high-temperature stability and height
It is had been to be concerned by more and more people with mobility, GaN base blue green LED has been commercialized, and in stability and highlights
Aspect has been achieved for breakthrough, however still has the lower problem of LED internal quantum efficiency.
Summary of the invention
In view of this, the present invention provides a kind of LED epitaxial structure and preparation method thereof of the bottom with recessed nano graph, with
Solve the problems, such as that LED internal quantum efficiency is lower in the prior art.
To achieve the above object, the invention provides the following technical scheme:
A kind of bottom has the LED epitaxial structure of recessed nano graph, comprising:
Sapphire Substrate；
In the Sapphire Substrate, received along buffer layer, the concave set gradually away from the Sapphire Substrate direction
Rice graph layer, non-doped layer, the first type semiconductor layer, multiple quantum well layer and the second type semiconductor layer；
Wherein, buffer layer described in the concave nano graph layer covering part, the thickness of the concave nano graph layer are small
In or equal to the non-doped layer thickness, and the material of the concave nano graph layer be silica.
Preferably, projected outline widest part width of the concave nano graph layer in the Sapphire Substrate is
180nm~280nm, including endpoint value.
Preferably, the concave nano graph layer in the direction perpendicular to the Sapphire Substrate with a thickness of 50nm~
200nm, including endpoint value；The transverse and longitudinal ratio of the concave nano graph layer is greater than or equal to 1.
Preferably, the concave nano graph layer is formed using nanometer embossing.
Preferably, the concave structure of the concave nano graph layer is that hemispherical groove, cone-shaped groove or inverted trapezoidal are recessed
Slot.
Preferably, the surface density range of the concave nano graph layer is 5*108cm-2~9*108cm-2, including endpoint value.
Preferably, the material of the buffer layer is AlN；Or the buffer layer is the laminated construction of AlGaN layer with AlN layers.
Preferably, the Sapphire Substrate is graphical sapphire substrate or sapphire plain film substrate.
The present invention also provides the LED epitaxial structure production methods that a kind of bottom has recessed nano graph, comprising:
Substrate is provided；
Buffer layer is formed over the substrate；
Concave nano graph layer is formed on the buffer layer, is buffered described in the concave nano graph layer covering part
Layer；
Non-doped layer is formed on the concave nano graph layer；
The first type semiconductor layer, multiple quantum well layer and the second type semiconductor layer are sequentially formed on the non-doped layer.
Preferably, described that concave nano graph layer is formed on the buffer layer, it specifically includes:
Silicon dioxide thin film growth；
Template is processed, the template is for imprinting the groove structure for forming concave nano graph layer；
Pattern transfer, forms photoresist on the silica membrane, by the pattern transfer in the template described in
On photoresist；
Solidify photoresist, and the template at shifting, by etching technics, forms groove structure, obtain the concave nanometer
Graph layer.
It can be seen via above technical scheme that bottom provided by the invention has the LED epitaxial structure of recessed nano graph, packet
Include Sapphire Substrate and the buffer layer set gradually positioned at the sapphire substrate surface, concave nano graph layer, undoped
Layer, the first type semiconductor layer, multiple quantum well layer and the second type semiconductor layer；It wherein, can due to the presence of concave nano graph layer
To discharge the stress due to lattice mismatch and the big generation of thermal mismatching between GaN and Sapphire Substrate, epitaxy defect is reduced, thus
The lattice quality for improving LED, increases the internal quantum efficiency of LED.In addition, concave nano graph layer part covers buffer layer, concave
It in nano graph layer manufacturing process, is formed using nanometer embossing, exposed local buffer layer is stamped into, due to the folding of buffer layer
The refractive index of the refractive index and concave nano graph layer of penetrating rate and non-doped layer is not identical, can change in this way from Multiple-quantum
Total reflection is reduced, to improve the external quantum efficiency of LED in the direction for the light that well layer issues.
Simultaneously as the side wall absolutely not buffer layer structure of concave nano graph layer, avoids subsequently epitaxial growing is non-from mixing
Pattern side wall stress when diamicton sharply increases in concave nano graph, causes concave-convex in the first type semiconductor layer growth course
Seriously, the crystal quality of subsequent multiple quantum wells layer material is influenced, to avoid influencing luminous efficiency and product yield.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the LED epitaxial structure schematic diagram that a kind of bottom provided in an embodiment of the present invention has recessed nano graph；
Fig. 2-Fig. 4 is that concave nano graph layer provided in an embodiment of the present invention makes the formwork structure schematic diagram used；
Fig. 5 is the LED epitaxial structure production method stream that a kind of bottom provided in an embodiment of the present invention has recessed nano graph
Cheng Tu.
Specific embodiment
Just as described in the background section, the internal quantum efficiency of LED is lower in the prior art, need to be improved.
Inventor find the reasons for the above problems be, in recent years GaN base high brightness LED due to it is small in size,
The features such as light-weight and service life is long is widely used in solid state lighting, traffic lights, automobile front illumination, Geodesic Optics communication and
The fields such as biosensor.Since large scale, the GaN homo-substrate of high quality are difficult to prepare, Sapphire Substrate, Si are generallyd use
It is used as substrate material with SiC etc., is used for epitaxial growth GaN film, Sapphire Substrate is stable, saturating because having chemical and physical features
The advantages that photosensitiveness is good and cost is suitable is widely used in the substrate of GaN base light emitting, but due to GaN film and sapphire
Substrate lattice mismatch and coefficient of thermal expansion mismatch are big, and dislocation density is high, have seriously affected the electrical properties of LED extension and optical
Matter reduces the internal quantum efficiency of device.
Based on this, the present invention provides a kind of LED epitaxial structure of the bottom with recessed nano graph, comprising:
Sapphire Substrate；
In the Sapphire Substrate, received along buffer layer, the concave set gradually away from the Sapphire Substrate direction
Rice graph layer, non-doped layer, the first type semiconductor layer, multiple quantum well layer and the second type semiconductor layer；
Wherein, buffer layer described in the concave nano graph layer covering part, the thickness of the concave nano graph layer are small
In or equal to the non-doped layer thickness, and the material of the concave nano graph layer be silica.
Bottom provided by the invention have recessed nano graph LED epitaxial structure, including Sapphire Substrate and be located at institute
State buffer layer, concave nano graph layer, non-doped layer, the first type semiconductor layer, volume that sapphire substrate surface is set gradually
Sub- well layer and the second type semiconductor layer；Wherein, it due to the presence of concave nano graph layer, can discharge due to GaN and sapphire
The stress of the big generation of lattice mismatch and thermal mismatching between substrate reduces epitaxy defect, to improve the lattice quality of LED, increases
Add the internal quantum efficiency of LED.In addition, concave nano graph layer part covers buffer layer, in concave nano graph layer manufacturing process,
It is formed using nanometer embossing, is stamped into exposed local buffer layer, due to the refractive index of buffer layer and the refraction of non-doped layer
Rate and the refractive index of concave nano graph layer be not identical, can change the direction of the light issued from multiple quantum well layer in this way, subtract
Few total reflection, to improve the external quantum efficiency of LED.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Figure 1, Fig. 1 is the LED epitaxial structure that a kind of bottom provided in an embodiment of the present invention has recessed nano graph
Schematic diagram, LED epitaxial structure of the bottom with recessed nano graph include:
Sapphire Substrate 1 is located in Sapphire Substrate 1, along the buffer layer 2 set gradually away from 1 direction of Sapphire Substrate,
Concave nano graph layer 3, non-doped layer 4, the first type semiconductor layer 5, multiple quantum well layer 6 and the second type semiconductor layer 7.
Wherein, 3 covering part buffer layer 2 of concave nano graph layer, the thickness of concave nano graph layer 3 are less than or equal to non-
The thickness of doped layer, and the material of concave nano graph layer 3 is silica.
The specific structure of Sapphire Substrate is not limited in the present embodiment, optionally, in one embodiment of the invention, institute
Stating Sapphire Substrate is graphical sapphire substrate (Patterned Sapphire Substrate, PSS), of the invention another
In one embodiment, Sapphire Substrate can also be sapphire plain film substrate.
The external quantum efficiency of LED is greatly weakened due to there is the phenomenon that total reflection between GaN film and air again.In mistake
The following period of time gone, the development experience of LED one is obviously improved, light extraction efficiency overcoming LED/ Air Interface it is complete in
Reflection aspect achieves gratifying technological progress.Studies have shown that using PSS (patterned sapphire substrate, figure
Shape Sapphire Substrate), slim GaN technology and veining p-GaN layer can significantly improve light extraction efficiency.It is especially blue
Minute yardstick pattern on sapphire substrates substantially increases optical output power, to improve the external quantum efficiency of LED.Therefore, this hair
In bright embodiment, it is preferable that the Sapphire Substrate is graphical sapphire substrate.
To buffer layer, non-doped layer, the first type semiconductor layer, the second type semiconductor layer and multiple quantum well layer in the present embodiment
Specific material with no restrictions, in one embodiment of the invention, the specific material of buffer layer can be as AlN；Or it is described
Buffer layer is the laminated construction of AlGaN layer with AlN layers, wherein buffer layer is using AlGaN layer and AlN layer stacked structure, especially first
Growth forms AlN layers, and regrowth forms AlGaN layer, can play the role of lattice transition, reduces sapphire and GaN because of lattice
Stress caused by mismatch.It should be noted that the thickness of buffer layer needs sufficiently thick, the thickness of restriction buffer layer in the present embodiment
For 0.5 μm~2.5 μm, including endpoint value.
LED epitaxial structure is mainly GaN base blue-green LED structure in the embodiment of the present invention, therefore, accordingly, the present invention
In embodiment, the material of non-doped layer is undoped GaN；First type semiconductor layer and the second type semiconductor layer are specially one
It is N-type GaN layer, one is p-type GaN layer, and optional in the present embodiment, the first type semiconductor layer is N-type GaN layer, second type half
Conductor layer is p-type GaN layer.In other embodiments of the invention, the first type semiconductor layer can also be p-type GaN layer, corresponding
, the second type semiconductor layer can be N-type GaN layer.The material for not limiting multiple quantum well layer in the present embodiment, can be according to reality
Lattice Matching selects Lattice Matching preferable, the preferable multiple quantum wells material of lattice quality.
It should be noted that in the present embodiment without limitation to the concrete shape of concave nano graph layer, the concave is received
Rice graph layer is formed using nanometer embossing.The concave structure of the concave nano graph layer is hemispherical groove, cone
Groove or inverted trapezoidal groove.That is, the concave nano graph layer formed using nanometer embossing, can be using plane
Hemispherical dome structure, conical structure or trapezium structure are set in template, on silica membrane coining formed hemispherical groove,
Cone-shaped groove or inverted trapezoidal groove form.In other embodiments of the invention, the shape of template is also possible to other shapes,
As long as the optical path that multiple quantum well layer issues light can be changed, total reflection is avoided.It as shown in figs 2-4, is to be arranged in template
The schematic diagram of different structure.
It should be noted that in order to avoid due to introducing concave nano graph layer, when causing the formation of succeeding layer structure, lattice
Defect is more, in the present embodiment, limit the projected outline's widest part width of concave nano graph layer on a sapphire substrate as
180nm~280nm, including endpoint value.The direction of the unlimited fixed width degree of the widest part namely projected outline with respect to both sides edge it
Between distance, width can be referred to as.When thickness is too big in other words for the depth of concave nano graph layer, lead to figure inclined surface
When too precipitous, it will cause a part of light to be limited in groove, can not be emitted, causes light emission rate lower, therefore, the present embodiment
Drop centre type nano graph layer on the direction perpendicular to Sapphire Substrate with a thickness of 50nm~200nm, including endpoint value；It is described
The transverse and longitudinal ratio of concave nano graph layer is greater than or equal to 1.Simultaneously, additionally it is possible to when avoiding subsequently epitaxial growing, too due to groove
It is precipitous epitaxial growth hole occur, reduce luminous efficiency.In the present embodiment, the surface density range of the concave nano graph layer is
5*108cm-2~9*108cm-2, including endpoint value.The transverse and longitudinal ratio of concave nano graph layer described in the present embodiment is concave
The projected outline's widest part width of nano graph layer on a sapphire substrate is served as a contrast with concave nano graph layer perpendicular to sapphire
The ratio between thickness on the direction at bottom.
It is provided by the invention that concave nano graph layer is grown on PSS or sapphire plain film substrate, epitaxial layer can be made to exist
During subsequent growth, screw dislocation is bent and then reduces dislocation density, the crystal quality of LED extension is improved, to improve LED
Internal quantum efficiency, in addition this structure can more effectively make the transmitting of greater proportion optically coupling in escape cone, and then improve
The external quantum efficiency of LED, meanwhile, increase the outer membrane area coverage of LED using the inclined surface of concave nano graph layer, effectively dissipates
Transmitting photon is penetrated, the luminous intensity of LED is caused to increase.Tilt angle by adjusting the side wall of concave nano graph layer is different,
Non-doped layer can be changed in the side wall and the speed of growth on the buffer layer of concave nano graph layer, to reduce the shape of hole
At, prevent hole formation, to LED realize high brightness play a crucial role.
Based on identical inventive concept, the present invention also provides the LED epitaxial structure systems that a kind of bottom has recessed nano graph
Make method, refers to Fig. 5, Fig. 5 is the LED epitaxial structure production method flow diagram that bottom has recessed nano graph, described
Production method includes:
S101: substrate is provided；
S102: buffer layer is formed over the substrate；
S103: concave nano graph layer is formed on the buffer layer, described in the concave nano graph layer covering part
Buffer layer；
It is specifically, described that concave nano graph layer is formed on the buffer layer, comprising:
Silicon dioxide thin film growth；
Template is processed, the template is for imprinting the groove structure for forming concave nano graph layer；
Pattern transfer, forms photoresist on the silica membrane, by the pattern transfer in the template described in
On photoresist；
Solidify photoresist, and the template at shifting, by etching technics, forms groove structure, obtain the concave nanometer
Graph layer.
S104: non-doped layer is formed on the concave nano graph layer；
S105: the first type semiconductor layer, multiple quantum well layer and second type semiconductor are sequentially formed on the non-doped layer
Layer.
Production method provided in an embodiment of the present invention to clearly illustrate, the present invention by taking the several specific embodiments in lower section as an example into
Row explanation.
Embodiment one
Firstly, using MOCVD (metallo-organic compound chemical gaseous phase deposition) in PSS Grown on Sapphire Substrates buffer layer
AlN layers, AlN layers with a thickness of 1 μm, growth temperature range is 800 DEG C~1000 DEG C, it is preferable that in the present embodiment, growth temperature
It is 800 DEG C；It should be noted that AlN buffer layer, can also be grown using PVD, PVD plated film is uniform, preferable around plating property.
Growth forms SiO on buffer layer AlN layer2Thin layer is used for nano impression, with a thickness of 80nm, growth temperature range
It is 950 DEG C~1100 DEG C, it is preferable that in the present embodiment, growth temperature is 1000 DEG C；Growth is divided into then NH3Flow is constant, will
Temperature is reduced to room temperature, takes out the epitaxial wafer of growth interruption.
Template is processed, using means such as electron beam lithographies, pyramid type template, circular cone bottom surface are processed on silicon or other substrates
Cross diameter may range from 180nm~280nm, be preferably 180nm in the present embodiment, cone height range can in the present embodiment
Think 50nm~200nm, highly preferred in the present embodiment is 60nm, and density range can be 5*108cm-2~9*108cm-2, this
Density is preferably 8*10 in embodiment8cm-2。
Thin layer SiO is as above being grown in the transfer of pattern2Epitaxial wafer surface coat photoresist, template is then pressed in it
Surface is transferred to pattern on photoresist by the way of pressurization.Notice that photoresist cannot be entirely removed, prevents template and material
Material directly contacts, and damages template.
Solidification, makes photoetching adhesive curing with ultraviolet light, after removing template, the photoetching that is not completely removed previous step with etching liquid
Glue etches away, and exposes material surface to be processed, is then processed using the method for chemical etching, removes whole photoetching after the completion
Glue finally obtains high-precision nano graph.
LED epitaxial wafer with nano graph is put into MOCVD, is grown, is passed through the NH of 120L3Carry out protection table
Temperature is risen to 1100 DEG C, two layers of U-GaN of 2.0 μm of growth, then successively grows N-type GaN layer, mqw layer, p-type GaN layer by face.
Embodiment two
Firstly, using MOCVD (metallo-organic compound chemical gaseous phase deposition) in PSS Grown on Sapphire Substrates buffer layer
AlN layers, AlN layers with a thickness of 0.5 μm, then grow AlGaN layer, growth thickness is 0.5 μm, and growth temperature range is 800 DEG C
~1000 DEG C, it is preferable that in the present embodiment, growth temperature is 800 DEG C；It should be noted that AlN buffer layer, can also use
PVD growth, PVD plated film is uniform, preferable around plating property.
Growth forms SiO on buffer layer AlN layer2Thin layer is used for nano impression, with a thickness of 80nm, growth temperature range
It is 950 DEG C~1100 DEG C, it is preferable that in the present embodiment, growth temperature is 1000 DEG C；Growth is divided into then NH3Flow is constant, will
Temperature is reduced to room temperature, takes out the epitaxial wafer of growth interruption.
Template is processed, using means such as electron beam lithographies, pyramid type template, circular cone bottom surface are processed on silicon or other substrates
Cross diameter may range from 180nm~280nm, be preferably 180nm in the present embodiment, cone height range can in the present embodiment
Think 50nm~200nm, highly preferred in the present embodiment is 60nm, and density range can be 5*108cm-2~9*108cm-2, this
Density is preferably 8*10 in embodiment8cm-2。
Thin layer SiO is as above being grown in the transfer of pattern2Epitaxial wafer surface coat photoresist, template is then pressed in it
Surface is transferred to pattern on photoresist by the way of pressurization.Notice that photoresist cannot be entirely removed, prevents template and material
Material directly contacts, and damages template.
Solidification, makes photoetching adhesive curing with ultraviolet light, after removing template, the photoetching that is not completely removed previous step with etching liquid
Glue etches away, and exposes material surface to be processed, is then processed using the method for chemical etching, removes whole photoetching after the completion
Glue finally obtains high-precision nano graph.
LED epitaxial wafer with nano graph is put into MOCVD, is grown, is passed through the NH of 120L3Carry out protection table
Temperature is risen to 1100 DEG C, two layers of U-GaN of 2.0 μm of growth, then successively grows N-type GaN layer, mqw layer, p-type GaN layer by face.
It is different from the buffer growth structure of embodiment one kind in the present embodiment, first growing AIN layer regrowth AlGaN layer,
It can play the excessive effect of lattice, reduce sapphire and GaN because of stress caused by lattice mismatch.
Embodiment three
Firstly, using MOCVD (metallo-organic compound chemical gaseous phase deposition) in PSS Grown on Sapphire Substrates buffer layer
AlN layers, AlN layers with a thickness of 1 μm, growth temperature range is 800 DEG C~1000 DEG C, it is preferable that in the present embodiment, growth temperature
It is 800 DEG C；It should be noted that AlN buffer layer, can also be grown using PVD, PVD plated film is uniform, preferable around plating property.
Growth forms SiO on buffer layer AlN layer2Thin layer is used for nano impression, with a thickness of 80nm, growth temperature range
It is 950 DEG C~1100 DEG C, it is preferable that in the present embodiment, growth temperature is 1000 DEG C；Growth is divided into then NH3Flow is constant, will
Temperature is reduced to room temperature, takes out the epitaxial wafer of growth interruption.
Template is processed, using means such as electron beam lithographies, pyramid type template, circular cone bottom surface are processed on silicon or other substrates
Cross diameter may range from 180nm~280nm, be preferably 180nm in the present embodiment, cone height range can in the present embodiment
Think 50nm~200nm, highly preferred in the present embodiment is 160nm, and density range can be 5*108cm-2~9*108cm-2, this
Density is preferably 8*10 in embodiment8cm-2。
Thin layer SiO is as above being grown in the transfer of pattern2Epitaxial wafer surface coat photoresist, template is then pressed in it
Surface is transferred to pattern on photoresist by the way of pressurization.Notice that photoresist cannot be entirely removed, prevents template and material
Material directly contacts, and damages template.
Solidification, makes photoetching adhesive curing with ultraviolet light, after removing template, the photoetching that is not completely removed previous step with etching liquid
Glue etches away, and exposes material surface to be processed, is then processed using the method for chemical etching, removes whole photoetching after the completion
Glue finally obtains high-precision nano graph.
LED epitaxial wafer with nano graph is put into MOCVD, is grown, is passed through the NH of 120L3Carry out protection table
Temperature is risen to 1100 DEG C, two layers of U-GaN of 2.0 μm of growth, then successively grows N-type GaN layer, mqw layer, p-type GaN layer by face.
Example IV
Firstly, using MOCVD (metallo-organic compound chemical gaseous phase deposition) in PSS Grown on Sapphire Substrates buffer layer
AlN layers, AlN layers with a thickness of 1 μm, growth temperature range is 800 DEG C~1000 DEG C, it is preferable that in the present embodiment, growth temperature
It is 800 DEG C；It should be noted that AlN buffer layer, can also be grown using PVD, PVD plated film is uniform, preferable around plating property.
Growth forms SiO on buffer layer AlN layer2Thin layer is used for nano impression, with a thickness of 80nm, growth temperature range
It is 950 DEG C~1100 DEG C, it is preferable that in the present embodiment, growth temperature is 1000 DEG C；Growth is divided into then NH3Flow is constant, will
Temperature is reduced to room temperature, takes out the epitaxial wafer of growth interruption.
Template is processed, using means such as electron beam lithographies, inverted trapezoidal template, upper cross section are processed on silicon or other substrates
Side length is 180nm, and it is highly 60nm, density range can be 5*10 that lower section side length, which is 100nm,8cm-2~9*108cm-2, this
Density is preferably 8*10 in embodiment8cm-2。
Thin layer SiO is as above being grown in the transfer of pattern2Epitaxial wafer surface coat photoresist, template is then pressed in it
Surface is transferred to pattern on photoresist by the way of pressurization.Notice that photoresist cannot be entirely removed, prevents template and material
Material directly contacts, and damages template.
Solidification, makes photoetching adhesive curing with ultraviolet light, after removing template, the photoetching that is not completely removed previous step with etching liquid
Glue etches away, and exposes material surface to be processed, is then processed using the method for chemical etching, removes whole photoetching after the completion
Glue finally obtains high-precision nano graph.
LED epitaxial wafer with nano graph is put into MOCVD, is grown, is passed through the NH of 120L3Carry out protection table
Temperature is risen to 1100 DEG C, two layers of U-GaN of 2.0 μm of growth, then successively grows N-type GaN layer, mqw layer, p-type GaN layer by face.
In the present embodiment unlike embodiment one: concave nano graph is different, the present embodiment drop centre type nano graph
For inverted trapezoidal structure, but two schemes are conducive to increase the outgoing of light, improve external quantum efficiency, and reduce bottom because of lattice
Stress caused by mismatch and thermal mismatching increases LED entirety lattice quality, improves internal quantum efficiency.
Embodiment five
Firstly, using MOCVD (metallo-organic compound chemical gaseous phase deposition) in PSS Grown on Sapphire Substrates buffer layer
AlN layers, AlN layers with a thickness of 1 μm, growth temperature range is 800 DEG C~1000 DEG C, it is preferable that in the present embodiment, growth temperature
It is 800 DEG C；It should be noted that AlN buffer layer, can also be grown using PVD, PVD plated film is uniform, preferable around plating property.
Growth forms SiO on buffer layer AlN layer2Thin layer is used for nano impression, with a thickness of 80nm, growth temperature range
It is 950 DEG C~1100 DEG C, it is preferable that in the present embodiment, growth temperature is 1000 DEG C；Growth is divided into then NH3Flow is constant, will
Temperature is reduced to room temperature, takes out the epitaxial wafer of growth interruption.
Template is processed, using means such as electron beam lithographies, pyramid type template, circular cone bottom surface are processed on silicon or other substrates
Cross diameter may range from 180nm~280nm, be preferably 180nm in the present embodiment, cone height range can in the present embodiment
Think 50nm~200nm, highly preferred in the present embodiment is 60nm, and density range can be 5*108cm-2~9*108cm-2, this
Density is preferably 5*10 in embodiment8cm-2。
Thin layer SiO is as above being grown in the transfer of pattern2Epitaxial wafer surface coat photoresist, template is then pressed in it
Surface is transferred to pattern on photoresist by the way of pressurization.Notice that photoresist cannot be entirely removed, prevents template and material
Material directly contacts, and damages template.
Solidification, makes photoetching adhesive curing with ultraviolet light, after removing template, the photoetching that is not completely removed previous step with etching liquid
Glue etches away, and exposes material surface to be processed, is then processed using the method for chemical etching, removes whole photoetching after the completion
Glue finally obtains high-precision nano graph.
LED epitaxial wafer with nano graph is put into MOCVD, is grown, is passed through the NH of 120L3Carry out protection table
Temperature is risen to 1100 DEG C, two layers of U-GaN of 2.0 μm of growth, then successively grows N-type GaN layer, mqw layer, p-type GaN layer by face.
In the present embodiment, what is different from the first embodiment is that the surface density of concave nano graph is different.But it equally being capable of phase
For the stress between prior art release lattice, lattice quality is improved.
Embodiment six
Firstly, using MOCVD (metallo-organic compound chemical gaseous phase deposition) in PSS Grown on Sapphire Substrates buffer layer
AlN layers, AlN layers with a thickness of 1 μm, growth temperature range is 800 DEG C~1000 DEG C, it is preferable that in the present embodiment, growth temperature
It is 800 DEG C；It should be noted that AlN buffer layer, can also be grown using PVD, PVD plated film is uniform, preferable around plating property.
Growth forms SiO on buffer layer AlN layer2Thin layer is used for nano impression, with a thickness of 80nm, growth temperature range
It is 950 DEG C~1100 DEG C, it is preferable that in the present embodiment, growth temperature is 1000 DEG C；Growth is divided into then NH3Flow is constant, will
Temperature is reduced to room temperature, takes out the epitaxial wafer of growth interruption.
Template is processed, using means such as electron beam lithographies, pyramid type template, circular cone bottom surface are processed on silicon or other substrates
Cross diameter may range from 180nm~280nm, be preferably 180nm in the present embodiment, cone height range can in the present embodiment
Think 50nm~200nm, highly preferred in the present embodiment is 60nm, and density range can be 5*108cm-2~9*108cm-2, this
Density is preferably 8*10 in embodiment8cm-2。
The transfer of pattern coats photoresist on the epitaxial wafer surface for as above having grown thin layer GaN, template is then pressed in its table
Face is transferred to pattern on photoresist by the way of pressurization.Notice that photoresist cannot be entirely removed, prevents template and material
It directly contacts, damages template.
Solidification, makes photoetching adhesive curing with ultraviolet light, after removing template, the photoetching that is not completely removed previous step with etching liquid
Glue etches away, and exposes material surface to be processed, is then processed using the method for chemical etching, removes whole photoetching after the completion
Glue finally obtains high-precision nano graph.
LED epitaxial wafer with nano graph is put into MOCVD, is grown, is passed through the NH of 120L3Carry out protection table
Temperature is risen to 1100 degree, two layers of U-GaN of 2.0 μm of growth, then successively grows N-type GaN layer, mqw layer, p-type GaN layer by face.
In the present embodiment, what is different from the first embodiment is that the material of the concave graph layer formed is GaN, the present embodiment is
Comparative example it is known that subsequent GaN is easier in the growth of side wall, but is more prone to produce hole by subsequent growth,
Therefore, more stringenter than requiring to the transverse and longitudinal of recessed figure.
In production method provided by the invention, after having grown buffer layer, a thin layer SiO2 is grown, with the skill of nano impression
Art generates concave nano graph, and is stamped into and appears local AlN buffer layer, is compared with the prior art, the nanometer of different depth is recessed
Slot can improve the lattice quality of LED, and thinner and deep groove, lattice quality is better, but luminous efficiency is not but to be positively correlated
, therefore emphasize the importance of figure transverse and longitudinal ratio.
Since the inclined-plane of different angle changes light direction, transmitting photonic optical behavior is affected.For generally tying
For structure, according to Snell's law, n1*sin θ 1=n2*sin θ 2；Wherein, n1=1 represents air refraction, and n2=2.5 is represented
The refractive index of gallium nitride film.In view of complete internal reflection behavior (i.e. θ 1=90 °), 2=23.5 ° of critical angle θ can be counted
It calculates.Therefore, 23.5 ° be should be less than from the angle of LED active layer incident light, the light issued is enable to escape from LED structure.Work as incidence
When angular is greater than 23.5 °, the light of sending will be reflected back toward inside LED, i.e., only incident light can just go out inside escape cone
Light is penetrated, recessed nano graph is used compared to this structure, even if the incident light except escape cone, because of the side wall in concave nano-pattern
Place is reflected, and is made more to emit light and is returned in escape cone and be extracted.This escapes from LED structure for transmitting photon
Ease provides more probabilities of scattering, to reach higher light extraction efficiency.
To sum up, bottom provided by the invention has the LED epitaxial structure and preparation method thereof of recessed nano graph, and structure increases
Light intensity be attributed to concave nano graph and improve crystal quality and then improve internal quantum efficiency and concave inclination face and improve light and mention
It takes efficiency and then improves external quantum efficiency.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. the LED epitaxial structure that a kind of bottom has recessed nano graph characterized by comprising
Sapphire Substrate；
In the Sapphire Substrate, along buffer layer, the concave nanometer figure set gradually away from the Sapphire Substrate direction
Shape layer, non-doped layer, the first type semiconductor layer, multiple quantum well layer and the second type semiconductor layer；
Wherein, buffer layer described in the concave nano graph layer covering part, the thickness of the concave nano graph layer be less than or
Equal to the thickness of the non-doped layer, and the material of the concave nano graph layer is silica.
2. the LED epitaxial structure that bottom according to claim 1 has recessed nano graph, which is characterized in that the concave
Projected outline widest part width of the nano graph layer in the Sapphire Substrate is 180nm~280nm, including endpoint value.
3. the LED epitaxial structure that bottom according to claim 2 has recessed nano graph, which is characterized in that the concave
Nano graph layer in the direction perpendicular to the Sapphire Substrate with a thickness of 50nm~200nm, including endpoint value；It is described recessed
The transverse and longitudinal ratio of type nano graph layer is greater than or equal to 1.
4. the LED epitaxial structure that bottom according to claim 1 has recessed nano graph, which is characterized in that the concave
Nano graph layer is formed using nanometer embossing.
5. the LED epitaxial structure that bottom according to claim 1 has recessed nano graph, which is characterized in that the concave
The concave structure of nano graph layer is hemispherical groove, cone-shaped groove or inverted trapezoidal groove.
6. the LED epitaxial structure that bottom according to claim 1 has recessed nano graph, which is characterized in that the concave
The surface density range of nano graph layer is 5*108cm-2~9*108cm-2, including endpoint value.
7. the LED epitaxial structure that bottom according to claim 1 has recessed nano graph, which is characterized in that the buffering
The material of layer is AlN；Or the buffer layer is the laminated construction of AlGaN layer with AlN layers.
8. the LED epitaxial structure that bottom according to claim 1 has recessed nano graph, which is characterized in that described blue precious
Stone lining bottom is graphical sapphire substrate or sapphire plain film substrate.
9. the LED epitaxial structure production method that a kind of bottom has recessed nano graph characterized by comprising
Substrate is provided；
Buffer layer is formed over the substrate；
Concave nano graph layer, buffer layer described in the concave nano graph layer covering part are formed on the buffer layer；
Non-doped layer is formed on the concave nano graph layer；
The first type semiconductor layer, multiple quantum well layer and the second type semiconductor layer are sequentially formed on the non-doped layer.
10. the LED epitaxial structure production method that bottom according to claim 9 has recessed nano graph, which is characterized in that
It is described that concave nano graph layer is formed on the buffer layer, it specifically includes:
Silicon dioxide thin film growth；
Template is processed, the template is for imprinting the groove structure for forming concave nano graph layer；
Pattern transfer, forms photoresist on the silica membrane, by the pattern transfer in the template to the photoetching
On glue；
Solidify photoresist, and the template at shifting, by etching technics, forms groove structure, obtain the concave nano graph
Layer.
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| US16/826,160 US11328924B2 (en) | 2017-09-30 | 2020-03-20 | Semiconductor wafer and method for manufacturing semiconductor wafer thereof |
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