CN110112166B - Inclined grid back-illuminated CMOS image sensor - Google Patents
Inclined grid back-illuminated CMOS image sensor Download PDFInfo
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- CN110112166B CN110112166B CN201910432896.3A CN201910432896A CN110112166B CN 110112166 B CN110112166 B CN 110112166B CN 201910432896 A CN201910432896 A CN 201910432896A CN 110112166 B CN110112166 B CN 110112166B
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
Abstract
The invention discloses a backside illuminated CMOS image sensor, comprising: n photodiodes; a transfer switch comprising a gate and N channel regions under the gate that are electrically isolated from each other; and N floating nodes, wherein each of the N photodiodes is connected to a corresponding one of the N floating nodes through a corresponding one of the channel regions of the transfer switch.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a tilted gate back-illuminated CMOS image sensor.
Background
A CMOS image sensor is an image sensor manufactured based on a CMOS process for converting an analog optical signal into a digital electrical signal. And an external light source converges an image on the pixel array of the photosensitive area of the CMOS image sensor through an optical device. The pixel array converts the received optical signal into an analog electrical signal, and the analog electrical signal is amplified, denoised and sent to an analog-to-digital converter for digitalization. And finally, the digitized signal is operated by an image processing chip to obtain a clear and real image.
The back-illuminated CMOS image sensor has the advantages of low power consumption, high quantum efficiency, and the like, and is widely used in devices such as mobile phones and cameras. The biggest optimization point of the back-illuminated CMOS image sensor is to change the structure inside an element, namely, the element of the photosensitive layer is turned to the direction, so that light energy can penetrate into the sensor from the back surface directly, and the influence of a metal circuit and a transistor between a micro lens and a photodiode on the light ray in the traditional CMOS sensor structure is avoided, thereby remarkably improving the light efficiency and greatly improving the shooting effect under the condition of low illumination.
A conventional back-illuminated CMOS image sensor product has a basic configuration including: microlens, optical filter, photodiode, metal layer, etc. Fig. 1 shows a circuit diagram of a related art back-illuminated CMOS image sensor. Figure 2 shows a cross-sectional schematic of a prior art photodiode. A CMOS image sensor commonly used at present is a 4T circuit, and includes a Transfer switch (TG) 110, a Reset transistor (Rx, Reset)120, a Source Follower (Sx, Source Follower)130, a Select transistor (Rs, Select)140, a photodiode (PD, Photo Diode)150, a Floating node (FD, Floating Diffusion)160, and other circuit structures.
As the demand for image sensors with high pixels increases, the design of chips with higher and higher pixels and the manufacturing process thereof need to be improved. As shown in fig. 1 and 2, in a 4T circuit adopted in a current pixel unit, circuit structures such as a transfer switch 110, a reset tube 120, a source follower 130, a selection tube 140, a photodiode 150, a floating node 160 and the like are all integrated in a pixel region, and one PD corresponds to one TG, which occupies a larger pixel region area, reduces the area of a photosensitive region, and affects an imaging effect.
There is therefore a need in the art for a new type of back-illuminated CMOS image sensor that improves the overall performance of the image sensor by optimizing the structure or layout of the various devices.
Disclosure of Invention
In view of the above problems in the prior art, according to an aspect of the present invention, there is provided a back-illuminated CMOS image sensor including:
n photodiodes;
a transfer switch comprising a gate and N channel regions under the gate that are electrically isolated from each other; and
n floating nodes, wherein each of the N photodiodes is connected to a corresponding one of the N floating nodes through a corresponding one of the channel regions of the transfer switch.
In one embodiment of the present invention, the back-illuminated CMOS image sensor further includes N signal transfer circuits each connected to a corresponding one of the N floating nodes, each signal transfer circuit including:
the source electrode of the reset tube is connected to one end of the floating node, and the drain electrode of the reset tube is connected to a power supply;
a source follower, the grid electrode of which is connected to the source stage of the reset tube, and the drain electrode of which is connected to the power supply;
and the drain electrode of the selection tube is connected to the source electrode of the source follower, the source electrode of the selection tube is an output end, and the grid electrodes of the transmission switch, the reset tube and the selection tube are connected to an external control circuit.
In one embodiment of the invention, during signal processing, the transfer switch is turned on, the charge of each photodiode is transferred through the corresponding floating node, and a signal is output at the output terminal.
In one embodiment of the present invention, the back-illuminated CMOS image sensor further includes a truncated pyramid groove formed on the front surface of the wafer, the top of the truncated pyramid is flush with the front surface of the wafer, the area of the top of the truncated pyramid is larger than the area of the bottom of the truncated pyramid, the truncated pyramid has N inclined side surfaces extending from the top to the bottom of the truncated pyramid, each inclined side surface is isolated by an isolation trench, the gate of the transfer switch is formed in the truncated pyramid groove, and N channel regions of the transfer switch, which are electrically isolated from each other, are formed on the N inclined side surfaces of the truncated pyramid.
In one embodiment of the present invention, each photodiode includes a clamp photodiode PPD, an N-type photodiode NPD formed at upper and lower ends of an inclined side of a truncated pyramid, and an N-type doped region therebelow, the clamp photodiode being formed at a front surface area of the wafer adjacent to the floating node, and a channel region of the transfer switch being disposed between the floating node and the N-type photodiode.
In another embodiment of the present invention, there is provided a back-illuminated CMOS image sensor array including:
a plurality of pixel units arranged in a matrix, each pixel unit comprising: 4 photodiodes; a transfer switch comprising a gate and 4 channel regions under the gate that are electrically isolated from each other; and 4 floating nodes, wherein each of the 4 photodiodes is connected to a corresponding one of the 4 floating nodes through a corresponding one of the channel regions of the transfer switch;
there are 4 signal transfer circuits provided around each pixel unit, each signal transfer circuit being connected to a corresponding one of the 4 floating nodes, each signal transfer circuit including: the source electrode of the reset tube is connected to one end of the floating node, and the drain electrode of the reset tube is connected to a power supply; a source follower, the grid electrode of which is connected to the source stage of the reset tube, and the drain electrode of which is connected to the power supply; and the drain electrode of the selection tube is connected to the source electrode of the source follower, the source electrode of the selection tube is an output end, and the grid electrodes of the transmission switch, the reset tube and the selection tube are connected to an external control circuit.
In another embodiment of the present invention, adjacent pixel cells share a signal transfer circuit.
In another embodiment of the present invention, during signal processing, the transfer switch of the first pixel unit is turned on, charges of each photodiode of the first pixel unit are transferred through the corresponding floating node, a signal is output at the output terminal, and then the transfer switches of the pixel units in the horizontal and vertical directions are sequentially controlled to obtain a complete image signal.
In still another embodiment of the present invention, there is provided a method of manufacturing a back-illuminated CMOS image sensor, including:
growing a dielectric layer on the wafer, and implanting a photodiode PD area and a photodiode isolation PDI area;
growing a mask layer;
coating a photoresist, patterning the photoresist by a photoetching process, etching the mask layer, then performing anisotropic etching in a wet etching mode, and forming a reversed frustum groove on the front surface of the wafer;
growing a sacrificial layer on the surface of the wafer, and implanting a P-well region;
carrying out NPD zone implantation;
performing FD area implantation;
performing PPD zone implantation;
growing a thick silicon dioxide layer as a polysilicon etching barrier layer;
coating a photoresist, and patterning the photoresist through a photoetching process to expose a grid channel region;
removing the oxide layer in the gate channel region;
removing the photoresist, cleaning the surface and growing a gate oxide layer;
growing an undoped polysilicon layer, and then carrying out surface doping by adopting an ion implantation mode;
coating a photoresist PR, patterning the photoresist by a photoetching process, and only keeping the photoresist of the grid polysilicon area;
etching the grid polysilicon, and then removing the residual photoresist;
forming a dielectric layer;
and carrying out metal connecting hole etching and hole filling processes, and forming external metal interconnection at the floating node and the grid electrode of the transmission switch.
In still another embodiment of the present invention, the FD region and the NPD region are formed at upper and lower ends of the inclined side of the chamfered stage.
The invention designs the inclined grid of the transfer switch and shares the grid, thereby improving the area of the photodiode area to a certain extent and improving the imaging quality. And four reset tube Rx, source follower Sx and selection tube Rs circuits are arranged around one pixel unit, which is equivalent to that 4 photodiodes PD and 4 floating nodes FD share 1 transfer switch TG, 2 reset tube Rx, source follower Sx and selection tube Rs circuits, the signal transmission speed is doubled compared with the signal transmission of the traditional circuit, and the performance of the device is improved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a circuit diagram of a related art back-illuminated CMOS image sensor.
Figure 2 shows a cross-sectional schematic of a prior art photodiode.
Fig. 3 illustrates a front view of a back-illuminated CMOS image sensor 300 according to an embodiment of the present invention.
Fig. 4 illustrates a cross-sectional view taken along line AA of the back-illuminated CMOS image sensor 300 illustrated in fig. 3.
Fig. 5 illustrates a back side view of a back-illuminated CMOS image sensor 300 according to an embodiment of the present invention.
Fig. 6 illustrates a circuit diagram of a back-illuminated CMOS image sensor 600 according to an embodiment of the present invention.
Fig. 7 illustrates a top view of a back-illuminated CMOS image sensor array according to an embodiment of the present invention.
Fig. 8A to 8P are sectional views illustrating a process of manufacturing a back-illuminated CMOS image sensor according to an embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
In the process of manufacturing the back-illuminated CMOS image sensor chip, the 4T circuit adopted in the pixel unit comprises a transfer switch, a reset tube, a source follower, a selection tube, a photodiode, a floating node and other circuit structures. Embodiments of the present invention optimize and design the layout of these circuit structures.
Fig. 3 illustrates a front view of a back-illuminated CMOS image sensor 300 according to an embodiment of the present invention. Fig. 4 illustrates a cross-sectional view taken along line AA of the back-illuminated CMOS image sensor 300 illustrated in fig. 3. Fig. 5 illustrates a back side view of a back-illuminated CMOS image sensor 300 according to an embodiment of the present invention.
After entering the shutter, the photons are first focused into the corresponding pixel by the microlens 360 and then filtered out of unwanted colors by the filter 370 of the bayer array 380. Photons are injected from the back surface of the device layer to the direction from the substrate to the N buried layer to the clamping layer. As shown in fig. 3 to 5, the back-illuminated CMOS image sensor 300 includes four photodiodes 310-1 to 310-4 (hereinafter collectively referred to as photodiodes 310), four floating nodes 320-1 to 320-4 (hereinafter collectively referred to as floating nodes 320), and one transfer switch 330. The four photodiodes 310-1 to 310-4 share one transfer switch 330. The four photodiodes 310-1 to 310-4 are connected to a corresponding one of the four floating nodes 320-1 to 320-4 through the transfer switch 330.
The back-illuminated CMOS image sensor 300 is formed on a wafer, including a truncated pyramid groove formed on the front surface of the wafer by etching. The top and the bottom of the chamfering platform are square, and the area of the top is larger than that of the bottom. The chamfering table has four sloped sides extending from the top to the bottom of the chamfering table. The four sloped sides are isolated by isolation trenches 340. The gate of the transfer switch 330 is formed in the inverted-pyramid groove, and thus the gate of the transfer switch 330 has four inclined sides.
The four sloped sides under the gate of the transfer switch 330 have four channel regions spaced apart from each other to control the four photodiodes to be turned on and off with respect to the corresponding floating nodes, respectively. Each photodiode 310 may include a clamping photodiode PPD 311 at the surface, an N-type photodiode NPD 312, and an underlying N-type doped region. The floating node 320 and the N-type photodiode 312 are formed at the upper and lower ends of the inclined side of the inverted truncated pyramid, respectively. Clamp photodiode 311 is formed on the front side of the wafer adjacent to floating node 320. The channel region of the transfer switch 330 is disposed between the floating node 320 and the N-type photodiode 312, and the floating node 320 and the N-type photodiode 312 are turned on and off by controlling the voltage at the gate.
Specifically, referring to the cross-sectional view shown in fig. 4, a P-type well region is formed around the top of the sloped side of the inverted mesa, and a floating node 320 region is formed in the P-type well region. The N-type photodiode NPD 312 is formed at a lower end of the P-type well region and includes an upper P-type doped region and a lower N-type doped region. The region between the floating node 320 and the N-type photodiode NPD 312 is a channel region of the transfer switch 330.
The CMOS image sensor circuit disclosed by the embodiment of the invention adopts a novel inclined grid electrode. The area of the photodiode region of the CMOS image sensor directly determines the full well capacity, and the area of the photodiode region can be increased to a certain extent and the imaging quality can be improved by designing the inclined grid of the transfer switch and sharing the grid.
Fig. 6 illustrates a circuit diagram of a back-illuminated CMOS image sensor 600 according to an embodiment of the present invention. As shown in fig. 6, the back-illuminated CMOS image sensor 600 includes a reset transistor 640, a source follower 650, and a selection transistor 660, in addition to the photodiode 610, the floating node 620, and the transfer switch 630 having the same structure as those shown in fig. 3 to 5. The source of the reset tube 640 is connected to one end of the floating node 620, and the drain thereof is connected to the power supply VDD. The source follower 650 has a gate connected to the source of the reset tube 640 and a drain connected to the power supply VDD. The drain of select transistor 660 is connected to the source of source follower 650, and the source of select transistor 660 is the output. The gates of the transfer switch 630, the reset tube 640 and the selection tube 660 are connected to an external control circuit.
Fig. 7 illustrates a top view of a back-illuminated CMOS image sensor array according to an embodiment of the present invention. As shown in fig. 7, the illumination CMOS image sensor array may include an array of four rows and four columns of photodiodes. It will be understood by those skilled in the art that the array shown in fig. 7 is for illustrative purposes only and that the image sensor array protected by the present invention may comprise any number of rows and columns depending on the actual needs. In the embodiment shown in fig. 7, four photodiodes PD of two adjacent rows and two columns share one transfer switch, and each photodiode corresponds to one floating node FD, so that four photodiodes PD, four floating nodes FD, and one transfer switch TG constitute one pixel unit. Each floating node is connected to a corresponding reset tube Rx, source follower Sx, and select tube Rs. As shown in fig. 7, the signal transmission circuit composed of the reset tube Rx, the source follower Sx, and the select tube Rs is disposed around one pixel unit, that is, four signal transmission circuits are disposed around each pixel unit, and adjacent pixel units may share the signal transmission circuit. Therefore, four circuits of the reset tube Rx, the source follower Sx and the selection tube Rs are arranged around one pixel unit, which is equivalent to that 4 photodiodes PD and 4 floating nodes FD share circuits of 1 transfer switch TG, 2 reset tubes Rx, the source follower Sx and the selection tube Rs, the signal propagation speed is doubled compared with the signal transmission of the traditional circuit, and the performance of the device is improved.
Specifically, as shown in fig. 7, Rx11 is connected to FD11, Rx12 is connected to FD12, Rx13 is connected to FD22, Rx32 is connected to FD21, and so on. In the signal processing, TG11 is turned on, and charges of 4 PDs are transferred by FD11, FD12, FD22, and FD21, respectively, to output a signal. And then sequentially controlling the switches of the TG in the horizontal direction and the vertical direction to obtain a complete image signal.
The area in CMOS image sensor PD region directly determines the size of full well capacity, and this patent inclines grid design through design TG to the sharing grid can increase required CD linewidth, and can promote the regional area of PD, improves the imaging quality.
A method of manufacturing the CMOS image sensor is described below with reference to fig. 8A to 8P. Fig. 8A to 8P are sectional views illustrating a process of manufacturing a back-illuminated CMOS image sensor according to an embodiment of the present invention.
First, a dielectric layer 801 is grown on the wafer and the photodiode PD region and the photodiode isolation PDI region are implanted, as shown in fig. 8A. The wafer may be a silicon wafer or may be other semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. The PD area is an N-type lightly doped area.
Next, regrowing mask layer SiO 2802, a film with better uniformity is obtained, as shown in fig. 8B.
Next, a photoresist PR is coated, and the photoresist PR is patterned by performing processes such as exposure and development, and the mask layer is etched first, and then anisotropically etched by wet etching, so as to form a truncated pyramid groove on the front surface of the wafer, as shown in fig. 8C. The photoresist and mask layer are then removed.
Next, a sacrificial layer, which may be SiO, is grown on the wafer surface2Coating photoresist PR, performing processes such as exposure and development to pattern the photoresist, and performing P-well implantation, as shown in FIG. 8D. And removing the photoresist after the P-well region implantation is completed.
Next, a photoresist PR is coated, and the photoresist PR is patterned by exposure, development, and the like, and then NPD region implantation is performed, as shown in fig. 8E. And removing the photoresist after the NPD zone implantation is finished.
Next, a photoresist PR is coated, and the photoresist PR is patterned by exposure, development, and the like, and then FD region implantation is performed, as shown in fig. 8F. And removing the photoresist after the FD region implantation is finished.
Next, a photoresist PR is coated, and the photoresist PR is patterned by exposure, development, and the like, and then PPD region implantation is performed, as shown in fig. 8G. And removing the photoresist after the FD region implantation is finished.
Next, a thick silicon dioxide layer is grown as a polysilicon etch stop layer, as shown in fig. 8H.
Next, a photoresist PR is coated, and the photoresist PR is patterned by exposure, development, and the like to expose the gate channel region, as shown in fig. 8I.
Next, the oxide layer of the gate channel region is removed, as shown in fig. 8J. The oxide layer of the gate channel region may be removed using a wet or dry etch process.
Next, the photoresist is removed, the surface is cleaned and a gate oxide layer is grown, as shown in fig. 8K.
Next, an undoped polysilicon layer is grown, and then surface doping is performed by means of ion implantation, as shown in fig. 8L.
Next, a photoresist PR is coated, and the photoresist PR is patterned by exposure, development, and the like, so that only the gate polysilicon region remains, as shown in fig. 8M.
Then, gate polysilicon etching is performed and the residual photoresist is removed, as shown in fig. 8N.
Next, depositing a dielectric layer; surface planarization is then performed by CMP, as shown in fig. 8O. The dielectric layer may typically be SiO2。
Next, a metal connection hole etching and hole filling process, generally a W filling and MOCVD process, is performed, and as shown in fig. 8P, an external metal interconnection is formed at the floating node and the gate of the transfer switch.
In the above embodiment of the present invention, the description has been given by taking an example where 4 photodiodes PD and 4 floating nodes FD share 1 transfer switch TG, 2 reset transistors Rx, source followers Sx, and select transistor Rs circuits, and it should be understood by those skilled in the art that in other embodiments of the present invention, N photodiodes PD and N floating nodes FD may share 1 transfer switch TG, M reset transistors Rx, source followers Sx, and select transistor Rs circuits, where M < N.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A pixel cell of a backside-illuminated CMOS image sensor, comprising:
n photodiodes, N being an integer greater than or equal to 2;
a transfer switch comprising a gate and N channel regions under the gate that are electrically isolated from each other; and
n floating nodes, wherein each of the N photodiodes is connected to a corresponding one of the N floating nodes through a corresponding one of the channel regions of the transfer switch.
2. A backside-illuminated CMOS image sensor, comprising:
n photodiodes, N being an integer greater than or equal to 2;
a transfer switch comprising a gate and N channel regions under the gate that are electrically isolated from each other; and
n floating nodes, wherein each of the N photodiodes is connected to a corresponding one of the N floating nodes through a corresponding one of the channel regions of the transfer switch;
n signal transfer circuits, each signal transfer circuit connected to a corresponding one of the N floating nodes, each signal transfer circuit comprising:
the source electrode of the reset tube is connected to one end of the floating node, and the drain electrode of the reset tube is connected to a power supply;
a source follower, the grid electrode of which is connected to the source stage of the reset tube, and the drain electrode of which is connected to the power supply;
and the drain electrode of the selection tube is connected to the source electrode of the source follower, the source electrode of the selection tube is an output end, and the grid electrodes of the transmission switch, the reset tube and the selection tube are connected to an external control circuit.
3. The back-illuminated CMOS image sensor according to claim 2, wherein the transfer switch is turned on at the time of signal processing, and a charge of each photodiode is transferred through a corresponding floating node to output a signal at an output terminal.
4. The backside illuminated CMOS image sensor of claim 2 further comprising a truncated pyramid recess formed on the front side of the wafer, the top of the truncated pyramid being flush with the front side of the wafer, the top of the truncated pyramid having an area larger than the bottom, the truncated pyramid having N sloped sides extending from the top to the bottom of the truncated pyramid, each sloped side being isolated by an isolation trench, the gate of the transfer switch being formed in the truncated pyramid recess, the N channel regions of the transfer switch being electrically isolated from each other being formed on the N sloped sides of the truncated pyramid.
5. The back-illuminated CMOS image sensor according to claim 4, wherein each photodiode includes a clamp photodiode PPD, an N-type photodiode NPD and an underlying N-type doped region, the floating node and the N-type photodiode are formed at upper and lower ends of the inclined side of the inverted pyramid, respectively, the clamp photodiode is formed at the front surface area of the wafer and adjacent to the floating node, and the channel region of the transfer switch is disposed between the floating node and the N-type photodiode.
6. A back-illuminated CMOS image sensor array, comprising:
a plurality of pixel units arranged in a matrix, each pixel unit comprising: 4 photodiodes; a transfer switch comprising a gate and 4 channel regions under the gate that are electrically isolated from each other; and 4 floating nodes, wherein each of the 4 photodiodes is connected to a corresponding one of the 4 floating nodes through a corresponding one of the channel regions of the transfer switch;
there are 4 signal transfer circuits provided around each pixel unit, each signal transfer circuit being connected to a corresponding one of the 4 floating nodes, each signal transfer circuit including: the source electrode of the reset tube is connected to one end of the floating node, and the drain electrode of the reset tube is connected to a power supply; a source follower, the grid electrode of which is connected to the source stage of the reset tube, and the drain electrode of which is connected to the power supply; and the drain electrode of the selection tube is connected to the source electrode of the source follower, the source electrode of the selection tube is an output end, and the grid electrodes of the transmission switch, the reset tube and the selection tube are connected to an external control circuit.
7. The back-illuminated CMOS image sensor array of claim 6, wherein adjacent pixel cells share signal transfer circuitry.
8. The back-illuminated CMOS image sensor array according to claim 6, wherein in the signal processing, the transfer switch of the first pixel unit is turned on, the charge of each photodiode of the first pixel unit is transferred through the corresponding floating node, a signal is outputted at the output terminal, and then the transfer switches of the pixel units in the horizontal and vertical directions are sequentially controlled to obtain a complete image signal.
9. A method of fabricating a pixel cell of a backside illuminated CMOS image sensor as claimed in claim 1, comprising:
growing a dielectric layer on the wafer, and implanting a photodiode PD area and a photodiode isolation PDI area;
growing a mask layer;
coating a photoresist, patterning the photoresist by a photoetching process, etching the mask layer, then performing anisotropic etching in a wet etching mode, and forming a reversed frustum groove on the front surface of the wafer;
growing a sacrificial layer on the surface of the wafer, and implanting a P-well region;
carrying out NPD zone implantation;
performing FD area implantation;
performing PPD zone implantation;
growing a thick silicon dioxide layer as a polysilicon etching barrier layer;
coating a photoresist, and patterning the photoresist through a photoetching process to expose a grid channel region;
removing the oxide layer in the gate channel region;
removing the photoresist, cleaning the surface and growing a gate oxide layer;
growing an undoped polysilicon layer, and then carrying out surface doping by adopting an ion implantation mode;
coating a photoresist PR, patterning the photoresist by a photoetching process, and only keeping the photoresist of the grid polysilicon area;
etching the grid polysilicon, and then removing the residual photoresist;
forming a dielectric layer;
and carrying out metal connecting hole etching and hole filling processes, and forming external metal interconnection at the floating node and the grid electrode of the transmission switch.
10. The method of fabricating a pixel unit of a back-illuminated CMOS image sensor as claimed in claim 9, wherein the FD region and the NPD region are formed at upper and lower ends of the inclined side of the chamfered.
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| CN105161462A (en) * | 2015-07-22 | 2015-12-16 | 格科微电子（上海）有限公司 | Method for improving carrier transmission efficiency of backside illumination image sensor |
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