CN110111833A - Memory verification circuit and verification method - Google Patents

Abstract

The invention discloses a memory verification circuit and a verification method. The verification circuit includes a block decoder and more than two memory modules, each memory module includes a row decoder, a column decoder and a memory array, each memory The array includes memory cells arranged in an array, the memory cells belonging to the same memory array are the same, and the memory cells belonging to different memory arrays are different; the block decoder is used to decode the block address signal to gate the row in a memory module Decoder and column decoder; The row decoder is used to decode the row address signal, so as to select a row of memory cells of the memory array in the memory module where the row decoder is located; The column decoder is used to The address signal is decoded to select a column of memory cells of the memory array in the memory module where the column decoder is located. The memory verification circuit and verification method provided by the invention can improve the verification efficiency of memory verification and reduce the verification cost of memory verification.

Description

Memory verification circuit and verification method

technical field

The invention relates to the technical field of memory, in particular to a memory verification circuit and verification method.

Background technique

With the continuous exploration of human beings into the space field, the radiation environment faced by spacecraft, satellites and other aerospace equipment is becoming more and more complex. In these complex radiation environments, the hazards of single event effects are very serious, which may cause logic confusion in the control system of aerospace equipment. The single event effect refers to a radiation effect that causes abnormal changes in the state of the device when a single high-energy particle passes through the sensitive area of the microelectronic device, including single event flipping, single event locking, single event burning, and single event gate breakdown.

Static Random Access Memory (SRAM, Static Random Access Memory) is a kind of memory with static access function. Due to its fast read and write speed and no need to refresh, SRAM has been widely used as a cache . Especially for space-oriented static random access memory, its anti-single event upset performance directly affects the reliability of aerospace equipment control systems. In SRAM, the memory cells with latch structure are the most sensitive to single event upset. The simulation experiment of single-event upset by relying on the heavy particles produced by the accelerator is an effective verification method to verify the anti-single event upset performance of static random access memory. However, the existing methods for verifying the anti-single event upset performance of static random access memory can only verify the anti-single event upset performance of one memory unit at the same time, which has low verification efficiency and high verification cost.

Contents of the invention

What the invention aims to solve is the problem of low efficiency and high cost of verifying the memory.

The present invention realizes through following technical scheme:

A memory verification circuit, comprising a row decoder, a column decoder, and a storage array, the storage array includes memory cells arranged in an array, and the memory cells arranged in an array are divided into two or more storage areas , the storage units belonging to the same storage area are the same, and the storage units belonging to different storage areas are different;

The row decoder is used to decode a row address signal to select a row of memory cells of the memory array;

The column decoder is used to decode the column address signal to select a column of memory cells of the memory array.

Optionally, memory cells belonging to different memory areas have different circuit structures; or,

Memory cells belonging to different memory areas have the same circuit structure and different sizes.

Optionally, the memory verification circuit also includes a read circuit and a control circuit;

The reading circuit is used to read the data stored in each storage unit;

The control circuit is used to provide read and write control signals to the column decoder and the read circuit.

Optionally, the number of storage units in each storage area is the same.

Based on the same inventive concept, the present invention also provides another memory verification circuit, including a block decoder and more than two memory modules, each memory module includes a row decoder, a column decoder and a memory array, each memory The array includes storage units arranged in an array, the storage units belonging to the same storage array are the same, and the storage units belonging to different storage arrays are different;

The block decoder is used to decode the block address signal to gate the row decoder and the column decoder in a storage module;

The row decoder is used to decode the row address signal to select a row of memory cells of the memory array in the memory module where the row decoder is located;

The column decoder is used to decode the column address signal to select a column of memory cells of the memory array in the memory module where the column decoder is located.

Optionally, memory cells belonging to different memory arrays have different circuit structures; or,

Memory cells belonging to different memory arrays have the same circuit structure but different sizes.

Optionally, the memory verification circuit also includes a read circuit and a control circuit;

The reading circuit is used to read data stored in each storage array;

The control circuit is used to provide read and write control signals to the column decoder and the read circuit.

Optionally, the number of the storage modules is determined according to the type of the storage unit to be verified.

Optionally, the number of storage units in each storage array is the same.

Based on the same inventive concept, the present invention also provides a memory verification method, which is applied to the above memory verification circuit, and the memory verification method includes:

Filling the storage array with verification data;

a single event incident on the storage array;

Read the data stored in each storage unit;

determining the storage unit in which an error occurs according to the data written into each storage unit and the data read from each storage unit;

According to the address corresponding to the storage unit in which the error occurred, the number of the storage unit in which the error occurred in each type of storage unit is obtained.

Optionally, the verification data is hexadecimal data 55AA.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

The memory verification circuit and verification method provided by the present invention can simultaneously verify the performance of different memory units, such as the anti-single event upset performance, by setting more than two storage areas or more than two memory modules. Since the probability of each ion hitting the unit area of the storage structure in a unit time is certain when conducting the anti-single event flipping performance experiment, the larger the area of the storage structure, the more ions can be incident in a shorter time. The experiment time is also shorter. However, the memory verification circuit provided by the present invention includes different types of memory units, which increases the area of the memory structure, so a certain amount of ions can be injected in a relatively short time, and the verification efficiency can be improved. Moreover, the memory verification circuit provided by the present invention can verify different memory units at the same time, which greatly reduces the cost of circuit design, plate making and experimentation, and has great application value.

Description of drawings

The drawings described here are used to provide a further understanding of the embodiments of the present invention, constitute a part of the application, and do not limit the embodiments of the present invention. In the attached picture:

FIG. 1 is a schematic structural diagram of a memory verification circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a memory verification circuit according to an embodiment of the present invention;

3 is a schematic structural diagram of a memory verification circuit according to another embodiment of the present invention;

4 is a circuit diagram of a memory verification circuit according to another embodiment of the present invention;

FIG. 5 is a flowchart of a memory verification method according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the examples and accompanying drawings. As a limitation of the present invention.

Example 1

This embodiment provides a memory verification circuit, and FIG. 1 is a schematic structural diagram of the memory verification circuit. The memory verification circuit includes a block decoder 10 and N storage modules (storage module 11, storage module 12, . . . , storage module 1N), where N is an integer not less than 2.

Each memory module includes a row decoder, a column decoder and a memory array. For example, the storage module 11 includes a column decoder 111, a row decoder 112, and a storage array 113; the storage module 12 includes a column decoder 121, a row decoder 122, and a storage array 123; ...; the The memory module 1N includes a column decoder 1N1 , a row decoder 1N2 and a memory array 1N3 . Each memory array includes memory cells arranged in an array, wherein the memory cells belonging to the same memory array are the same, that is, the circuit structure and size of all memory cells in the same memory array are the same; the memory cells belonging to different memory arrays The difference, for example, may be that memory cells belonging to different memory arrays have different circuit structures, or may be that memory cells belonging to different memory arrays have the same circuit structure and different sizes. The number of the storage modules, that is, the value of N, is determined according to the type of the storage unit to be verified. For example, if there are 8 types of storage units that need to be verified, then the number of storage modules is 8, that is, the value of N is 8. In this embodiment, the anti-single event upset characteristic of the static random access memory is verified, so each storage unit is a static random access storage unit. Certainly, each storage unit may also be another storage unit, which is determined according to the actual object to be verified. Further, the number of storage units in each storage array can be set to be the same.

The block decoder 10 is used to decode the block address signal to gate the row decoder and the column decoder in a memory module. Specifically, each input end of the block decoder 10 is correspondingly connected to a block address line, and each output end of the block decoder 10 is correspondingly connected to the enable end and the row decoder in a memory module. The enable terminal of the column decoder. The number of block address lines connected to the input of the block decoder 10 is determined according to the number of the memory modules, that is, 2 ^W =N, where W is the number of block address lines connected to the block decoder 10 . Taking the number of the storage modules as 8, that is, the value of N is 8 as an example, the input end of the block decoder 10 is connected to 3 block address lines in total, that is, the block decoder 10 is 3-wire- 8-line decoder.

When the block address signal is binary data 000, the column decoder 111 and the row decoder 112 in the storage module 11 are strobed, that is, the column decoder 111 and the row decoder 112 work, and the columns in other storage modules The decoder and the row decoder do not work; when the block address signal is binary data 001, the column decoder 121 and the row decoder 122 in the storage module 12 are gated, that is, the column decoder 121 and the row decoder Decoder 122 works, column decoder and row decoder in other storage modules do not work; ...; when the block address signal is binary data 110, column decoder 171 and row decoder 172 in storage module 11 Be gated, that is, column decoder 171 and row decoder 172 work, column decoder and row decoder in other memory modules do not work; when block address signal is binary data 111, memory module 12 The column decoder 181 and the row decoder 182 are gated, that is, the column decoder 181 and the row decoder 182 work, and the column decoders and row decoders in other memory modules do not work.

The column decoder is used to decode the column address signal to select a column of memory cells of the memory array in the memory module where the column decoder is located. Specifically, the number of column address lines connected to the input end of the column decoder is determined according to the number of columns of the memory array, that is, 2 ^U = L, where U is the number of column address lines connected to the column decoder , L is the number of columns of the storage array. Taking the number of columns of the memory array as 8, that is, the value of L is 8 as an example, the input end of the column decoder is connected to 3 column address lines in total, that is, the column decoder is 3 lines-8 line decoder. When the column address signal is binary data 000 and the column decoder 111 is strobed, the first column memory cell of the memory array 113 is selected; when the column address signal is binary data 001 and the column decoder When 111 is strobed, the second column storage unit of the memory array 113 is selected; ...; when the column address signal is binary data 110 and the column decoder 111 is gated, the second row of the memory array 113 Seven columns of memory cells are selected; when the column address signal is binary data 111 and the column decoder 111 is strobed, the eighth column of memory cells of the memory array 113 is selected.

The row decoder is used to decode the row address signal to select a row of memory cells of the memory array in the memory module where the row decoder is located. Specifically, the number of row address lines connected to the input of the row decoder is determined according to the number of rows of the memory array, that is, 2 ^V = M, where V is the number of row address lines connected to the row decoder , M is the number of rows of the storage array. Taking the number of rows of the memory array as 8, that is, the value of M is 8 as an example, the input end of the row decoder is connected to 3 row address lines in total, that is, the row decoder is 3 lines-8 line decoder. When the row address signal is binary data 000 and the row decoder 112 is strobed, the first row memory cell of the memory array 113 is selected; when the row address signal is binary data 001 and the row decoder 112 is selected When strobing, the second row of memory cells of the memory array 113 is selected; ...; when the row address signal is binary data 110 and the row decoder 112 is strobed, the seventh row of the memory array 113 stores The cell is selected; when the row address signal is binary data 111 and the row decoder 112 is strobed, the memory cell in the eighth row of the memory array 113 is selected.

It should be noted that all column decoders are connected to the column address lines, and the row decoders are connected to the row address lines, and are decoded by the block decoder 10, and each time there is only one memory module The row decoder and column decoder in work. The total number of the column address lines and the row address lines is determined according to the storage capacity of the storage array, for example, if the storage capacity of the storage array is 8Kbit, the total number of the column address lines and the row address lines The quantity is 13.

It should be noted that, similar to a conventional memory, the memory verification circuit further includes a read circuit and a control circuit. The read circuit is used to read data stored in each storage unit, and the control circuit is used to provide read and write control signals to the column decoder and the read circuit. The structures of the reading circuit and the control circuit are the same as those in the prior art, which are not improvements of the present invention, and will not be repeated in this embodiment.

To better illustrate the structure of the memory verification circuit, FIG. 2 shows a memory verification circuit including four memory arrays, each memory array including four rows and four columns of memory cells. Wherein, A1A2 is the block address signal received by the block decoder 10, and the row decoder 10 obtains four output signals EN1, EN2, EN3 and EN4 by decoding the block address signal A1A2, and converts the four Road output signals EN1, EN2, EN3 and EN4 are respectively used as the enable signals of the row decoder and column decoder in each memory array, that is, EN1 is used as the enable signal of the column decoder 111 and the row decoder 112, EN2 is used as the enable signal of the column decoder 121 and the row decoder 122, EN3 is used as the enable signal of the column decoder 131 and the row decoder 132, and EN4 is used as the enable signal of the column decoder 141 and the row decoder 142. Enable signal; A3A4 is the row address signal received by each row decoder, and A5A6 is the column address signal received by each column decoder.

Example 2

This embodiment provides another memory verification circuit, and FIG. 3 is a schematic structural diagram of the memory verification circuit. The memory verification circuit includes a row decoder 31 , a column decoder 32 and a memory array 33 .

The storage array 33 includes storage units arranged in an array, and the storage units arranged in an array are divided into N storage areas (storage area 331, storage area 332, ..., storage area 33N), wherein, belonging to the same The storage units in the storage area are the same, that is, the circuit structure and size of all the storage units in the same storage area are the same; the storage units belonging to different storage areas are different, for example, the circuit structures of the storage units belonging to different storage areas may be different , it is also possible that memory cells belonging to different memory areas have the same circuit structure and different sizes. The number of the storage areas, that is, the value of N, is determined according to the type of the storage unit to be verified. For example, if there are 8 types of storage units that need to be verified, then the number of storage modules is 8, that is, the value of N is 8. In this embodiment, the anti-single event upset characteristic of the static random access memory is verified, so each storage unit is a static random access storage unit. Certainly, each storage unit may also be another storage unit, which is determined according to the actual object to be verified. Further, the number of storage units in each storage area may be set to be the same.

The row decoder 31 is used for decoding row address signals to select a row of memory cells of the memory array 33 . Specifically, the number of row address lines connected to the input end of the row decoder 31 is determined according to the number of rows of the memory array, that is, 2 ^V =M, where V is the row address connected to the row decoder 31 The number of lines, M is the number of lines of the storage array 33. Take the number of rows of the memory array 33 as 8, that is, the value of M is 8 as an example, the input end of the row decoder 31 is connected to 3 row address lines in total, that is, the row decoder 31 is 3 Line - 8 line decoder. When the row address signal was binary data 000, the first row storage unit of the storage array 33 was selected; when the row address signal was binary data 001, the second row storage unit of the storage array 33 was selected; ...; when the row address When the signal is binary data 110, the storage unit in the seventh row of the memory array 33 is selected; when the row address signal is binary data 111, the storage unit in the eighth row of the storage array 33 is selected.

The column decoder 32 is used to decode a column address signal to select a column of memory cells of the memory array 33 . Specifically, the number of column address lines connected to the input end of the column decoder 32 is determined according to the number of columns of the storage array 33, that is, 2 ^U =L, where U is the column connected to the column decoder 32 The number of address lines, L is the number of columns of the storage array 33 . Taking the number of columns of the memory array 33 as 8, that is, the value of L is 8 as an example, the input terminals of the column decoder 32 are connected to 3 column address lines in total, that is, the column decoder 32 is 3 Line - 8 line decoder. When the column address signal is binary data 000, the first column storage unit of the storage array 33 is selected; when the column address signal is binary data 001, the second column storage unit of the storage array 33 is selected;  …; When the column address signal is binary data 110, the storage unit in the seventh column of the memory array 33 is selected; when the column address signal is binary data 111, the storage unit in the eighth column of the storage array 33 is selected.

It should be noted that the total number of the column address lines and the row address lines is determined according to the storage capacity of the storage array 33, for example, if the storage capacity of the storage array 33 is 8Kbit, the column address lines and The total number of row address lines is thirteen. Similar to a conventional memory, the memory verification circuit also includes a read circuit and a control circuit. The read circuit is used to read data stored in each storage unit, and the control circuit is used to provide read and write control signals to the column decoder and the read circuit. The structures of the reading circuit and the control circuit are the same as those in the prior art, which are not improvements of the present invention, and will not be repeated in this embodiment.

In order to better illustrate the structure of the memory verification circuit, FIG. 4 shows a memory verification circuit in which the memory array 33 includes four storage areas, and each storage area includes four rows and four columns of memory cells, wherein, A1A2A3 is the row address signal received by the row decoder 31 , and A4A5A6 is the column address signal received by the column decoder 32 .

Example 3

Based on the memory verification circuit provided in Embodiment 1 or Embodiment 2, this embodiment also provides a memory verification method. In this embodiment, the memory verification method is used for verifying the anti-single event upset characteristic of the static random access memory. Of course, the above memory verification circuit is not limited to verifying the anti-single event upset characteristic of the SRAM, for example, it can also be used to verify the noise tolerance of the storage unit, etc., which is not limited in this embodiment. Fig. 5 is the flow chart of described memory verification method, and described memory verification method comprises:

Step S1, filling the storage array with verification data. Specifically, for the memory verification circuit provided in Embodiment 1, the block address signal is decoded by the block decoder 10, and the column decoder and the row decoder in the memory module are selected; The decoder decodes the column address signal and the row decoder decodes the row address signal to select the storage unit in the storage array. Each storage unit is selected in turn, and one bit of data is written correspondingly until all storage units are written with data, that is, each storage array is filled. The verification data can be set according to actual needs. In this embodiment, the verification data is hexadecimal data 55AA, that is, binary data 0101010110101010. For the memory verification circuit provided in Embodiment 2, the column address signal is decoded directly by the column decoder 32 and the row address signal is decoded by the row decoder 31, and the memory array 33 is selected storage unit.

In step S2, a single particle is incident on the storage array. The memory verification circuit is irradiated with various radiation sources generated by single event effects, such as ions provided by an accelerator. When the incident ions accumulated to the fluence required by the experiment, the irradiation was stopped.

Step S3, reading the data stored in each storage unit. Specifically, for the memory verification circuit provided in Embodiment 1, the block address signal is decoded by the block decoder 10, and the column decoder and the row decoder in the memory module are selected; The decoder decodes the column address signal and the row decoder decodes the row address signal to select the storage unit in the storage array. Each storage unit is selected in turn, and one bit of data is read out correspondingly, until the data stored in all storage units are read out. For the memory verification circuit provided in Embodiment 2, the column address signal is decoded directly by the column decoder 32 and the row address signal is decoded by the row decoder 31, and the memory array 33 is selected memory cells to be read.

Step S4, according to the data written into each storage unit and the data read from each storage unit, determine the storage unit where the error occurs. Comparing the data written into each storage unit with the data read from each storage unit, if the data read from a storage unit is the same as the data written into the storage unit, then the storage unit stored The data is correct, and the single event reversal effect has not occurred; if the data read from a certain storage unit is different from the data written to the storage unit, the single event reversal effect has occurred in the storage unit, and the storage unit is an error storage unit .

Step S5, according to the address corresponding to the storage unit where the error occurred, the number of the storage unit where the error occurred in each type of storage unit is obtained. Since the address corresponding to each storage unit is unique, according to the address corresponding to the storage unit where the error occurs, the block address signal corresponding to the storage unit where the error occurs can be obtained, and then the storage array or storage area where the storage unit where the error occurs can be obtained. By counting the number of storage units with errors in each storage array or storage area, the anti-single event upset characteristic of each storage unit can be obtained.

Since the probability of each ion hitting the unit area of the storage structure in a unit time is certain when conducting the anti-single event flipping performance experiment, the larger the area of the storage structure, the more ions can be incident in a shorter time. The experiment time is also shorter. However, the memory verification circuit provided by this embodiment includes different types of memory cells, which increases the area of the memory structure, so that a certain amount of ions can be injected in a relatively short time, and the verification efficiency can be improved. Moreover, the memory verification circuit provided by the present invention can verify different memory units at the same time, which greatly reduces the cost of circuit design, plate making and experimentation, and has great application value.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (10)

1. A memory verification circuit, characterized in that it comprises a row decoder, a column decoder and a memory array, the memory array includes memory cells arranged in an array, and the memory cells arranged in an array are divided into For more than two storage areas, the storage units belonging to the same storage area are the same, and the storage units belonging to different storage areas are different; The row decoder is used to decode a row address signal to select a row of memory cells of the memory array; The column decoder is used to decode the column address signal to select a column of memory cells of the memory array. 2. The memory verification circuit according to claim 1, wherein the circuit structures of memory cells belonging to different memory areas are different; or, Memory cells belonging to different memory areas have the same circuit structure and different sizes. 3. The memory verification circuit according to claim 1, further comprising a read circuit and a control circuit; The reading circuit is used to read the data stored in each storage unit; The control circuit is used to provide read and write control signals to the column decoder and the read circuit. 4. The memory verification circuit according to claim 1, wherein the number of storage cells in each storage area is the same. 5. A memory verification circuit, characterized in that it includes a block decoder and more than two memory modules, each memory module includes a row decoder, a column decoder and a memory array, and each memory array includes a memory array arranged in an array The storage units of the same storage array are the same, and the storage units belonging to different storage arrays are different; The block decoder is used to decode the block address signal to gate the row decoder and the column decoder in a memory module; The row decoder is used to decode the row address signal to select a row of memory cells of the memory array in the memory module where the row decoder is located; The column decoder is used to decode the column address signal to select a column of memory cells of the memory array in the memory module where the column decoder is located. 6. The memory verification circuit according to claim 5, wherein the memory cells belonging to different memory arrays have different circuit structures; or, Memory cells belonging to different memory arrays have the same circuit structure but different sizes. 7. The memory verification circuit according to claim 5, further comprising a read circuit and a control circuit; The reading circuit is used to read the data stored in each storage unit; The control circuit is used to provide read and write control signals to the column decoder and the read circuit. 8. The memory verification circuit according to claim 5, wherein the number of memory cells in each memory array is the same. 9. A memory verification method, applied to the memory verification circuit according to any one of claims 1 to 8, characterized in that, comprising: Filling the storage array with verification data; a single event incident on the storage array; Read the data stored in each storage unit; determining the storage unit in which an error occurs according to the data written into each storage unit and the data read from each storage unit; According to the address corresponding to the storage unit in which the error occurred, the number of the storage unit in which the error occurred in each type of storage unit is obtained. 10. The memory verification method according to claim 9, wherein the verification data is hexadecimal data 55AA.