CN110111833A - Memory verification circuit and verification method - Google Patents

Memory verification circuit and verification method Download PDF

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CN110111833A
CN110111833A CN201910263759.1A CN201910263759A CN110111833A CN 110111833 A CN110111833 A CN 110111833A CN 201910263759 A CN201910263759 A CN 201910263759A CN 110111833 A CN110111833 A CN 110111833A
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memory
decoder
array
storage
circuit
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CN110111833B (en
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王林飞
韩郑生
罗家俊
刘海南
邢劼思
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Institute of Microelectronics of CAS
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30Accessing single arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38Response verification devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

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Abstract

本发明公开了一种存储器验证电路以及验证方法,所述验证电路包括块译码器和两个以上存储模块,每个存储模块包括行译码器、列译码器以及存储阵列,每个存储阵列包括呈阵列排布的存储单元,属于相同存储阵列的存储单元相同,属于不同存储阵列的存储单元不同;块译码器用于对块地址信号进行译码,以选通一个存储模块中的行译码器和列译码器;行译码器用于对行地址信号进行译码,以选通所述行译码器所在存储模块中的存储阵列的一行存储单元;列译码器用于对列地址信号进行译码,以选通所述列译码器所在存储模块中的存储阵列的一列存储单元。本发明提供的存储器验证电路和验证方法,能够提高存储器验证的验证效率、降低存储器验证的验证成本。

The invention discloses a memory verification circuit and a verification method. The verification circuit includes a block decoder and more than two memory modules, each memory module includes a row decoder, a column decoder and a memory array, each memory The array includes memory cells arranged in an array, the memory cells belonging to the same memory array are the same, and the memory cells belonging to different memory arrays are different; the block decoder is used to decode the block address signal to gate the row in a memory module Decoder and column decoder; The row decoder is used to decode the row address signal, so as to select a row of memory cells of the memory array in the memory module where the row decoder is located; The column decoder is used to The address signal is decoded to select a column of memory cells of the memory array in the memory module where the column decoder is located. The memory verification circuit and verification method provided by the invention can improve the verification efficiency of memory verification and reduce the verification cost of memory verification.

Description

存储器验证电路以及验证方法Memory verification circuit and verification method

技术领域technical field

本发明涉及存储器技术领域,具体涉及一种存储器验证电路以及验证方法。The invention relates to the technical field of memory, in particular to a memory verification circuit and verification method.

背景技术Background technique

随着人类向太空领域的不断探索,宇宙飞船以及卫星等航天设备所要面临的辐射环境也越来越复杂。在这些复杂的辐射环境中,单粒子效应的危害十分严重,可能造成航天设备的控制系统逻辑混乱。单粒子效应是指单个高能粒子穿过微电子器件灵敏区时造成器件状态非正常改变的一种辐射效应,包括单粒子翻转、单粒子锁定、单粒子烧毁以及单粒子栅击穿等。With the continuous exploration of human beings into the space field, the radiation environment faced by spacecraft, satellites and other aerospace equipment is becoming more and more complex. In these complex radiation environments, the hazards of single event effects are very serious, which may cause logic confusion in the control system of aerospace equipment. The single event effect refers to a radiation effect that causes abnormal changes in the state of the device when a single high-energy particle passes through the sensitive area of the microelectronic device, including single event flipping, single event locking, single event burning, and single event gate breakdown.

静态随机存取存储器(SRAM,Static Random Access Memory)是一种具有静态存取功能的内存,由于其具有读写速度快且无需进行刷新的特点,静态随机存取存储器作为高速缓存已经被广泛应用。尤其是面向空间应用的静态随机存取存储器,其抗单粒子翻转性能直接影响着航天设备控制系统的可靠性。在静态随机存取存储器中,对单粒子翻转最敏感的是具有锁存结构的存储单元。依靠加速器产生的重粒子进行单粒子翻转的模拟实验,是一种验证静态随机存取存储器抗单粒子翻转性能的有效验证方法。然而,现有的验证静态随机存取存储器抗单粒子翻转性能的方法,只能同时验证一种存储单元的抗单粒子翻转性能,验证效率低,且验证成本较高。Static Random Access Memory (SRAM, Static Random Access Memory) is a kind of memory with static access function. Due to its fast read and write speed and no need to refresh, SRAM has been widely used as a cache . Especially for space-oriented static random access memory, its anti-single event upset performance directly affects the reliability of aerospace equipment control systems. In SRAM, the memory cells with latch structure are the most sensitive to single event upset. The simulation experiment of single-event upset by relying on the heavy particles produced by the accelerator is an effective verification method to verify the anti-single event upset performance of static random access memory. However, the existing methods for verifying the anti-single event upset performance of static random access memory can only verify the anti-single event upset performance of one memory unit at the same time, which has low verification efficiency and high verification cost.

发明内容Contents of the invention

本发明所要解决的是对存储器进行验证效率低、成本高的问题。What the invention aims to solve is the problem of low efficiency and high cost of verifying the memory.

本发明通过下述技术方案实现:The present invention realizes through following technical scheme:

一种存储器验证电路,包括行译码器、列译码器以及存储阵列,所述存储阵列包括呈阵列排布的存储单元,所述呈阵列排布的存储单元被划分为两个以上存储区域,属于相同存储区域的存储单元相同,属于不同存储区域的存储单元不同;A memory verification circuit, comprising a row decoder, a column decoder, and a storage array, the storage array includes memory cells arranged in an array, and the memory cells arranged in an array are divided into two or more storage areas , the storage units belonging to the same storage area are the same, and the storage units belonging to different storage areas are different;

所述行译码器用于对行地址信号进行译码,以选通所述存储阵列的一行存储单元;The row decoder is used to decode a row address signal to select a row of memory cells of the memory array;

所述列译码器用于对列地址信号进行译码,以选通所述存储阵列的一列存储单元。The column decoder is used to decode the column address signal to select a column of memory cells of the memory array.

可选的,属于不同存储区域的存储单元的电路结构不同;或者,Optionally, memory cells belonging to different memory areas have different circuit structures; or,

属于不同存储区域的存储单元的电路结构相同、尺寸不同。Memory cells belonging to different memory areas have the same circuit structure and different sizes.

可选的,所述存储器验证电路还包括读取电路和控制电路;Optionally, the memory verification circuit also includes a read circuit and a control circuit;

所述读取电路用于读取每个存储单元存储的数据;The reading circuit is used to read the data stored in each storage unit;

所述控制电路用于向所述列译码器和所述读取电路提供读写控制信号。The control circuit is used to provide read and write control signals to the column decoder and the read circuit.

可选的,所述每个存储区域中的存储单元数量均相同。Optionally, the number of storage units in each storage area is the same.

基于同样的发明构思,本发明还提供另一种存储器验证电路,包括块译码器和两个以上存储模块,每个存储模块包括行译码器、列译码器以及存储阵列,每个存储阵列包括呈阵列排布的存储单元,属于相同存储阵列的存储单元相同,属于不同存储阵列的存储单元不同;Based on the same inventive concept, the present invention also provides another memory verification circuit, including a block decoder and more than two memory modules, each memory module includes a row decoder, a column decoder and a memory array, each memory The array includes storage units arranged in an array, the storage units belonging to the same storage array are the same, and the storage units belonging to different storage arrays are different;

所述块译码器用于对块地址信号进行译码,以选通一个存储模块中的行译码器和列译码器;The block decoder is used to decode the block address signal to gate the row decoder and the column decoder in a storage module;

所述行译码器用于对行地址信号进行译码,以选通所述行译码器所在存储模块中的存储阵列的一行存储单元;The row decoder is used to decode the row address signal to select a row of memory cells of the memory array in the memory module where the row decoder is located;

所述列译码器用于对列地址信号进行译码,以选通所述列译码器所在存储模块中的存储阵列的一列存储单元。The column decoder is used to decode the column address signal to select a column of memory cells of the memory array in the memory module where the column decoder is located.

可选的,属于不同存储阵列的存储单元的电路结构不同;或者,Optionally, memory cells belonging to different memory arrays have different circuit structures; or,

属于不同存储阵列的存储单元的电路结构相同、尺寸不同。Memory cells belonging to different memory arrays have the same circuit structure but different sizes.

可选的,所述存储器验证电路还包括读取电路和控制电路;Optionally, the memory verification circuit also includes a read circuit and a control circuit;

所述读取电路用于读取每个存储阵列存储的数据;The reading circuit is used to read data stored in each storage array;

所述控制电路用于向所述列译码器和所述读取电路提供读写控制信号。The control circuit is used to provide read and write control signals to the column decoder and the read circuit.

可选的,所述存储模块的数量根据需要验证的存储单元的种类确定。Optionally, the number of the storage modules is determined according to the type of the storage unit to be verified.

可选的,所述每个存储阵列中的存储单元数量均相同。Optionally, the number of storage units in each storage array is the same.

基于同样的发明构思,本发明还提供一种存储器验证方法,应用于上述存储器验证电路,所述存储器验证方法包括:Based on the same inventive concept, the present invention also provides a memory verification method, which is applied to the above memory verification circuit, and the memory verification method includes:

对所述存储阵列写满验证数据;Filling the storage array with verification data;

单粒子入射所述存储阵列;a single event incident on the storage array;

读取每个存储单元存储的数据;Read the data stored in each storage unit;

根据写入所述每个存储单元的数据和从所述每个存储单元读出的数据,确定发生错误的存储单元;determining the storage unit in which an error occurs according to the data written into each storage unit and the data read from each storage unit;

根据发生错误的存储单元对应的地址,获得每种存储单元中发生错误的存储单元的数量。According to the address corresponding to the storage unit in which the error occurred, the number of the storage unit in which the error occurred in each type of storage unit is obtained.

可选的,所述验证数据为十六进制数据55AA。Optionally, the verification data is hexadecimal data 55AA.

本发明与现有技术相比,具有如下的优点和有益效果:Compared with the prior art, the present invention has the following advantages and beneficial effects:

本发明提供的存储器验证电路以及验证方法,通过设置两个以上存储区域或者两个以上存储模块,能够同时验证不同存储单元的性能,例如抗单粒子翻转性能。由于进行抗单粒子翻转性能实验时,每个离子在单位时间内射中存储结构的单位面积的概率是一定的,存储结构的面积越大,则在较短的时间就可以入射一定量的离子,实验的时间也就越短。而本发明提供的存储器验证电路包括了不同种类的存储单元,增大了存储结构的面积,因而在较短的时间就可以入射一定量的离子,能够提高验证效率。并且,本发明提供的存储器验证电路能够对不同存储单元同时进行验证,大大降低了电路设计、制版以及实验成本,具有很大的应用价值。The memory verification circuit and verification method provided by the present invention can simultaneously verify the performance of different memory units, such as the anti-single event upset performance, by setting more than two storage areas or more than two memory modules. Since the probability of each ion hitting the unit area of the storage structure in a unit time is certain when conducting the anti-single event flipping performance experiment, the larger the area of the storage structure, the more ions can be incident in a shorter time. The experiment time is also shorter. However, the memory verification circuit provided by the present invention includes different types of memory units, which increases the area of the memory structure, so a certain amount of ions can be injected in a relatively short time, and the verification efficiency can be improved. Moreover, the memory verification circuit provided by the present invention can verify different memory units at the same time, which greatly reduces the cost of circuit design, plate making and experimentation, and has great application value.

附图说明Description of drawings

此处所说明的附图用来提供对本发明实施例的进一步理解,构成本申请的一部分,并不构成对本发明实施例的限定。在附图中:The drawings described here are used to provide a further understanding of the embodiments of the present invention, constitute a part of the application, and do not limit the embodiments of the present invention. In the attached picture:

图1为本发明一种实施例的存储器验证电路的结构示意图;FIG. 1 is a schematic structural diagram of a memory verification circuit according to an embodiment of the present invention;

图2为本发明一种实施例的存储器验证电路的电路图;FIG. 2 is a circuit diagram of a memory verification circuit according to an embodiment of the present invention;

图3为本发明另一种实施例的存储器验证电路的结构示意图;3 is a schematic structural diagram of a memory verification circuit according to another embodiment of the present invention;

图4为本发明另一种实施例的存储器验证电路的电路图;4 is a circuit diagram of a memory verification circuit according to another embodiment of the present invention;

图5为本发明实施例的存储器验证方法的流程图。FIG. 5 is a flowchart of a memory verification method according to an embodiment of the present invention.

具体实施方式Detailed ways

为使本发明的目的、技术方案和优点更加清楚明白,下面结合实施例和附图,对本发明作进一步的详细说明,本发明的示意性实施方式及其说明仅用于解释本发明,并不作为对本发明的限定。In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the examples and accompanying drawings. As a limitation of the present invention.

实施例1Example 1

本实施例提供一种存储器验证电路,图1是所述存储器验证电路的结构示意图。所述存储器验证电路包括块译码器10和N个存储模块(存储模块11、存储模块12、…、存储模块1N),N为不小于2的整数。This embodiment provides a memory verification circuit, and FIG. 1 is a schematic structural diagram of the memory verification circuit. The memory verification circuit includes a block decoder 10 and N storage modules (storage module 11, storage module 12, . . . , storage module 1N), where N is an integer not less than 2.

每个存储模块包括行译码器、列译码器以及存储阵列。例如,所述存储模块11包括列译码器111、行译码器112以及存储阵列113;所述存储模块12包括列译码器121、行译码器122以及存储阵列123;…;所述存储模块1N包括列译码器1N1、行译码器1N2以及存储阵列1N3。每个存储阵列包括呈阵列排布的存储单元,其中,属于相同存储阵列的存储单元相同,即位于同一个存储阵列中的所有存储单元的电路结构和尺寸均相同;属于不同存储阵列的存储单元不同,例如,可以是属于不同存储阵列的存储单元的电路结构不同,也可以是属于不同存储阵列的存储单元的电路结构相同、尺寸不同。所述存储模块的数量,即N的取值,是根据需要验证的存储单元的种类确定的。例如,需要验证的存储单元的种类为8种,则所述存储模块的数量为8,即N的取值为8。在本实施例中,验证的是静态随机存取存储器抗单粒子翻转特性,因而每个存储单元均为静态随机存取存储单元。当然,每个存储单元也可以为其他存储单元,具体根据实际需要验证的对象确定。进一步,所述每个存储阵列中的存储单元数量可以设置为均相同。Each memory module includes a row decoder, a column decoder and a memory array. For example, the storage module 11 includes a column decoder 111, a row decoder 112, and a storage array 113; the storage module 12 includes a column decoder 121, a row decoder 122, and a storage array 123; ...; the The memory module 1N includes a column decoder 1N1 , a row decoder 1N2 and a memory array 1N3 . Each memory array includes memory cells arranged in an array, wherein the memory cells belonging to the same memory array are the same, that is, the circuit structure and size of all memory cells in the same memory array are the same; the memory cells belonging to different memory arrays The difference, for example, may be that memory cells belonging to different memory arrays have different circuit structures, or may be that memory cells belonging to different memory arrays have the same circuit structure and different sizes. The number of the storage modules, that is, the value of N, is determined according to the type of the storage unit to be verified. For example, if there are 8 types of storage units that need to be verified, then the number of storage modules is 8, that is, the value of N is 8. In this embodiment, the anti-single event upset characteristic of the static random access memory is verified, so each storage unit is a static random access storage unit. Certainly, each storage unit may also be another storage unit, which is determined according to the actual object to be verified. Further, the number of storage units in each storage array can be set to be the same.

所述块译码器10用于对块地址信号进行译码,以选通一个存储模块中的行译码器和列译码器。具体地,所述块译码器10的每个输入端对应连接一条块地址线,所述块译码器10的每个输出端对应连接一个存储模块中的行译码器的使能端和列译码器的使能端。所述块译码器10的输入端连接的块地址线数量根据所述存储模块的数量确定,即2W=N,其中,W为所述块译码器10连接的块地址线数量。以所述存储模块的数量为8,即N的取值为8为例,所述块译码器10的输入端总共连接3条块地址线,即所述块译码器10为3线-8线译码器。The block decoder 10 is used to decode the block address signal to gate the row decoder and the column decoder in a memory module. Specifically, each input end of the block decoder 10 is correspondingly connected to a block address line, and each output end of the block decoder 10 is correspondingly connected to the enable end and the row decoder in a memory module. The enable terminal of the column decoder. The number of block address lines connected to the input of the block decoder 10 is determined according to the number of the memory modules, that is, 2 W =N, where W is the number of block address lines connected to the block decoder 10 . Taking the number of the storage modules as 8, that is, the value of N is 8 as an example, the input end of the block decoder 10 is connected to 3 block address lines in total, that is, the block decoder 10 is 3-wire- 8-line decoder.

当块地址信号为二进制数据000时,存储模块11中的列译码器111和行译码器112被选通,即列译码器111和行译码器112工作,其他存储模块中的列译码器和行译码器不工作;当块地址信号为二进制数据001时,存储模块12中的列译码器121和行译码器122被选通,即列译码器121和行译码器122工作,其他存储模块中的列译码器和行译码器不工作;…;当块地址信号为二进制数据110时,存储模块11中的列译码器171和行译码器172被选通,即列译码器171和行译码器172工作,其他存储模块中的列译码器和行译码器不工作;当块地址信号为二进制数据111时,存储模块12中的列译码器181和行译码器182被选通,即列译码器181和行译码器182工作,其他存储模块中的列译码器和行译码器不工作。When the block address signal is binary data 000, the column decoder 111 and the row decoder 112 in the storage module 11 are strobed, that is, the column decoder 111 and the row decoder 112 work, and the columns in other storage modules The decoder and the row decoder do not work; when the block address signal is binary data 001, the column decoder 121 and the row decoder 122 in the storage module 12 are gated, that is, the column decoder 121 and the row decoder Decoder 122 works, column decoder and row decoder in other storage modules do not work; ...; when the block address signal is binary data 110, column decoder 171 and row decoder 172 in storage module 11 Be gated, that is, column decoder 171 and row decoder 172 work, column decoder and row decoder in other memory modules do not work; when block address signal is binary data 111, memory module 12 The column decoder 181 and the row decoder 182 are gated, that is, the column decoder 181 and the row decoder 182 work, and the column decoders and row decoders in other memory modules do not work.

所述列译码器用于对列地址信号进行译码,以选通所述列译码器所在存储模块中的存储阵列的一列存储单元。具体地,所述列译码器的输入端连接的列地址线数量根据所述存储阵列的列数量确定,即2U=L,其中,U为所述列译码器连接的列地址线数量,L为所述存储阵列的列数量。以所述存储阵列的列数量为8,即L的取值为8为例,所述列译码器的输入端总共连接3条列地址线,即所述列译码器为3线-8线译码器。当列地址信号为二进制数据000且所述列译码器111被选通时,所述存储阵列113的第一列存储单元被选中;当列地址信号为二进制数据001且所述列译码器111被选通时,所述存储阵列113的第二列存储单元被选中;…;当列地址信号为二进制数据110且所述列译码器111被选通时,所述存储阵列113的第七列存储单元被选中;当列地址信号为二进制数据111且所述列译码器111被选通时,所述存储阵列113的第八列存储单元被选中。The column decoder is used to decode the column address signal to select a column of memory cells of the memory array in the memory module where the column decoder is located. Specifically, the number of column address lines connected to the input end of the column decoder is determined according to the number of columns of the memory array, that is, 2 U = L, where U is the number of column address lines connected to the column decoder , L is the number of columns of the storage array. Taking the number of columns of the memory array as 8, that is, the value of L is 8 as an example, the input end of the column decoder is connected to 3 column address lines in total, that is, the column decoder is 3 lines-8 line decoder. When the column address signal is binary data 000 and the column decoder 111 is strobed, the first column memory cell of the memory array 113 is selected; when the column address signal is binary data 001 and the column decoder When 111 is strobed, the second column storage unit of the memory array 113 is selected; ...; when the column address signal is binary data 110 and the column decoder 111 is gated, the second row of the memory array 113 Seven columns of memory cells are selected; when the column address signal is binary data 111 and the column decoder 111 is strobed, the eighth column of memory cells of the memory array 113 is selected.

所述行译码器用于对行地址信号进行译码,以选通所述行译码器所在存储模块中的存储阵列的一行存储单元。具体地,所述行译码器的输入端连接的行地址线数量根据所述存储阵列的行数量确定,即2V=M,其中,V为所述行译码器连接的行地址线数量,M为所述存储阵列的行数量。以所述存储阵列的行数量为8,即M的取值为8为例,所述行译码器的输入端总共连接3条行地址线,即所述行译码器为3线-8线译码器。当行地址信号为二进制数据000且所述行译码器112被选通时,所述存储阵列113的第一行存储单元被选中;当行地址信号为二进制数据001且所述行译码器112被选通时,所述存储阵列113的第二行存储单元被选中;…;当行地址信号为二进制数据110且所述行译码器112被选通时,所述存储阵列113的第七行存储单元被选中;当行地址信号为二进制数据111且所述行译码器112被选通时,所述存储阵列113的第八行存储单元被选中。The row decoder is used to decode the row address signal to select a row of memory cells of the memory array in the memory module where the row decoder is located. Specifically, the number of row address lines connected to the input of the row decoder is determined according to the number of rows of the memory array, that is, 2 V = M, where V is the number of row address lines connected to the row decoder , M is the number of rows of the storage array. Taking the number of rows of the memory array as 8, that is, the value of M is 8 as an example, the input end of the row decoder is connected to 3 row address lines in total, that is, the row decoder is 3 lines-8 line decoder. When the row address signal is binary data 000 and the row decoder 112 is strobed, the first row memory cell of the memory array 113 is selected; when the row address signal is binary data 001 and the row decoder 112 is selected When strobing, the second row of memory cells of the memory array 113 is selected; ...; when the row address signal is binary data 110 and the row decoder 112 is strobed, the seventh row of the memory array 113 stores The cell is selected; when the row address signal is binary data 111 and the row decoder 112 is strobed, the memory cell in the eighth row of the memory array 113 is selected.

需要说明的是,所有列译码器均连接所述列地址线,所述行译码器均连接所述行地址线,通过所述块译码器10进行译码,每次只有一个存储模块中的行译码器和列译码器工作。所述列地址线和所述行地址线的总数量根据所述存储阵列的存储容量确定,例如,若所述存储阵列的存储容量8Kbit,则所述列地址线和所述行地址线的总数量为13。It should be noted that all column decoders are connected to the column address lines, and the row decoders are connected to the row address lines, and are decoded by the block decoder 10, and each time there is only one memory module The row decoder and column decoder in work. The total number of the column address lines and the row address lines is determined according to the storage capacity of the storage array, for example, if the storage capacity of the storage array is 8Kbit, the total number of the column address lines and the row address lines The quantity is 13.

需要说明的是,与常规的存储器类似,所述存储器验证电路还包括读取电路和控制电路。所述读取电路用于读取每个存储单元存储的数据,所述控制电路用于向所述列译码器和所述读取电路提供读写控制信号。所述读取电路和所述控制电路的结构与现有技术中相同,并非本发明的改进点,本实施例对此不再赘述。It should be noted that, similar to a conventional memory, the memory verification circuit further includes a read circuit and a control circuit. The read circuit is used to read data stored in each storage unit, and the control circuit is used to provide read and write control signals to the column decoder and the read circuit. The structures of the reading circuit and the control circuit are the same as those in the prior art, which are not improvements of the present invention, and will not be repeated in this embodiment.

为更好地说明所述存储器验证电路的结构,图2给出了一种包括四个存储阵列、每个存储阵列包括四行、四列存储单元的存储器验证电路。其中,A1A2为所述块译码器10接收的块地址信号,所述行译码器10通过对块地址信号A1A2进行译码,获得四路输出信号EN1、EN2、EN3以及EN4,并将四路输出信号EN1、EN2、EN3以及EN4分别作为每个存储阵列中的行译码器和列译码的使能信号,即EN1作为列译码器111和行译码器112的使能信号,EN2作为列译码器121和行译码器122的使能信号,EN3作为列译码器131和行译码器132的使能信号,EN4作为列译码器141和行译码器142的使能信号;A3A4为各个行译码器接收的行地址信号,A5A6为各个列译码器接收的列地址信号。To better illustrate the structure of the memory verification circuit, FIG. 2 shows a memory verification circuit including four memory arrays, each memory array including four rows and four columns of memory cells. Wherein, A1A2 is the block address signal received by the block decoder 10, and the row decoder 10 obtains four output signals EN1, EN2, EN3 and EN4 by decoding the block address signal A1A2, and converts the four Road output signals EN1, EN2, EN3 and EN4 are respectively used as the enable signals of the row decoder and column decoder in each memory array, that is, EN1 is used as the enable signal of the column decoder 111 and the row decoder 112, EN2 is used as the enable signal of the column decoder 121 and the row decoder 122, EN3 is used as the enable signal of the column decoder 131 and the row decoder 132, and EN4 is used as the enable signal of the column decoder 141 and the row decoder 142. Enable signal; A3A4 is the row address signal received by each row decoder, and A5A6 is the column address signal received by each column decoder.

实施例2Example 2

本实施例提供另一种存储器验证电路,图3是所述存储器验证电路的结构示意图。所述存储器验证电路包括行译码器31、列译码器32以及存储阵列33。This embodiment provides another memory verification circuit, and FIG. 3 is a schematic structural diagram of the memory verification circuit. The memory verification circuit includes a row decoder 31 , a column decoder 32 and a memory array 33 .

所述存储阵列33包括呈阵列排布的存储单元,所述呈阵列排布的存储单元被划分为N个存储区域(存储区域331、存储区域332、…、存储区域33N),其中,属于相同存储区域的存储单元相同,即位于同一个存储区域中的所有存储单元的电路结构和尺寸均相同;属于不同存储区域的存储单元不同,例如,可以是属于不同存储区域的存储单元的电路结构不同,也可以是属于不同存储区域的存储单元的电路结构相同、尺寸不同。所述存储区域的数量,即N的取值,是根据需要验证的存储单元的种类确定的。例如,需要验证的存储单元的种类为8种,则所述存储模块的数量为8,即N的取值为8。在本实施例中,验证的是静态随机存取存储器抗单粒子翻转特性,因而每个存储单元均为静态随机存取存储单元。当然,每个存储单元也可以为其他存储单元,具体根据实际需要验证的对象确定。进一步,所述每个存储区域中的存储单元数量可以设置为均相同。The storage array 33 includes storage units arranged in an array, and the storage units arranged in an array are divided into N storage areas (storage area 331, storage area 332, ..., storage area 33N), wherein, belonging to the same The storage units in the storage area are the same, that is, the circuit structure and size of all the storage units in the same storage area are the same; the storage units belonging to different storage areas are different, for example, the circuit structures of the storage units belonging to different storage areas may be different , it is also possible that memory cells belonging to different memory areas have the same circuit structure and different sizes. The number of the storage areas, that is, the value of N, is determined according to the type of the storage unit to be verified. For example, if there are 8 types of storage units that need to be verified, then the number of storage modules is 8, that is, the value of N is 8. In this embodiment, the anti-single event upset characteristic of the static random access memory is verified, so each storage unit is a static random access storage unit. Certainly, each storage unit may also be another storage unit, which is determined according to the actual object to be verified. Further, the number of storage units in each storage area may be set to be the same.

所述行译码器31用于对行地址信号进行译码,以选通所述存储阵列33的一行存储单元。具体地,所述行译码器31的输入端连接的行地址线数量根据所述存储阵列的行数量确定,即2V=M,其中,V为所述行译码器31连接的行地址线数量,M为所述存储阵列33的行数量。以所述存储阵列33的行数量为8,即M的取值为8为例,所述行译码器31的输入端总共连接3条行地址线,即所述行译码器31为3线-8线译码器。当行地址信号为二进制数据000时,所述存储阵列33的第一行存储单元被选中;当行地址信号为二进制数据001时,所述存储阵列33的第二行存储单元被选中;…;当行地址信号为二进制数据110时,所述存储阵列33的第七行存储单元被选中;当行地址信号为二进制数据111时,所述存储阵列33的第八行存储单元被选中。The row decoder 31 is used for decoding row address signals to select a row of memory cells of the memory array 33 . Specifically, the number of row address lines connected to the input end of the row decoder 31 is determined according to the number of rows of the memory array, that is, 2 V =M, where V is the row address connected to the row decoder 31 The number of lines, M is the number of lines of the storage array 33. Take the number of rows of the memory array 33 as 8, that is, the value of M is 8 as an example, the input end of the row decoder 31 is connected to 3 row address lines in total, that is, the row decoder 31 is 3 Line - 8 line decoder. When the row address signal was binary data 000, the first row storage unit of the storage array 33 was selected; when the row address signal was binary data 001, the second row storage unit of the storage array 33 was selected; ...; when the row address When the signal is binary data 110, the storage unit in the seventh row of the memory array 33 is selected; when the row address signal is binary data 111, the storage unit in the eighth row of the storage array 33 is selected.

所述列译码器32用于对列地址信号进行译码,以选通所述存储阵列33的一列存储单元。具体地,所述列译码器32的输入端连接的列地址线数量根据所述存储阵列33的列数量确定,即2U=L,其中,U为所述列译码器32连接的列地址线数量,L为所述存储阵列33的列数量。以所述存储阵列33的列数量为8,即L的取值为8为例,所述列译码器32的输入端总共连接3条列地址线,即所述列译码器32为3线-8线译码器。当列地址信号为二进制数据000时,所述存储阵列33的第一列存储单元被选中;当列地址信号为二进制数据001时,所述存储阵列33的第二列存储单元被选中;…;当列地址信号为二进制数据110时,所述存储阵列33的第七列存储单元被选中;当列地址信号为二进制数据111时,所述存储阵列33的第八列存储单元被选中。The column decoder 32 is used to decode a column address signal to select a column of memory cells of the memory array 33 . Specifically, the number of column address lines connected to the input end of the column decoder 32 is determined according to the number of columns of the storage array 33, that is, 2 U =L, where U is the column connected to the column decoder 32 The number of address lines, L is the number of columns of the storage array 33 . Taking the number of columns of the memory array 33 as 8, that is, the value of L is 8 as an example, the input terminals of the column decoder 32 are connected to 3 column address lines in total, that is, the column decoder 32 is 3 Line - 8 line decoder. When the column address signal is binary data 000, the first column storage unit of the storage array 33 is selected; when the column address signal is binary data 001, the second column storage unit of the storage array 33 is selected;  …; When the column address signal is binary data 110, the storage unit in the seventh column of the memory array 33 is selected; when the column address signal is binary data 111, the storage unit in the eighth column of the storage array 33 is selected.

需要说明的是,所述列地址线和所述行地址线的总数量根据所述存储阵列33的存储容量确定,例如,若所述存储阵列33的存储容量8Kbit,则所述列地址线和所述行地址线的总数量为13。与常规的存储器类似,所述存储器验证电路还包括读取电路和控制电路。所述读取电路用于读取每个存储单元存储的数据,所述控制电路用于向所述列译码器和所述读取电路提供读写控制信号。所述读取电路和所述控制电路的结构与现有技术中相同,并非本发明的改进点,本实施例对此不再赘述。It should be noted that the total number of the column address lines and the row address lines is determined according to the storage capacity of the storage array 33, for example, if the storage capacity of the storage array 33 is 8Kbit, the column address lines and The total number of row address lines is thirteen. Similar to a conventional memory, the memory verification circuit also includes a read circuit and a control circuit. The read circuit is used to read data stored in each storage unit, and the control circuit is used to provide read and write control signals to the column decoder and the read circuit. The structures of the reading circuit and the control circuit are the same as those in the prior art, which are not improvements of the present invention, and will not be repeated in this embodiment.

为更好地说明所述存储器验证电路的结构,图4给出了一种所述存储阵列33包括四个存储区域、每个存储区域包括四行、四列存储单元的存储器验证电路,其中,A1A2A3为所述行译码器31接收的行地址信号,A4A5A6为所述列译码器32接收的列地址信号。In order to better illustrate the structure of the memory verification circuit, FIG. 4 shows a memory verification circuit in which the memory array 33 includes four storage areas, and each storage area includes four rows and four columns of memory cells, wherein, A1A2A3 is the row address signal received by the row decoder 31 , and A4A5A6 is the column address signal received by the column decoder 32 .

实施例3Example 3

基于实施例1或者实施例2提供的存储器验证电路,本实施例还提供一种存储器验证方法。在本实施例中,所述存储器验证方法用于验证静态随机存取存储器抗单粒子翻转特性。当然,上述存储器验证电路并不限于验证静态随机存取存储器抗单粒子翻转特性,例如,还可以用于验证存储单元的噪声容限等,本实施例对此不进行限定。图5是所述存储器验证方法的流程图,所述存储器验证方法包括:Based on the memory verification circuit provided in Embodiment 1 or Embodiment 2, this embodiment also provides a memory verification method. In this embodiment, the memory verification method is used for verifying the anti-single event upset characteristic of the static random access memory. Of course, the above memory verification circuit is not limited to verifying the anti-single event upset characteristic of the SRAM, for example, it can also be used to verify the noise tolerance of the storage unit, etc., which is not limited in this embodiment. Fig. 5 is the flow chart of described memory verification method, and described memory verification method comprises:

步骤S1,对所述存储阵列写满验证数据。具体地,针对实施例1提供的存储器验证电路,通过所述块译码器10对块地址信号进行译码,选中存储模块中的列译码器和行译码器;通过所述列译码器对列地址信号进行译码和所述行译码器对行地址信号进行译码,选中存储阵列中的存储单元。依次选中每个存储单元,对应写入一位数据,直至所有存储单元都被写入数据,即写满所述每个存储阵列。所述验证数据可根据实际需求进行设置,在本实施例中,所述验证数据为十六进制数据55AA,即二进制数据0101010110101010。针对实施例2提供的存储器验证电路,直接通过所述列译码器32对列地址信号进行译码和所述行译码器31对行地址信号进行译码,选中所述存储阵列33中的存储单元。Step S1, filling the storage array with verification data. Specifically, for the memory verification circuit provided in Embodiment 1, the block address signal is decoded by the block decoder 10, and the column decoder and the row decoder in the memory module are selected; The decoder decodes the column address signal and the row decoder decodes the row address signal to select the storage unit in the storage array. Each storage unit is selected in turn, and one bit of data is written correspondingly until all storage units are written with data, that is, each storage array is filled. The verification data can be set according to actual needs. In this embodiment, the verification data is hexadecimal data 55AA, that is, binary data 0101010110101010. For the memory verification circuit provided in Embodiment 2, the column address signal is decoded directly by the column decoder 32 and the row address signal is decoded by the row decoder 31, and the memory array 33 is selected storage unit.

步骤S2,单粒子入射所述存储阵列。利用单粒子效应产生的各种辐照源,例如加速器提供的离子,辐照所述存储器验证电路。当入射的离子累计到实验要求的注量后,停止辐照。In step S2, a single particle is incident on the storage array. The memory verification circuit is irradiated with various radiation sources generated by single event effects, such as ions provided by an accelerator. When the incident ions accumulated to the fluence required by the experiment, the irradiation was stopped.

步骤S3,读取每个存储单元存储的数据。具体地,针对实施例1提供的存储器验证电路,通过所述块译码器10对块地址信号进行译码,选中存储模块中的列译码器和行译码器;通过所述列译码器对列地址信号进行译码和所述行译码器对行地址信号进行译码,选中存储阵列中的存储单元。依次选中每个存储单元,对应读出一位数据,直至所有存储单元存储的数据都被读出。针对实施例2提供的存储器验证电路,直接通过所述列译码器32对列地址信号进行译码和所述行译码器31对行地址信号进行译码,选中所述存储阵列33中的存储单元进行读取。Step S3, reading the data stored in each storage unit. Specifically, for the memory verification circuit provided in Embodiment 1, the block address signal is decoded by the block decoder 10, and the column decoder and the row decoder in the memory module are selected; The decoder decodes the column address signal and the row decoder decodes the row address signal to select the storage unit in the storage array. Each storage unit is selected in turn, and one bit of data is read out correspondingly, until the data stored in all storage units are read out. For the memory verification circuit provided in Embodiment 2, the column address signal is decoded directly by the column decoder 32 and the row address signal is decoded by the row decoder 31, and the memory array 33 is selected memory cells to be read.

步骤S4,根据写入所述每个存储单元的数据和从所述每个存储单元读出的数据,确定发生错误的存储单元。对比写入所述每个存储单元的数据和从所述每个存储单元读出的数据,若从某个存储单元读出的数据与写入该存储单元的数据相同,则该存储单元存储的数据正确,未发生单粒子翻转效应;若从某个存储单元读出的数据与写入该存储单元的数据不同,则该存储单元发生了单粒子翻转效应,该存储单元是发生错误的存储单元。Step S4, according to the data written into each storage unit and the data read from each storage unit, determine the storage unit where the error occurs. Comparing the data written into each storage unit with the data read from each storage unit, if the data read from a storage unit is the same as the data written into the storage unit, then the storage unit stored The data is correct, and the single event reversal effect has not occurred; if the data read from a certain storage unit is different from the data written to the storage unit, the single event reversal effect has occurred in the storage unit, and the storage unit is an error storage unit .

步骤S5,根据发生错误的存储单元对应的地址,获得每种存储单元中发生错误的存储单元的数量。由于每个存储单元对应的地址是唯一的,根据发生错误的存储单元对应的地址,可以获得发生错误的存储单元对应的块地址信号,进而获得发生错误的存储单元所在的存储阵列或者存储区域。对每个存储阵列或者存储区域发生错误的存储单元的数量进行统计,可以得出每种存储单元抗单粒子翻转特性。Step S5, according to the address corresponding to the storage unit where the error occurred, the number of the storage unit where the error occurred in each type of storage unit is obtained. Since the address corresponding to each storage unit is unique, according to the address corresponding to the storage unit where the error occurs, the block address signal corresponding to the storage unit where the error occurs can be obtained, and then the storage array or storage area where the storage unit where the error occurs can be obtained. By counting the number of storage units with errors in each storage array or storage area, the anti-single event upset characteristic of each storage unit can be obtained.

由于进行抗单粒子翻转性能实验时,每个离子在单位时间内射中存储结构的单位面积的概率是一定的,存储结构的面积越大,则在较短的时间就可以入射一定量的离子,实验的时间也就越短。而本实施例提供的存储器验证电路包括了不同种类的存储单元,增大了存储结构的面积,因而在较短的时间就可以入射一定量的离子,能够提高验证效率。并且,本发明提供的存储器验证电路能够对不同存储单元同时进行验证,大大降低了电路设计、制版以及实验成本,具有很大的应用价值。Since the probability of each ion hitting the unit area of the storage structure in a unit time is certain when conducting the anti-single event flipping performance experiment, the larger the area of the storage structure, the more ions can be incident in a shorter time. The experiment time is also shorter. However, the memory verification circuit provided by this embodiment includes different types of memory cells, which increases the area of the memory structure, so that a certain amount of ions can be injected in a relatively short time, and the verification efficiency can be improved. Moreover, the memory verification circuit provided by the present invention can verify different memory units at the same time, which greatly reduces the cost of circuit design, plate making and experimentation, and has great application value.

以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (10)

1.一种存储器验证电路,其特征在于,包括行译码器、列译码器以及存储阵列,所述存储阵列包括呈阵列排布的存储单元,所述呈阵列排布的存储单元被划分为两个以上存储区域,属于相同存储区域的存储单元相同,属于不同存储区域的存储单元不同;1. A memory verification circuit, characterized in that it comprises a row decoder, a column decoder and a memory array, the memory array includes memory cells arranged in an array, and the memory cells arranged in an array are divided into For more than two storage areas, the storage units belonging to the same storage area are the same, and the storage units belonging to different storage areas are different; 所述行译码器用于对行地址信号进行译码,以选通所述存储阵列的一行存储单元;The row decoder is used to decode a row address signal to select a row of memory cells of the memory array; 所述列译码器用于对列地址信号进行译码,以选通所述存储阵列的一列存储单元。The column decoder is used to decode the column address signal to select a column of memory cells of the memory array. 2.根据权利要求1所述的存储器验证电路,其特征在于,属于不同存储区域的存储单元的电路结构不同;或者,2. The memory verification circuit according to claim 1, wherein the circuit structures of memory cells belonging to different memory areas are different; or, 属于不同存储区域的存储单元的电路结构相同、尺寸不同。Memory cells belonging to different memory areas have the same circuit structure and different sizes. 3.根据权利要求1所述的存储器验证电路,其特征在于,还包括读取电路和控制电路;3. The memory verification circuit according to claim 1, further comprising a read circuit and a control circuit; 所述读取电路用于读取每个存储单元存储的数据;The reading circuit is used to read the data stored in each storage unit; 所述控制电路用于向所述列译码器和所述读取电路提供读写控制信号。The control circuit is used to provide read and write control signals to the column decoder and the read circuit. 4.根据权利要求1所述的存储器验证电路,其特征在于,所述每个存储区域中的存储单元数量均相同。4. The memory verification circuit according to claim 1, wherein the number of storage cells in each storage area is the same. 5.一种存储器验证电路,其特征在于,包括块译码器和两个以上存储模块,每个存储模块包括行译码器、列译码器以及存储阵列,每个存储阵列包括呈阵列排布的存储单元,属于相同存储阵列的存储单元相同,属于不同存储阵列的存储单元不同;5. A memory verification circuit, characterized in that it includes a block decoder and more than two memory modules, each memory module includes a row decoder, a column decoder and a memory array, and each memory array includes a memory array arranged in an array The storage units of the same storage array are the same, and the storage units belonging to different storage arrays are different; 所述块译码器用于对块地址信号进行译码,以选通一个存储模块中的行译码器和列译码器;The block decoder is used to decode the block address signal to gate the row decoder and the column decoder in a memory module; 所述行译码器用于对行地址信号进行译码,以选通所述行译码器所在存储模块中的存储阵列的一行存储单元;The row decoder is used to decode the row address signal to select a row of memory cells of the memory array in the memory module where the row decoder is located; 所述列译码器用于对列地址信号进行译码,以选通所述列译码器所在存储模块中的存储阵列的一列存储单元。The column decoder is used to decode the column address signal to select a column of memory cells of the memory array in the memory module where the column decoder is located. 6.根据权利要求5所述的存储器验证电路,其特征在于,属于不同存储阵列的存储单元的电路结构不同;或者,6. The memory verification circuit according to claim 5, wherein the memory cells belonging to different memory arrays have different circuit structures; or, 属于不同存储阵列的存储单元的电路结构相同、尺寸不同。Memory cells belonging to different memory arrays have the same circuit structure but different sizes. 7.根据权利要求5所述的存储器验证电路,其特征在于,还包括读取电路和控制电路;7. The memory verification circuit according to claim 5, further comprising a read circuit and a control circuit; 所述读取电路用于读取每个存储单元存储的数据;The reading circuit is used to read the data stored in each storage unit; 所述控制电路用于向所述列译码器和所述读取电路提供读写控制信号。The control circuit is used to provide read and write control signals to the column decoder and the read circuit. 8.根据权利要求5所述的存储器验证电路,其特征在于,所述每个存储阵列中的存储单元数量均相同。8. The memory verification circuit according to claim 5, wherein the number of memory cells in each memory array is the same. 9.一种存储器验证方法,应用于权利要求1至8任一项所述的存储器验证电路,其特征在于,包括:9. A memory verification method, applied to the memory verification circuit according to any one of claims 1 to 8, characterized in that, comprising: 对所述存储阵列写满验证数据;Filling the storage array with verification data; 单粒子入射所述存储阵列;a single event incident on the storage array; 读取每个存储单元存储的数据;Read the data stored in each storage unit; 根据写入所述每个存储单元的数据和从所述每个存储单元读出的数据,确定发生错误的存储单元;determining the storage unit in which an error occurs according to the data written into each storage unit and the data read from each storage unit; 根据发生错误的存储单元对应的地址,获得每种存储单元中发生错误的存储单元的数量。According to the address corresponding to the storage unit in which the error occurred, the number of the storage unit in which the error occurred in each type of storage unit is obtained. 10.根据权利要求9所述的存储器验证方法,其特征在于,所述验证数据为十六进制数据55AA。10. The memory verification method according to claim 9, wherein the verification data is hexadecimal data 55AA.
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