CN110111833A - Memory verification circuit and verification method - Google Patents
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- CN110111833A CN110111833A CN201910263759.1A CN201910263759A CN110111833A CN 110111833 A CN110111833 A CN 110111833A CN 201910263759 A CN201910263759 A CN 201910263759A CN 110111833 A CN110111833 A CN 110111833A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The invention discloses a kind of memory verification circuit and verification methods, the verifying circuit includes Block decoder and more than two memory modules, each memory module includes line decoder, column decoder and storage array, each storage array includes the storage unit being arranged in array, the storage unit for belonging to identical storage array is identical, and the storage unit for belonging to different storage arrays is different；Block decoder is for decoding block address signal, to gate line decoder and column decoder in a memory module；Line decoder for being decoded to row address signal, with gate the line decoder storage array in a storage module a line storage unit；Column decoder for being decoded to column address signal, with gate the column decoder storage array in a storage module an array storage unit.Memory verification circuit and verification method provided by the invention can be improved the verification efficiency of memory verification, reduce the verifying cost of memory verification.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a memory verification circuit and a verification method.
Background
With the continuous exploration of human beings in the space field, the radiation environment to which space equipment such as spacecrafts, satellites and the like faces is more and more complex. In these complex radiation environments, the single event effect is very serious, and may cause logical confusion of the control system of the space equipment. The single event effect is a radiation effect which causes abnormal change of the state of a microelectronic device when a single high-energy particle passes through a sensitive region of the microelectronic device, and comprises single event upset, single event locking, single event burnout, single event gate breakdown and the like.
A Static Random Access Memory (SRAM) is a Memory having a Static Access function, and has been widely used as a cache Memory because of its characteristics of high read/write speed and no need of refresh. In particular to a static random access memory for space application, the single event upset resistance of the static random access memory directly influences the reliability of a control system of space equipment. In static random access memory, the most sensitive to single event upsets are memory cells with a latch structure. The simulation experiment of single event upset by heavy particles generated by an accelerator is an effective verification method for verifying the single event upset resistance of the static random access memory. However, the conventional method for verifying the single event upset resistance of the static random access memory can only verify the single event upset resistance of one memory cell at the same time, and has low verification efficiency and higher verification cost.
Disclosure of Invention
The invention aims to solve the problems of low efficiency and high cost of verifying the memory.
The invention is realized by the following technical scheme:
a memory verification circuit comprises a row decoder, a column decoder and a memory array, wherein the memory array comprises memory cells arranged in an array, the memory cells arranged in the array are divided into more than two memory areas, the memory cells belonging to the same memory area are the same, and the memory cells belonging to different memory areas are different;
the row decoder is used for decoding row address signals to gate a row of memory cells of the memory array;
the column decoder is used for decoding a column address signal so as to gate a column of memory cells of the memory array.
Optionally, the circuit structures of the memory cells belonging to different memory regions are different; or,
the memory cells belonging to different memory regions have the same circuit structure and different sizes.
Optionally, the memory verification circuit further includes a read circuit and a control circuit;
the reading circuit is used for reading the data stored in each storage unit;
the control circuit is used for providing read-write control signals for the column decoder and the reading circuit.
Optionally, the number of the storage units in each storage area is the same.
Based on the same inventive concept, the invention also provides another memory verification circuit, which comprises a block decoder and more than two memory modules, wherein each memory module comprises a row decoder, a column decoder and a memory array, each memory array comprises memory units arranged in an array, the memory units belonging to the same memory array are the same, and the memory units belonging to different memory arrays are different;
the block decoder is used for decoding the block address signal so as to gate a row decoder and a column decoder in one storage module;
the row decoder is used for decoding the row address signal so as to gate a row of memory cells of the memory array in the memory module where the row decoder is located;
the column decoder is used for decoding the column address signal so as to gate a column of memory cells of the memory array in the memory module where the column decoder is located.
Optionally, the circuit structures of the memory cells belonging to different memory arrays are different; or,
the memory cells belonging to different memory arrays have the same circuit structure and different sizes.
Optionally, the memory verification circuit further includes a read circuit and a control circuit;
the reading circuit is used for reading the data stored in each memory array;
the control circuit is used for providing read-write control signals for the column decoder and the reading circuit.
Optionally, the number of the storage modules is determined according to the kind of the storage units to be verified.
Optionally, the number of the memory cells in each memory array is the same.
Based on the same inventive concept, the invention also provides a memory verification method, which is applied to the memory verification circuit and comprises the following steps:
writing full verification data to the storage array;
single particles are incident to the storage array;
reading data stored in each storage unit;
determining a memory cell in which an error occurs based on the data written into and the data read out from each memory cell;
and acquiring the number of the memory units with errors in each memory unit according to the addresses corresponding to the memory units with errors.
Optionally, the verification data is hexadecimal data 55 AA.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the memory verification circuit and the verification method provided by the invention can simultaneously verify the performances of different memory units, such as single event upset resistance, by setting more than two memory areas or more than two memory modules. When the single-particle-upset resistance experiment is carried out, the probability of each ion in the unit area of the storage structure in unit time is constant, and the larger the area of the storage structure is, a certain amount of ions can be injected in a shorter time, so that the experiment time is shorter. The memory verification circuit provided by the invention comprises different types of memory cells, and the area of the memory structure is increased, so that a certain amount of ions can be incident in a short time, and the verification efficiency can be improved. In addition, the memory verification circuit provided by the invention can simultaneously verify different memory units, thereby greatly reducing the cost of circuit design, plate making and experiment and having great application value.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of a memory verification circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a memory verification circuit according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a memory verification circuit according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of a memory verification circuit according to another embodiment of the present invention;
FIG. 5 is a flowchart of a memory verification method according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
The present embodiment provides a memory verification circuit, and fig. 1 is a schematic structural diagram of the memory verification circuit. The memory verification circuit includes a block decoder 10 and N memory blocks (memory block 11, memory block 12, …, memory block 1N), where N is an integer no less than 2.
Each memory module includes a row decoder, a column decoder, and a memory array. For example, the memory module 11 includes a column decoder 111, a row decoder 112, and a memory array 113; the memory module 12 includes a column decoder 121, a row decoder 122, and a memory array 123; …, respectively; the memory module 1N includes a column decoder 1N1, a row decoder 1N2, and a memory array 1N 3. Each storage array comprises storage units arranged in an array, wherein the storage units belonging to the same storage array are the same, namely the circuit structures and the sizes of all the storage units in the same storage array are the same; the memory cells belonging to different memory arrays may be different, for example, the circuit structures of the memory cells belonging to different memory arrays may be different, or the circuit structures of the memory cells belonging to different memory arrays may be the same and the sizes thereof may be different. The number of the storage modules, i.e. the value of N, is determined according to the kind of the storage unit to be verified. For example, if the types of the memory cells to be verified are 8, the number of the memory modules is 8, that is, the value of N is 8. In the present embodiment, the single event upset resistance of the sram is verified, and thus each memory cell is a sram cell. Of course, each storage unit may also be other storage units, and is specifically determined according to an object that needs to be verified. Further, the number of memory cells in each of the memory arrays may be set to be the same.
The block decoder 10 is used to decode block address signals to gate row and column decoders within a memory module. Specifically, each input end of the block decoder 10 is correspondingly connected to one block address line, and each output end of the block decoder 10 is correspondingly connected to an enable end of a row decoder and an enable end of a column decoder in one memory module. The number of block address lines connected to the input of the block decoder 10 is determined by the number of memory modules, i.e. 2WWhere W is the number of block address lines to which the block decoder 10 is connected. Taking the number of the memory modules as 8, that is, the value of N is 8 as an example, the input end of the block decoder 10 is connected with 3 block address lines in total, that is, the block decoder 10 is a 3-to-8-line decoder.
When the block address signal is binary data 000, the column decoder 111 and the row decoder 112 in the memory module 11 are selected, that is, the column decoder 111 and the row decoder 112 operate, and the column decoders and the row decoders in other memory modules do not operate; when the block address signal is binary data 001, the column decoder 121 and the row decoder 122 in the memory module 12 are selected, that is, the column decoder 121 and the row decoder 122 operate, and the column decoders and the row decoders in other memory modules do not operate; …, respectively; when the block address signal is the binary data 110, the column decoder 171 and the row decoder 172 in the memory module 11 are enabled, that is, the column decoder 171 and the row decoder 172 operate, and the column decoders and the row decoders in the other memory modules do not operate; when the block address signal is binary data 111, the column decoder 181 and the row decoder 182 in the memory module 12 are enabled, that is, the column decoder 181 and the row decoder 182 operate, and the column decoder and the row decoder in the other memory modules do not operate.
The column decoder is used for decoding the column address signal so as to gate a column of memory cells of the memory array in the memory module where the column decoder is located. In particular, the number of column address lines connected to the input of the column decoder is determined by the number of columns of the memory array, i.e. 2UWhere U is the number of column address lines to which the column decoder is connected and L is the number of columns of the memory array. Taking the example that the number of columns of the memory array is 8, that is, the value of L is 8, the input end of the column decoder is connected with 3 column address lines in total, that is, the column decoder is a 3-8 line decoder. When the column address signal is binary data 000 and the column decoder 111 is gated, a first column of memory cells of the memory array 113 is selected; when the column address signal is binary data 001 and the column decoder 111 is gated, the second column of memory cells of the memory array 113 is selected; …, respectively; when the column address signal is binary data 110 and the column decoder 111 is gated, a seventh column of memory cells of the memory array 113 is selected; when the column address signal is binary data 111 and the column decoder 111 is gated, an eighth column of memory cells of the memory array 113 is selected.
The row decoder is used for decoding the row address signal so as to gate a row of memory cells of the memory array in the memory module where the row decoder is located. In particular, the number of row address lines connected to the input of the row decoder is determined by the number of rows of the memory array, i.e. 2VWhere V is the number of row address lines to which the row decoder is connected and M is the number of rows of the memory array. Taking the number of rows of the memory array as 8, that is, the value of M is 8 as an example, the input end of the row decoder is connected with 3 row address lines in total, that is, the row decoder is a 3-8 line decoder. When the row address signal is binary data 000 and the row decoder 112 is gated, the first row of memory cells of the memory array 113 is selected; when the row address signal is binary data 001 and the row decoder 112 is gated, the second row of memory cells of the memory array 113 is selected; …, respectively; when the row address signal is binary data 110 and the row decoder 112 is gated, a seventh row of memory cells of the memory array 113 is selected; when the row address signal is binary data 111 and the row decoder 112 is gated, an eighth row of memory cells of the memory array 113 is selected.
It should be noted that all the column decoders are connected to the column address lines, the row decoders are connected to the row address lines, and the block decoder 10 performs decoding, and only the row decoder and the column decoder in one memory module operate at a time. The total number of the column address lines and the row address lines is determined according to the storage capacity of the memory array, for example, if the storage capacity of the memory array is 8Kbit, the total number of the column address lines and the row address lines is 13.
Note that the memory verification circuit further includes a read circuit and a control circuit, similar to a conventional memory. The reading circuit is used for reading the data stored in each storage unit, and the control circuit is used for providing reading and writing control signals for the column decoder and the reading circuit. The structures of the reading circuit and the control circuit are the same as those in the prior art, which is not the improvement point of the present invention, and the description of this embodiment is omitted.
To better illustrate the structure of the memory verification circuit, fig. 2 shows a memory verification circuit including four memory arrays, each including four rows and four columns of memory cells. Wherein A1a2 is a block address signal received by the block decoder 10, the row decoder 10 decodes the block address signal A1a2 to obtain four output signals EN1, EN2, EN3 and EN4, and uses the four output signals EN1, EN2, EN3 and EN4 as enable signals of row decoder and column decoder in each memory array, that is, EN1 is used as enable signals of the column decoder 111 and the row decoder 112, EN2 is used as enable signals of the column decoder 121 and the row decoder 122, EN3 is used as enable signals of the column decoder 131 and the row decoder 132, and EN4 is used as enable signals of the column decoder 141 and the row decoder 142; a3a4 is a row address signal received by each row decoder, and A5a6 is a column address signal received by each column decoder.
Example 2
The present embodiment provides another memory verification circuit, and fig. 3 is a schematic structural diagram of the memory verification circuit. The memory verification circuitry includes a row decoder 31, a column decoder 32, and a memory array 33.
The memory array 33 includes memory cells arranged in an array, and the memory cells arranged in an array are divided into N memory areas (memory area 331, memory areas 332, …, and memory area 33N), where the memory cells belonging to the same memory area are the same, that is, the circuit structures and the sizes of all the memory cells located in the same memory area are the same; the memory cells belonging to different memory regions may be different, for example, the memory cells belonging to different memory regions may have different circuit configurations, or the memory cells belonging to different memory regions may have the same circuit configuration and different sizes. The number of the storage areas, i.e. the value of N, is determined according to the kind of the storage unit to be verified. For example, if the types of the memory cells to be verified are 8, the number of the memory modules is 8, that is, the value of N is 8. In the present embodiment, the single event upset resistance of the sram is verified, and thus each memory cell is a sram cell. Of course, each storage unit may also be other storage units, and is specifically determined according to an object that needs to be verified. Further, the number of memory cells in each of the memory areas may be set to be the same.
The row decoder 31 is used for decoding a row address signal to gate a row of memory cells of the memory array 33. In particular, the number of row address lines connected to the input of the row decoder 31 is determined by the number of rows of the memory array, i.e. 2VWhere V is the number of row address lines to which the row decoder 31 is connected and M is the number of rows of the memory array 33. Taking the number of rows of the memory array 33 as 8, that is, the value of M is 8 as an example, the input end of the row decoder 31 is connected with 3 row address lines in total, that is, the row decoder 31 is a 3-line to 8-line decoder. When the row address signal is binary data 000, the first row of memory cells of the memory array 33 is selected; when the row address signal is binary data 001, the second row of memory cells of the memory array 33 is selected; …, respectively; when the row address signal is binary data 110, a seventh row of memory cells of the memory array 33 is selected; when the row address signal is binary data 111, the eighth row of memory cells of the memory array 33 is selected.
The column decoder 32 is configured to decode a column address signal to gate a column of memory cells of the memory array 33. Specifically, the number of column address lines connected to the input terminal of the column decoder 32 is determined according to the number of columns of the memory array 33, i.e., 2UWhere U is the number of column address lines to which the column decoder 32 is connected and L is the number of columns of the memory array 33. Taking the number of columns of the memory array 33 as 8, that is, the value of L is 8 as an example, the input end of the column decoder 32 is connected with 3 column address lines in total, that is, the column decoder 32 is a 3-line to 8-line decoder. When the column address signal is binary data 000, the first column of memory cells of the memory array 33 is selected; when the column address signal is binary data 001, the second column of memory cells of the memory array 33 is selected; …, respectively; when the column address signal is binary data 110, a seventh column of memory cells of the memory array 33 is selected; when the column address signal is binary data 111, the eighth column of memory cells of the memory array 33 is selected.
It should be noted that the total number of the column address lines and the row address lines is determined according to the storage capacity of the memory array 33, for example, if the storage capacity of the memory array 33 is 8Kbit, the total number of the column address lines and the row address lines is 13. The memory verification circuit further includes a read circuit and a control circuit, similar to a conventional memory. The reading circuit is used for reading the data stored in each storage unit, and the control circuit is used for providing reading and writing control signals for the column decoder and the reading circuit. The structures of the reading circuit and the control circuit are the same as those in the prior art, which is not the improvement point of the present invention, and the description of this embodiment is omitted.
To better illustrate the structure of the memory verification circuit, fig. 4 shows a memory verification circuit in which the memory array 33 includes four memory regions, each including four rows and four columns of memory cells, where A1A2A3 is a row address signal received by the row decoder 31, and A4A5a6 is a column address signal received by the column decoder 32.
Example 3
Based on the memory verification circuit provided in embodiment 1 or embodiment 2, this embodiment also provides a memory verification method. In this embodiment, the memory verification method is used for verifying the single event upset resistance of the sram. Of course, the memory verification circuit is not limited to verifying the anti-single event upset characteristic of the sram, and may also be used to verify the noise margin of the memory cell, for example, which is not limited in this embodiment. FIG. 5 is a flow chart of the memory verification method, which includes:
in step S1, the storage array is written with verification data. Specifically, for the memory verification circuit provided in embodiment 1, the block decoder 10 decodes a block address signal, and selects a column decoder and a row decoder in the memory module; and decoding the column address signals through the column decoder and decoding the row address signals through the row decoder, and selecting the memory cells in the memory array. And sequentially selecting each storage unit, and correspondingly writing one bit of data until all the storage units are written with data, namely, all the storage arrays are written with the data. The verification data may be set according to actual requirements, and in this embodiment, the verification data is hexadecimal data 55AA, that is, binary data 0101010110101010. With respect to the memory verification circuit provided in embodiment 2, the column decoder 32 decodes the column address signal and the row decoder 31 decodes the row address signal directly, and the memory cell in the memory array 33 is selected.
And step S2, the single particle is incident to the memory array. The memory verification circuitry is irradiated with various irradiation sources generated by a single event effect, such as ions provided by an accelerator. When the incident ions are accumulated to the fluence required by the experiment, the irradiation is stopped.
In step S3, the data stored in each memory cell is read. Specifically, for the memory verification circuit provided in embodiment 1, the block decoder 10 decodes a block address signal, and selects a column decoder and a row decoder in the memory module; and decoding the column address signals through the column decoder and decoding the row address signals through the row decoder, and selecting the memory cells in the memory array. And sequentially selecting each memory cell, and correspondingly reading one bit of data until the data stored in all the memory cells are read. For the memory verification circuit provided in embodiment 2, the column decoder 32 decodes the column address signal and the row decoder 31 decodes the row address signal directly, and the memory cell in the memory array 33 is selected and read.
Step S4 is to determine a memory cell in which an error has occurred based on the data written into and the data read from each memory cell. Comparing the data written into each memory cell with the data read out from each memory cell, wherein if the data read out from a certain memory cell is the same as the data written into the memory cell, the data stored in the memory cell is correct, and the single event upset effect does not occur; if the data read from a certain memory cell is different from the data written into the memory cell, the single event upset effect occurs in the memory cell, and the memory cell is an erroneous memory cell.
In step S5, the number of memory cells in which errors occur in each memory cell is obtained according to the address corresponding to the memory cell in which the error occurred. Because the address corresponding to each memory cell is unique, the block address signal corresponding to the memory cell with the error can be obtained according to the address corresponding to the memory cell with the error, and then the memory array or the memory area where the memory cell with the error is located can be obtained. Counting the number of the memory cells with errors in each memory array or memory area can obtain the single event upset resistance of each memory cell.
When the single-particle-upset resistance experiment is carried out, the probability of each ion in the unit area of the storage structure in unit time is constant, and the larger the area of the storage structure is, a certain amount of ions can be injected in a shorter time, so that the experiment time is shorter. The memory verification circuit provided by the embodiment comprises different types of memory cells, and the area of the memory structure is increased, so that a certain amount of ions can be incident in a short time, and the verification efficiency can be improved. In addition, the memory verification circuit provided by the invention can simultaneously verify different memory units, thereby greatly reducing the cost of circuit design, plate making and experiment and having great application value.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A memory verification circuit is characterized by comprising a row decoder, a column decoder and a memory array, wherein the memory array comprises memory cells arranged in an array, the memory cells arranged in the array are divided into more than two memory areas, the memory cells belonging to the same memory area are the same, and the memory cells belonging to different memory areas are different;
the row decoder is used for decoding row address signals to gate a row of memory cells of the memory array;
the column decoder is used for decoding a column address signal so as to gate a column of memory cells of the memory array.
2. The memory verification circuit according to claim 1, wherein the circuit structures of the memory cells belonging to different memory regions are different; or,
the memory cells belonging to different memory regions have the same circuit structure and different sizes.
3. The memory verification circuit of claim 1, further comprising a read circuit and a control circuit;
the reading circuit is used for reading the data stored in each storage unit;
the control circuit is used for providing read-write control signals for the column decoder and the reading circuit.
4. The memory verification circuit of claim 1, wherein the number of memory cells in each memory region is the same.
5. A memory verification circuit is characterized by comprising a block decoder and more than two memory modules, wherein each memory module comprises a row decoder, a column decoder and a memory array, each memory array comprises memory units arranged in an array, the memory units belonging to the same memory array are the same, and the memory units belonging to different memory arrays are different;
the block decoder is used for decoding the block address signal so as to gate a row decoder and a column decoder in one storage module;
the row decoder is used for decoding the row address signal so as to gate a row of memory cells of the memory array in the memory module where the row decoder is located;
the column decoder is used for decoding the column address signal so as to gate a column of memory cells of the memory array in the memory module where the column decoder is located.
6. The memory verification circuit according to claim 5, wherein the circuit structures of the memory cells belonging to different memory arrays are different; or,
the memory cells belonging to different memory arrays have the same circuit structure and different sizes.
7. The memory verification circuit of claim 5, further comprising a read circuit and a control circuit;
the reading circuit is used for reading the data stored in each storage unit;
the control circuit is used for providing read-write control signals for the column decoder and the reading circuit.
8. The memory verification circuit of claim 5, wherein the number of memory cells in each memory array is the same.
9. A memory verification method applied to the memory verification circuit according to any one of claims 1 to 8, comprising:
writing full verification data to the storage array;
single particles are incident to the storage array;
reading data stored in each storage unit;
determining a memory cell in which an error occurs based on the data written into and the data read out from each memory cell;
and acquiring the number of the memory units with errors in each memory unit according to the addresses corresponding to the memory units with errors.
10. The memory verification method of claim 9, wherein the verification data is 55AA hexadecimal data.
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| CN111813705A (en) * | 2020-06-28 | 2020-10-23 | 上海华虹宏力半导体制造有限公司 | Serial flash memory and address control method thereof |
| CN113470711A (en) * | 2020-03-30 | 2021-10-01 | 长鑫存储技术有限公司 | Memory block and memory |
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| CN110111833B (en) | 2021-07-13 |
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