CN110098821A - Flip-flop circuit and integrated circuit - Google Patents
Flip-flop circuit and integrated circuit Download PDFInfo
- Publication number
- CN110098821A CN110098821A CN201810097078.8A CN201810097078A CN110098821A CN 110098821 A CN110098821 A CN 110098821A CN 201810097078 A CN201810097078 A CN 201810097078A CN 110098821 A CN110098821 A CN 110098821A
- Authority
- CN
- China
- Prior art keywords
- output
- unit
- flip
- output end
- connect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318522—Test of Sequential circuits
- G01R31/318525—Test of flip-flops or latches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The embodiment of the present invention provides a kind of flip-flop circuit and integrated circuit, trigger includes: input logic assembled unit, flip-flop element, output logical combination unit and mode controlling unit, input logic assembled unit includes function signal input terminal, test signal input part and input terminal group, and input logic assembled unit is connect by output end group corresponding with input terminal group in input terminal group and mode controlling unit with mode controlling unit；Input logic assembled unit output function signal or test signal under the control of mode controlling unit；The output end of input logic assembled unit and the input terminal of flip-flop element connect；First output end of flip-flop element is connect with the first output unit of output logical combination unit；The second output terminal of flip-flop element is connect with the second output unit of output logical combination unit, and the first output end of flip-flop element and the phase of second output terminal are different.The performance of trigger is improved under the premise of guaranteeing that trigger has measurability.
Description
Technical field
The present embodiments relate to trigger technology field more particularly to a kind of flip-flop circuits and integrated circuit.
Background technique
Trigger is one of digital circuit timing storage unit, can be controlled by clock signal to trigger
System, clock signal rising edge or failing edge arrive when, trigger is triggered, output at this time with the change of input and
Change, in remaining time, the output of trigger continues to have.
In actual application, it in order to guarantee that trigger can work normally, needs to test trigger.And with
The raising of electronic circuit integrated level, circuit more sophisticated, for example, may include the timing such as many triggers in a circuit
Device, so that the test process to electronic circuit is more complicated.In the prior art, increase test electricity usually in trigger
Trigger is tested with realizing in road, and in the identical node output function result of trigger and test result.However,
When by identical node output function result and test result, the output of functional result and test result may mutual shadow
It rings, so that the load capacitance of fuction output is larger, and then reduces the speed of fuction output, so that the performance of trigger is poor.
Summary of the invention
The embodiment of the present invention provides a kind of flip-flop circuit and integrated circuit, in the premise for guaranteeing that trigger has measurability
The lower performance for improving trigger.
In a first aspect, the embodiment of the present invention provides a kind of flip-flop circuit, comprising: input logic assembled unit, trigger
Unit, output logical combination unit and mode controlling unit, wherein
The input logic assembled unit includes function signal input terminal, test signal input part and input terminal group, institute
State input logic assembled unit pass through it is corresponding with the input terminal group on the input terminal group and the mode controlling unit
Output end group is connect with the mode controlling unit；The input logic assembled unit is under the control of the mode controlling unit
Output function signal or test signal；The output end of the input logic assembled unit and the input terminal of the flip-flop element connect
It connects；
First output end of the flip-flop element is connect with the first output unit of the output logical combination unit, institute
The output end for stating the first output unit exports the corresponding test result of the test signal；
The second output terminal of the flip-flop element is connect with the second output unit of the output logical combination unit, institute
The output end for stating the second output unit exports the corresponding functional result of the function signal, the first output of the flip-flop element
It holds different with the phase of second output terminal.
In a kind of possible embodiment, the mode controlling unit includes the first output end and second output terminal, institute
State input logic assembled unit include first with door, second with door and or door, wherein
Described first with door include it is described test signal input part and the input terminal group in first input end, institute
The first output end stated in the output end group of the first input end and the mode controlling unit in input terminal group is connect；
Described second with door includes the second input terminal in the function signal input terminal and the input terminal group, institute
The second output terminal stated in the output end group of the second input terminal and the mode controlling unit in input terminal group is connect, the mould
First output end of the output end group of formula control unit and the opposite in phase of second output terminal output signal；
Described first connect with the output end of door with described or door first input end, described second with the output end of door with
Described or door the second input terminal connection；
Described or door output end is connect with the input terminal of the flip-flop element.
In alternatively possible embodiment, the first output unit of the output logical combination unit includes first anti-
Phase device, wherein
The input terminal of first phase inverter is connect with the first output end of the flip-flop element；
The output end of first phase inverter exports the test result.
In alternatively possible embodiment, it is described output logical combination unit the first output unit further include with it is non-
Door, wherein
The first input end of the NAND gate is connect with the first output end of the flip-flop element, and the of the NAND gate
Two input terminals are connect with the first output end of the mode controlling unit；
The output end of the NAND gate is connect with the input terminal of first phase inverter, the output end of first phase inverter
Export the test result.
In alternatively possible embodiment, the second output unit of the output logical combination unit includes second anti-
Phase device, wherein
The input terminal of second phase inverter is connect with the second output terminal of the flip-flop element；
The output end of second phase inverter exports the functional result.
In alternatively possible embodiment, the flip-flop element includes the first transmission gate, the second transmission gate, third
Transmission gate, the 4th transmission gate, third phase inverter, the 4th phase inverter and clock unit, wherein
The input terminal of first transmission gate is connect with the output end of the input logic assembled unit, first transmission
The control terminal of door is connect with the first output end of the clock unit；
The output end of first transmission gate is connect with the input terminal of the third phase inverter, the third phase inverter it is defeated
Enter end also to connect with the output end of second transmission gate；
The output end of the third phase inverter respectively with the input terminal of second transmission gate and the third transmission gate
Input terminal connection, the control terminal of second transmission gate are connect with the second output terminal of the clock unit, the third transmission
The control terminal of door is connect with the second output terminal of the clock unit, the first output end and second output terminal of the clock unit
The opposite in phase of output signal；
The output end of the third transmission gate respectively with the input terminal of second output unit and the 4th phase inverter
Input terminal connection, the input terminal of the 4th phase inverter also connect with the output end of the 4th transmission gate；
The output end of 4th phase inverter respectively with the input terminal and first output unit of the 4th transmission gate
Input terminal connection, the control terminal of the 4th transmission gate connect with the first output end of the clock unit；
The output end of 4th transmission gate is also connect with the input terminal of second output unit.
In alternatively possible embodiment, the first output end of the flip-flop element is the 4th phase inverter
Output end.
In alternatively possible embodiment, the second output terminal of the flip-flop element is the third transmission gate
The output end of output end or the 4th transmission gate.
In alternatively possible embodiment, first transmission gate, second transmission gate, the third transmission gate
It is complementary metal oxide semiconductor cmos transmission gate at least one transmission gate in the 4th transmission gate.
Second aspect, the embodiment of the present invention provide a kind of integrated circuit, including described in any item first touchings of first aspect
Send out device circuit, described in any item second flip-flop circuits of first aspect, feature path and scan chain, wherein
First output end of the output logical combination unit of first flip-flop circuit and the input terminal of the scan chain
The test signal input part of the input logic assembled unit of connection, the output end of the scan chain and second flip-flop circuit
Connection；
The second output terminal of the output logical combination unit of first flip-flop circuit and the input of the feature path
End connection, the output end of the feature path and the function signal of the input logic assembled unit of second flip-flop circuit are defeated
Enter end connection.
Flip-flop circuit and integrated circuit provided in an embodiment of the present invention, since input logic assembled unit includes function letter
Number input terminal and test signal input part, so that input logic assembled unit can receive function signal and test signal, mode
Control unit can control input logic assembled unit, so that input logic assembled unit output function signal or test
Signal, since the output end of input logic assembled unit and the input terminal of flip-flop element connect, it is thereby achieved that triggering
Device unit input function signal or test signal, so that flip-flop element has testability.And the first of flip-flop element is defeated
Outlet is used for transmission test result, and second output terminal is used for transmission functional result, due to the first output end and second output terminal
Phase is different, and therefore, the output of the first output end and second output terminal will not influence each other, so that test result and function
As a result output will not influence each other, avoid increase fuction output load capacitance, to avoid influence fuction output speed,
And then improve the performance of flip-flop circuit.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without any creative labor, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram one of flip-flop circuit provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram two of flip-flop circuit provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of integrated circuit provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is the structural schematic diagram one of flip-flop circuit provided in an embodiment of the present invention.Referring to Figure 1, comprising: input is patrolled
Collect assembled unit 11, flip-flop element 12, output logical combination unit 13 and mode controlling unit 14, wherein
Input logic assembled unit 11 includes function signal input terminal, test signal input part and input terminal group, input
Logical combination unit 11 passes through output end group corresponding with input terminal group and mode in input terminal group and mode controlling unit 14
Control unit 14 connects；Input logic assembled unit 11 output function signal or test letter under the control of mode controlling unit 14
Number；The output end of input logic assembled unit 11 is connect with the input terminal of flip-flop element 12.
First output end of flip-flop element 12 is connect with the first output unit of output logical combination unit 13, and first is defeated
The corresponding test result of output end output test signal of unit out.
The second output terminal of flip-flop element 12 is connect with the second output unit of output logical combination unit 13, and second is defeated
The corresponding functional result of output end output function signal of unit out, the first output end and second output terminal of flip-flop element 12
Phase it is different.
In the embodiment shown in fig. 1, the function signal input terminal of input logic assembled unit 11 is believed for receive capabilities
Number.The test signal input part of input logic assembled unit 11 is for receiving test signal.
Input logic assembled unit 11 passes through corresponding with input terminal group defeated in input terminal group and mode controlling unit 14
Outlet group is connect with mode controlling unit 14, and mode controlling unit 14 is exported to input logic assembled unit 11 and is controlled
Signal, to control the output of input logic assembled unit 11 so that the output of input logic assembled unit 11 be function signal or
Test signal.
For example, input logic assembled unit 11 can be made when the control signal that mode controlling unit 14 exports is 0
Output is function signal, when the control signal that mode controlling unit 14 exports is 1, can make input logic assembled unit 11
Output be test signal.
Since the output of input logic assembled unit 11 for function signal or tests signal, and input logic assembled unit 11
Output end connect with the input terminal of flip-flop element 12, therefore, to the input signal of flip-flop element 12 be function signal or
Person tests signal, in this way, flip-flop element 12 can be made to have testability.
Flip-flop element 12 includes the first output end and second output terminal.Exporting logical combination unit 13 includes the first output
First output end of unit and the second output unit, flip-flop element 12 is connect with the first output unit, flip-flop element 12
Second output terminal is connect with the second output unit.And since the first output unit is for outputing test result, the second output unit
For output function as a result, therefore, the first output end of flip-flop element 12 is used for transmission test result, and second output terminal is used for
Transfer function result.First output end is different from the phase of second output terminal, therefore, the first output end and second output terminal it is defeated
It will not influence each other out, that is, the output of test result and functional result will not influence each other.
Flip-flop circuit provided in an embodiment of the present invention, due to input logic assembled unit include function signal input terminal and
Signal input part is tested, so that input logic assembled unit can receive function signal and test signal.Mode controlling unit can
To control input logic assembled unit, so that input logic assembled unit output function signal or test signal.Due to
The output end of input logic assembled unit and the input terminal of flip-flop element connect, it is thereby achieved that defeated to flip-flop element
Enter function signal or test signal, so that flip-flop element has testability.And the first output end of flip-flop element is used for
Test result is transmitted, second output terminal is used for transmission functional result, since the first output end is different from the phase of second output terminal,
Therefore, the output of the first output end and second output terminal will not influence each other, so that test result and functional result is defeated
It will not influence each other out, avoid the load capacitance for increasing fuction output, to avoid the speed for influencing fuction output, and then improve
The performance of flip-flop circuit.
On the basis of embodiment shown in Fig. 1, in the following, by embodiment shown in Fig. 2, to testability flip-flop circuit
It is further elaborated.
Fig. 2 is the structural schematic diagram two of flip-flop circuit provided in an embodiment of the present invention.
Fig. 2 is referred to, mode controlling unit 14 includes the first output end and second output terminal, input logic assembled unit 11
Including first with door AND1, second and door AND2 and or door OR1, wherein first with door AND1 include test signal input
First input end in end and input terminal group, the output end of first input end and mode controlling unit 14 in input terminal group
The first output end connection in group.Second and door AND2 includes the second input in function signal input terminal and input terminal group
It holds, the second input terminal in input terminal group is connect with the second output terminal in the output end group of mode controlling unit 14, mode control
First output end of the output end group of unit 14 processed and the opposite in phase of second output terminal output signal.First is defeated with door AND1
Outlet with or the first input end of door OR1 connect, second with the output end of door AND2 with or the second input terminal of door OR1 connect.
Or the output end of door OR1 is connect with the input terminal of flip-flop element 12.
Optionally, the control letter of the first output end in the output end group of mode controlling unit 14 and second output terminal output
Number opposite in phase.Fig. 2 is referred to, the control signal of the first output end output of mode controlling unit 14 is TE, scheme control
The control signal of the second output terminal output of unit 14 is TEN.For example, the first output end of mode controlling unit 14 and second defeated
Phase inverter is provided between outlet, in this manner it is achieved that the first output end and second output terminal of mode controlling unit 14 export
Control signal opposite in phase.
For example, when the 0 of the signal that the first output end of mode controlling unit 14 exports, then the of mode controlling unit 14
The signal of two output ends output is 1.When the 1 of the signal that the first output end of mode controlling unit 14 exports, then scheme control
The signal of the second output terminal output of unit 14 is 0.
In actual application, it can be set according to actual needs the output of mode controlling unit 14, it specifically can be as
Under:
When needing to test trigger, the output of the first output end of mode controlling unit 14 can be set to
1, correspondingly, the output of the second output terminal of mode controlling unit 14 is 0.In that case, first and door AND1 is to mode
The output (1) of first output end of control unit 14 and test signal TI are carried out and are handled, so that the output of first and door AND1
To test signal TI, and test signal TI is transferred to or door OR1.Second is defeated to the second of mode controlling unit 14 with door AND2
The output (0) of outlet and function signal D are carried out and processing, so that second and the output of door AND2 are 0, and 0 is transferred to or door
OR1.Or door OR1 is carried out or is handled with the output (test signal TI) of door AND1 and the output (0) of second and door AND2 to first,
So that or door OR1 output be test signal TI.From the foregoing, it will be observed that passing through control model when needing to test trigger
The control of control unit 14, may be implemented by or door OR1 output test signal TI.
It, can be by the output of the first output end of mode controlling unit 14 when needing to carry out function operation by trigger
It is set as 0, correspondingly, the output of the second output terminal of mode controlling unit 14 is 1.In that case, first and door AND1
Output (0) and test signal TI to the first output end of mode controlling unit 14 are carried out and are handled, so that first and door AND1
Output be 0, and 0 is transferred to or door OR1.Second with output of the door AND2 to the second output terminal of mode controlling unit 14
(1) and function signal D is carried out and processing, so that the output of second and door AND2 is function signal D, and function signal D is transmitted
It gives or door OR1.Or door OR1 to first with the output (0) of door AND1 and second with output (function signal D) progress of door AND2 or
Processing so that or door OR1 output be function signal D.From the foregoing, it will be observed that leading to when needing to carry out function operation by trigger
The control for crossing control model control unit 14, may be implemented by or door OR1 output function signal D.
Fig. 2 is referred to, flip-flop element 12 includes the first transmission gate T1, the second transmission gate T2, third transmission gate T3, the 4th
Transmission gate T4, third phase inverter I3, the 4th phase inverter I4 and clock unit C.Wherein, the input terminal of the first transmission gate T1 and input
The output end of logical combination unit 11 connects, and the control terminal of the first transmission gate T1 is connect with the first output end of clock unit C, the
The output end of one transmission gate T1 is connect with the input terminal of third phase inverter I3.The input terminal of third reverser I3 is also transmitted with second
The output end connection of door T2.The output end of third phase inverter I3 respectively with the input terminal of the second transmission gate T2 and third transmission gate T3
Input terminal connection, the control terminal of the second transmission gate T2 connect with the second output terminal of clock unit C, the control of third transmission gate T3
End processed is connect with the second output terminal of clock unit C, the first output end of clock unit C and the phase of second output terminal output signal
Position is opposite.The input with the input terminal and the 4th phase inverter I4 of the second output unit 132 respectively of the output end of third transmission gate T3
End connection, the input terminal of the 4th phase inverter I4 are also connect with the output end of the 4th transmission gate T4.The output end of 4th phase inverter I4
It is connect respectively with the input terminal of the input terminal of the 4th transmission gate T4 and the first output unit 131, the control terminal of the 4th transmission gate T4
It is connect with the first output end of clock unit C, the output end of the 4th transmission gate T4 also connects with the input terminal of the second output unit 132
It connects.
Optionally, the outside of flip-flop element 12 can also be arranged in clock unit C.
In actual application, the usual cyclically-varying of clock signal that clock unit C is issued, for example, clock unit C
The clock signal G that can be issued can be square-wave signal, in the clock signal that clock signal G is obtained after a phase inverter
The opposite in phase of GN and clock signal G, clock signal GN is using the clock signal GI and clock obtained after a phase inverter
The phase signal of signal GN.That is, the opposite in phase of clock signal G and clock signal GN, clock signal GN and clock signal GI
Opposite in phase, clock signal G are identical with the phase of clock signal GI.
When clock signal G is low level, clock signal GI is low level, and the first transmission gate T1 and the 4th transmission gate T4 are led
It is logical.Clock signal GN is high level, and the second transmission gate T2 and third transmission gate T3 are disconnected.At this point, the signal of input passes through first
After transmission gate T1 and third phase inverter I3, the third transmission gate T3 being disconnected is obstructed.
When clock signal G is high level, clock signal GN is low level, and the second transmission gate T2 and third transmission gate T3 are led
It is logical.Clock signal GI is high level, and the first transmission gate T1 and the 4th transmission gate T4 are disconnected.At this point, third phase inverter I3 and second
Transmission gate T2 forms a level holding circuit keeper1, the data that the first transmission gate T1 of storage is written before disconnecting, and due to the
One transmission gate T1 is disconnected, and the input of flip-flop element is obstructed by the first transmission gate T1, new input can not be received, so that being stored in
The data of keeper1 are exported by third transmission gate T3.
Optionally, the first output end of flip-flop element 12 is the output end of the 4th phase inverter I4.Flip-flop element 12
Second output terminal is the output end of third transmission gate T3 or the output end of the 4th transmission gate T4.For example, when third transmission gate T3 is led
When logical, the 4th transmission gate T4 is disconnected, then the second output terminal of flip-flop element 12 is the output end of third transmission gate T3.Work as third
When transmission gate T3 is disconnected, the 4th transmission gate T4 is connected, then the second output terminal of flip-flop element 12 is the defeated of the 4th transmission gate T4
Outlet.Due to the opposite in phase of the output end of the output end and the 4th transmission gate T4 of the 4th phase inverter I4, flip-flop element
12 the first output end and the opposite in phase of second output terminal.First output end of flip-flop element 12 is used for transmission test result
TQ, the second output terminal of flip-flop element are used for transmission functional result Q, due to the first output end of flip-flop element 12 and second
Output end is different, and therefore, flip-flop element 12 is mutually independent of each other to the transmission between test result TQ and functional result Q.
It should be noted that Fig. 2 only illustrates flip-flop element 12 in exemplary fashion, not to flip-flop element 12
It limits, in actual application, can be set according to actual needs flip-flop element 12, flip-flop element 12 can be substantially
Rest-set flip-flop, synchronous rs flip-flop, master-slave flip-flop, edge-triggered device etc., the embodiment of the present invention does not make flip-flop element 12
It is specific to limit.
Fig. 2 is referred to, the first output unit of output logical combination unit 13 includes the first phase inverter I1, wherein first
The input terminal of phase inverter I1 is connect with the first output end of flip-flop element 12；The output end output test knot of first phase inverter I1
Fruit TQ.The second output unit for exporting logical combination unit 13 includes the second phase inverter I2, wherein the input of the second phase inverter I2
End is connect with the second output terminal of flip-flop element 12；The output end output function result Q of second phase inverter I2.
Further, the first output unit 131 for exporting logical combination unit 13 further includes NAND gate NAND1.Wherein, with
The first input end of NOT gate NAND1 is connect with the first output end of flip-flop element 12, the second input terminal of NAND gate NAND1 with
First output end of mode controlling unit 14 connects.The output end of NAND gate NAND1 is connect with the input terminal of the first phase inverter I1,
The output end of first phase inverter I1 outputs test result TQ.
When the first output unit includes NAND gate NAND1, due to the second input terminal and scheme control of NAND gate NAND1
First output end of unit 14 connects, therefore, what the control signal and first that NAND gate NAND1 is received were received with door AND1
It is identical to control signal.Therefore, in the functional mode, the control signal that NAND gate NAND1 is received is 0, is passed through in control signal 0
Output after the processing of NAND gate NAND1 and phase inverter is 0.That is, under functional mode, the output of the first output unit is always
Zero.Incorporated by reference to Fig. 3, when the output of the first output unit is always zero, scan path then stops overturning, so that scan path is not
Corresponding dynamic power consumption is generated, and then saves the total power consumption of circuit.
In the embodiment shown in Figure 2, by embedding selection circuit and setting circuit inside circuit, with external call mark
Quasi- unit is completed same function and is compared, and can be shared in layout design by grid or drain, save entire area.Further
, usual frequency requirement is lower under test pattern, and settling time requires relatively good satisfaction, in the increased set in sweep test port
And inverted logic circuit can play the repair of retention time Hold, reduce to need to be added outside flip-flop element 12 and repair Hold
Buffer quantity.
In the following, the course of work of flip-flop circuit shown in Fig. 2 embodiment is described in detail.
In test mode, the control signal of the first output end output of mode controlling unit 14 is 1, mode controlling unit
The control signal of 14 second output terminal output is 0.It is received with door AND1 by the first input end in input terminal group first
Test is received to the control signal 1 of the first output end output of mode controlling unit 14 and by testing signal input part
After signal TI, first carries out with processing control signal 1 and test signal TI with door AND1, and obtained output is test signal
TI, and test signal TI is sent to or door OR1.It is received with door AND2 by the second input terminal in input terminal group second
The control signal 0 and function letter is received by function signal input terminal that the second output terminal of mode controlling unit 14 exports
After number D, second is carried out control signal 0 and function signal D with door AND2 and processing, obtained output are 0, and 0 sent
It gives or door OR1.Or door OR1 receive test signal TI and 0 after, to test signal TI and 0 carry out or processing, tested
Signal TI, and the first transmission gate T1 of flip-flop element 12 is sent to by signal TI is tested.
After the first transmission gate T1 receives test signal TI, when clock signal G is low level, clock signal GI is
Low level, the first transmission gate T1 and the 4th transmission gate T4 conducting.Clock signal GN is high level, and the second transmission gate T2 and third pass
Defeated door T3 is disconnected.At this point, the signal newly inputted is passed by the third after the first transmission gate T1 and third phase inverter I3, being disconnected
Defeated door T3 barrier.
When clock signal G is turned into high level, the first transmission gate T1 and the 4th transmission gate T4 are disconnected, the second transmission gate T2
It is connected with third transmission gate T3.At this point, third phase inverter I3 and the second transmission gate T2 forms a level holding circuit
Keeper1, the data that the first transmission gate T1 of storage is written before disconnecting, and since the first transmission gate T1 is disconnected, flip-flop element
Input is obstructed by the first transmission gate T1, can not receive new input.Be stored in the data of keeper1 by third transmission gate T3 and
4th phase inverter is exported to the NOT gate NAND1 of the first output unit 131, since the NAND gate NAND1 in the first output unit connects
The control signal received is 1, and therefore, the first output unit 131, which is equivalent to, carries out twice after reverse phase test signal TI, by the
The first phase inverter I1 in one output unit outputs test result TQ.Meanwhile the data for being stored in keeper1 are transmitted by third
Door T3 exports the second phase inverter T2 into the second output unit 132, and passes through the second phase inverter T2 output function result Q.Its
In, test result TQ is identical with functional result Q.
When clock G is turned into low level again, the first transmission gate T1 and the 4th transmission gate T4 conducting, the second transmission gate T2
It is disconnected with third transmission gate T3, the new data of input is obstructed by T3, and the level that the 4th transmission gate T4 and the 4th phase inverter are formed
Holding circuit keeper2 can continue to output test result to the first output unit TQ, to 132 output function of the second output unit
As a result Q.Wherein, test result TQ is identical with functional result Q.
In the functional mode, the control signal of the first output end output of mode controlling unit 14 is 0, mode controlling unit
The control signal of 14 second output terminal output is 1.It is received with door AND1 by the first input end in input terminal group first
Test is received to the control signal 0 of the first output end output of mode controlling unit 14 and by testing signal input part
After signal TI, first with door AND1 is to control signal 0 and test signal TI is carried out and processing, obtained output is 0, and by 0
It is sent to or door OR1.Mode controlling unit 14 is received by the second input terminal in input terminal group with door AND2 second
The control signal 1 of second output terminal output and after receiving function signal D by function signal input terminal, second and door
AND2 is carried out to control signal 1 and function signal D and processing, and obtained output is function signal D, and function signal D is sent
It gives or door OR1.Or after door OR1 receives function signal D and 0, function signal D and 0 is carried out or processing, obtains function letter
Number D, and function signal D is sent to the first transmission gate T1 of flip-flop element 12.
After the first transmission gate T1 receives function signal D, when clock signal G is low level, clock signal GI is
Low level, the first transmission gate T1 and the 4th transmission gate T4 conducting.Clock signal GN is high level, and the second transmission gate T2 and third pass
Defeated door T3 is disconnected.At this point, the signal newly inputted is passed by the third after the first transmission gate T1 and third phase inverter I3, being disconnected
Defeated door T3 barrier.
When clock signal G is turned into high level, the first transmission gate T1 and the 4th transmission gate T4 are disconnected, the second transmission gate T2
It is connected with third transmission gate T3.At this point, third phase inverter I3 and the second transmission gate T2 forms a level holding circuit
Keeper1, the data that the first transmission gate T1 of storage is written before disconnecting, and since the first transmission gate T1 is disconnected, flip-flop element
Input is obstructed by the first transmission gate T1, can not receive new input.Be stored in the data of keeper1 by third transmission gate T3 and
4th phase inverter is exported to the NOT gate NAND1 of the first output unit 131, since the NAND gate NAND1 in the first output unit connects
The control signal received is 0, and the output after NAND gate NAND1 is 1, is using the output after the first phase inverter I1
0, that is, by the first phase inverter I1 output 0 in the first output unit.Meanwhile the data for being stored in keeper1 are transmitted by third
Door T3 exports the second phase inverter T2 into the second output unit 132, and passes through the second phase inverter T2 output function result Q.
When clock G is turned into low level again, the first transmission gate T1 and the 4th transmission gate T4 conducting, the second transmission gate T2
It is disconnected with third transmission gate T3, the new data of input is obstructed by T3, and the level that the 4th transmission gate T4 and the 4th phase inverter are formed
Holding circuit keeper2 can continue to 132 output function result Q of the second output unit.
Fig. 3 is the structural schematic diagram of integrated circuit provided in an embodiment of the present invention.Refer to Fig. 3, including the first trigger
Circuit 31, the second flip-flop circuit 32, feature path 33 and scan chain, wherein
First flip-flop circuit 31 and the second flip-flop circuit 32 are trigger shown in above-mentioned Fig. 1-Fig. 2 any embodiment
Circuit.
The first output end of output logical combination unit 13 and the input terminal of scan chain of first flip-flop circuit 31 connect,
The output end of scan chain is connect with the test signal input part of the input logic assembled unit 11 of the second flip-flop circuit 32.
The second output terminal of output logical combination unit 13 and the input terminal of feature path of first flip-flop circuit 31 connect
It connects, the function signal input terminal of the input logic assembled unit 11 of the output end of feature path and the second flip-flop circuit 32 connects
It connects.
Optionally, feature path is made of multiple functional unit functions, scan chain multiple phase inverters.
Optionally, the first flip-flop circuit 31 is identical with the structure of the second hair device circuit 32.For any one trigger
Circuit, D is function signal input terminal, TI is test signal input part, and TE is control signal input, and G is clock signal input
End, Q are functional result output, and TQ is test result output.
Finally, it should be noted that the above various embodiments is only to illustrate the technical solution of the embodiment of the present invention, rather than to it
Limitation；Although the embodiment of the present invention is described in detail referring to foregoing embodiments, those skilled in the art
It is understood that it is still possible to modify the technical solutions described in the foregoing embodiments, either to part of or
All technical features are equivalently replaced；And these are modified or replaceed, it does not separate the essence of the corresponding technical solution this hair
The range of bright example scheme.
Claims (10)
1. a kind of flip-flop circuit characterized by comprising input logic assembled unit, flip-flop element, output logical combination
Unit and mode controlling unit, wherein
The input logic assembled unit includes function signal input terminal, tests signal input part and input terminal group, described defeated
Enter logical combination unit and passes through output corresponding with the input terminal group on the input terminal group and the mode controlling unit
End group is connect with the mode controlling unit；The input logic assembled unit exports under the control of the mode controlling unit
Function signal or test signal；The output end of the input logic assembled unit is connect with the input terminal of the flip-flop element；
First output end of the flip-flop element is connect with the first output unit of the output logical combination unit, and described the
The output end of one output unit exports the corresponding test result of the test signal；
The second output terminal of the flip-flop element is connect with the second output unit of the output logical combination unit, and described the
The output ends of two output units exports the corresponding functional result of the function signal, the first output end of the flip-flop element and
The phase of second output terminal is different.
2. flip-flop circuit according to claim 1, which is characterized in that the mode controlling unit includes the first output end
And second output terminal, the input logic assembled unit include first with door, second with door and or door, wherein
Described first with door include it is described test signal input part and the input terminal group in first input end, it is described defeated
The first output end entered in the output end group of the first input end and the mode controlling unit in the group of end is connect；
Described second with door includes the second input terminal in the function signal input terminal and the input terminal group, described defeated
The second output terminal entered in the output end group of the second input terminal and the mode controlling unit in the group of end is connect, the mode control
First output end of the output end group of unit processed and the opposite in phase of second output terminal output signal；
Described first connect with the output end of door with described or door first input end, described second with the output end of door with it is described
Or the second input terminal connection of door；
Described or door output end is connect with the input terminal of the flip-flop element.
3. flip-flop circuit according to claim 1 or 2, which is characterized in that the first of the output logical combination unit
Output unit includes the first phase inverter, wherein
The input terminal of first phase inverter is connect with the first output end of the flip-flop element；
The output end of first phase inverter exports the test result.
4. flip-flop circuit according to claim 3, which is characterized in that the first output of the output logical combination unit
Unit further includes NAND gate, wherein
The first input end of the NAND gate is connect with the first output end of the flip-flop element, and the second of the NAND gate is defeated
Enter end to connect with the first output end of the mode controlling unit；
The output end of the NAND gate is connect with the input terminal of first phase inverter, the output end output of first phase inverter
The test result.
5. flip-flop circuit according to claim 1 or 2, which is characterized in that the second of the output logical combination unit
Output unit includes the second phase inverter, wherein
The input terminal of second phase inverter is connect with the second output terminal of the flip-flop element；
The output end of second phase inverter exports the functional result.
6. flip-flop circuit according to claim 1 or 2, which is characterized in that the flip-flop element includes the first transmission
Door, the second transmission gate, third transmission gate, the 4th transmission gate, third phase inverter, the 4th phase inverter and clock unit, wherein
The input terminal of first transmission gate is connect with the output end of the input logic assembled unit, first transmission gate
Control terminal is connect with the first output end of the clock unit；
The output end of first transmission gate is connect with the input terminal of the third phase inverter, the input terminal of the third phase inverter
Also it is connect with the output end of second transmission gate；
The input with the input terminal of second transmission gate and the third transmission gate respectively of the output end of the third phase inverter
End connection, the control terminal of second transmission gate are connect with the second output terminal of the clock unit, the third transmission gate
Control terminal is connect with the second output terminal of the clock unit, the first output end and the second output terminal output of the clock unit
The opposite in phase of signal；
The output end of the third transmission gate is defeated with the input terminal of second output unit and the 4th phase inverter respectively
Enter end connection, the input terminal of the 4th phase inverter is also connect with the output end of the 4th transmission gate；
The output end of 4th phase inverter is defeated with the input terminal of the 4th transmission gate and first output unit respectively
Enter end connection, the control terminal of the 4th transmission gate is connect with the first output end of the clock unit；
The output end of 4th transmission gate is also connect with the input terminal of second output unit.
7. flip-flop circuit according to claim 6, which is characterized in that the first output end of the flip-flop element is institute
State the output end of the 4th phase inverter.
8. flip-flop circuit according to claim 6, which is characterized in that the second output terminal of the flip-flop element is institute
State the output end of third transmission gate or the output end of the 4th transmission gate.
9. flip-flop circuit according to claim 6, which is characterized in that first transmission gate, second transmission gate,
At least one transmission gate in the third transmission gate and the 4th transmission gate is complementary metal oxide semiconductor CMOS biography
Defeated door.
10. a kind of integrated circuit, which is characterized in that including described in any item first flip-flop circuits of claim 1-9, right
It is required that described in any item second flip-flop circuits of 1-9, feature path and scan chain, wherein
First output end of the output logical combination unit of first flip-flop circuit is connect with the input terminal of the scan chain,
The output end of the scan chain is connect with the test signal input part of the input logic assembled unit of second flip-flop circuit；
The second output terminal of output logical combination unit and the input terminal of the feature path of first flip-flop circuit connect
It connects, the function signal input terminal of the input logic assembled unit of the output end of the feature path and second flip-flop circuit
Connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810097078.8A CN110098821B (en) | 2018-01-31 | 2018-01-31 | Flip-flop circuit and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810097078.8A CN110098821B (en) | 2018-01-31 | 2018-01-31 | Flip-flop circuit and integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110098821A true CN110098821A (en) | 2019-08-06 |
| CN110098821B CN110098821B (en) | 2023-01-24 |
Family
ID=67442904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810097078.8A Active CN110098821B (en) | 2018-01-31 | 2018-01-31 | Flip-flop circuit and integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110098821B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580278A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Optimization method and optimization device for logic circuit and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070052466A1 (en) * | 2005-09-02 | 2007-03-08 | Kim Oak-Ha | Flip-flop with improved operating speed |
| CN101499787A (en) * | 2008-02-02 | 2009-08-05 | 华润矽威科技（上海）有限公司 | Oscillator circuit having frequency jitter characteristic |
| CN104767516A (en) * | 2014-01-06 | 2015-07-08 | 上海华虹集成电路有限责任公司 | Synchronous circuit for asynchronous signals |
-
2018
- 2018-01-31 CN CN201810097078.8A patent/CN110098821B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070052466A1 (en) * | 2005-09-02 | 2007-03-08 | Kim Oak-Ha | Flip-flop with improved operating speed |
| CN101499787A (en) * | 2008-02-02 | 2009-08-05 | 华润矽威科技（上海）有限公司 | Oscillator circuit having frequency jitter characteristic |
| CN104767516A (en) * | 2014-01-06 | 2015-07-08 | 上海华虹集成电路有限责任公司 | Synchronous circuit for asynchronous signals |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580278A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Optimization method and optimization device for logic circuit and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110098821B (en) | 2023-01-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112805577B (en) | Chip, chip testing method and electronic equipment | |
| US9222979B2 (en) | On-chip controller and a system-on-chip | |
| US20130335128A1 (en) | Sequential latching device with elements to increase hold times on the diagnostic data path | |
| US11680981B2 (en) | Test access port with address and command capability | |
| JP3057814B2 (en) | Semiconductor integrated circuit | |
| CN110007217A (en) | A kind of low-power consumption boundary scanning test method | |
| CN111624478B (en) | Clock signal control circuit and equipment | |
| US5471152A (en) | Storage element for delay testing | |
| CN105247377A (en) | Circuit and layout techniques for flop tray area and power optimization | |
| CN110098821A (en) | Flip-flop circuit and integrated circuit | |
| CN107565936B (en) | Logic implementation device of input clock stabilizing circuit | |
| CN107565951A (en) | Multimode signal generating circuit | |
| US6789219B2 (en) | Arrangement and method of testing an integrated circuit | |
| US6448835B1 (en) | High-speed leaf splitter for clock gating | |
| CN110098829A (en) | Latch circuit and integrated circuit | |
| CN103391072B (en) | Be used for detect clock pulse shake testing circuit | |
| CN116203406A (en) | Scan register, operation method thereof, scan chain and chip | |
| CN116760403A (en) | High-speed D trigger circuit and high-speed D trigger chip | |
| CN115144740A (en) | Power-on latch circuit, power-on latch device and power-on latch method | |
| KR101123551B1 (en) | Circuit for measuring interval of events | |
| JPH0484783A (en) | Test method for semiconductor integrated circuit | |
| JPH05209934A (en) | Boundary scan cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Applicant after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Applicant before: LOONGSON TECHNOLOGY Corp.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |