CN110098165A - Bonding pad structure, semiconductor chip and its manufacturing method using the bonding pad structure - Google Patents
Bonding pad structure, semiconductor chip and its manufacturing method using the bonding pad structure Download PDFInfo
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- CN110098165A CN110098165A CN201810249228.2A CN201810249228A CN110098165A CN 110098165 A CN110098165 A CN 110098165A CN 201810249228 A CN201810249228 A CN 201810249228A CN 110098165 A CN110098165 A CN 110098165A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000010276 construction Methods 0.000 claims description 11
- 239000003989 dielectric material Substances 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000005253 cladding Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000010931 gold Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000004064 dysfunction Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/05076—Plural internal layers being mutually engaged together, e.g. through inserts
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention discloses a kind of bonding pad structure, semiconductor chip and its manufacturing method using the bonding pad structure.Bonding pad structure is formed on three-five substrate.Bonding pad structure includes the first conductive layer, dielectric layer, the second conductive layer and circuit.Dielectric layer is formed on the first conductive layer and has through hole, and through hole exposes the first conductive layer.Second conductive layer includes riveting part and connection pad portion, and riveting part fills up through hole and is connected to the first conductive layer, and connection pad portion is formed in dielectric layer.
Description
Technical field
The present invention relates to a kind of bonding pad structure, using the semiconductor chip and its manufacturing method of the bonding pad structure, and especially
Relate to a kind of bonding pad structure with circuit, semiconductor chip and its manufacturing method using it.
Background technique
Since the competitiveness of electronic product is strong, the speed of making a reduction of product is fast, therefore effectively designs the integrated of low cost
Circuit (Integrated Circuit) chip becomes a kind of necessity, in order to reduce the cost of IC chip, by part
Circuit is put into the way of the lower section of connection pad (PAD), and integrated circuit die size can be reduced by becoming one kind, and then reduce cost
Mode, circuit will not be put into below connection pad by the IC chip of traditional three-five technique, using three-five as substrate process
IC chip, connection pad generally comprise dielectric layer and metal layer, and wherein metal layer is formed on the dielectric layer.In the mistake of routing
Cheng Zhong, the pressure for being applied to metal layer are easy to damage metal layer by pressure or the dielectric layer of lower section are crushed, in addition with below dielectric layer
Circuit structure short circuit so that the dysfunction of integrated circuit, and the dielectric layer material as used by the three-five technique of part with
The associativity of metal layer is bad, is easy to remove metal layer into (pad peeling) from dielectric layer during routing.Cause
This, needs to propose a kind of scheme that can improve foregoing problems.
Summary of the invention
Therefore, it is an object of the invention to propose a kind of bonding pad structure, using the bonding pad structure semiconductor chip and its
Manufacturing method can improve aforementioned problem of the prior art.
An embodiment according to the present invention, proposes a kind of bonding pad structure.Bonding pad structure is formed on three-five substrate.It connects
Mat structure includes one first conductive layer, one first dielectric layer, one second conductive layer and one first circuit.First dielectric layer is formed in
On first conductive layer and at least with first through hole, the first through hole the first conductive layer of exposing.Second conductive layer includes
At least one riveting part and one first connection pad portion, riveting part fills up the first through hole and is connected to the first conductive layer, and first connects
Pad portion is formed in the first dielectric layer.
According to another embodiment of the present invention, a kind of semiconductor chip is proposed.Semiconductor chip includes a three-five substrate
An and bonding pad structure.Bonding pad structure is formed on three-five substrate.Bonding pad structure includes one first conductive layer, one first dielectric
Layer, one second conductive layer and one first circuit.First dielectric layer is formed on the first conductive layer and at least has one first and passes through
Perforation, the first through hole expose the first conductive layer.Second conductive layer includes at least one riveting part and one first connection pad portion, riveted
Portion fills up the first through hole and is connected to the first conductive layer, and the first connection pad portion is formed in the first dielectric layer.
According to another embodiment of the present invention, a kind of manufacturing method of bonding pad structure is proposed.Manufacturing method includes following step
Suddenly.One first circuit is on a three-five substrate；One first conductive layer is formed on three-five substrate；Form one first dielectric material
Material the first conductive layer of covering and the first circuit；It forms at least one first through hole and runs through the first dielectric material, to form one first
Dielectric layer, the first through hole expose the first conductive layer；And one second conductive layer is formed on the first dielectric layer, second is conductive
Layer includes at least one riveting part and one first connection pad portion, and riveting part fills up the first through hole and is connected to the first conductive layer, and
First connection pad portion is formed in the first dielectric layer.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Figure 1A is painted the top view of the semiconductor chip according to one embodiment of the invention；
Figure 1B is painted cross-sectional view of the semiconductor chip along direction 1B-1B ' of Figure 1A；
Fig. 2A is painted the top view of the semiconductor chip according to another embodiment of the present invention；
Fig. 2 B is painted cross-sectional view of the semiconductor chip along direction 2B-2B ' of Fig. 2A；
Fig. 3 is painted the top view of the semiconductor chip according to another embodiment of the present invention；
Fig. 4 is painted the cross-sectional view of the semiconductor chip according to another embodiment of the present invention；
Fig. 5 is painted the cross-sectional view of the semiconductor chip according to another embodiment of the present invention；
Fig. 6 A~6D is painted the process drawing of the bonding pad structure of Figure 1B.
Wherein, appended drawing reference
100,200,300,400,500: semiconductor chip
110: three-five substrate
110u: upper surface
120,220,320,420,520: bonding pad structure
121: the first conductive layers
122: the first dielectric layers
122 ': the first dielectric material
122s: lateral surface
122a: the first through hole
123: the second conductive layers
124: the first circuits
1231: riveting part
1231s: outer peripheral surface
1232: the first connection pad portions
130: articulamentum
140: second circuit
199: interface area
424: the second dielectric layers
424a: the second through hole
425: third conductive layer
4251: filling portion
4252: the second connection pad portions
R1: riveted construction
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
Figure 1A is painted the top view of the semiconductor chip 100 according to one embodiment of the invention, and Figure 1B is painted the half of Figure 1A
Cross-sectional view of the conductor chip 100 along direction 1B-1B '.
Semiconductor chip 100 includes three-five substrate 110, at least a bonding pad structure 120, articulamentum 130 and second circuit
140.Three-five substrate 110 includes three-five material.Three-five material, which refers to, to be made of the three races of periodic table with group-v element
Compound, such as GaAs (GaAs), indium phosphide (InP), gallium nitride (GaN), InGaAsP (InGaAs) and aluminum gallium arsenide
(InAlAs) etc..
Bonding pad structure 120 is formed on the upper surface 110u of three-five substrate 110.Bonding pad structure 120 includes first conductive
The 121, first dielectric layer 122 of layer, the second conductive layer 123 and the first circuit 124.First circuit 124 can be fully located at connection pad knot
Within structure 120, so that bonding pad structure 120 becomes CUP (Circuit Under Pad) structure.In another embodiment,
One circuit 124 can also be not limited within bonding pad structure 120.For example, the first circuit 124 can partially be located at bonding pad structure
Within 120, and another part of the first circuit 124 is located at except bonding pad structure 120, so that bonding pad structure 120 is tied as CUP
Structure.
Due to using CUP structure, a part of circuit in integrated circuit is placed into below PAD this structure, therefore can be with
Reduce the size of semiconductor chip 100.In addition, the material of the first conductive layer 121 is, for example, the compound of golden (Au) or gold.
First circuit 124 be, for example, Anti-static circuit (Electrical Static Discharge (ESD) circuit),
Active circuits or passive circuit.Alternatively, all first circuits 124 can be integrated into an active circuits or a passive circuit.
As shown in Figure 1B, the side of the first circuit 124 is coated completely.So in another embodiment, the first circuit 124 can
The lateral surface 122s for extending to the first dielectric layer 122, without being coated by the first conductive layer 121.Under this design, the first circuit
124 expose from lateral surface 122s.
First dielectric layer 122 is formed on the first conductive layer 121 and has at least one first through hole 122a, these the
Pass through aperture 122a exposes the first conductive layer 121.In addition, the material of the first dielectric layer 122 can be silicon nitride (SiN), polyamides
Imines (Polymide) or polybenzoxazoles (Polybenzoxazole, PBO), it is sub- that the first dielectric layer can also be silicon nitride, polyamides
The dielectric materials such as amine and polybenzoxazoles are arbitrarily overlapped and are formed in mixed between the first conductive layer 121 and the second conductive layer 123
Close dielectric layer.
Second conductive layer 123 includes several riveting parts 1231 and the first connection pad portion 1232, and correspondence is filled up in each riveting part 1231
The first through hole 122a and be connected to the first conductive layer 121.First connection pad portion 1232 connection riveting part 1231 and it is formed in the
One dielectric layer, 122 top.Riveting part 1231 is, for example, to be formed in same technique with the first connection pad portion 1232.In addition, second leads
The material of electric layer 123 is, for example, the compound of gold or gold.In another embodiment, the quantity of riveting part 1231 and first run through
The quantity of hole 122a distinguishes only one.
In the present embodiment, riveting part 1231 constitutes a riveting with corresponding first through hole 122a and the first conductive layer 121
Close structure R1.Riveted construction R1 can enhance the compressive resistance of bonding pad structure 120, so that at routing technique (wire-bonding)
In, the pressure that wiring tool head is applied on the second conductive layer 123 is not easy to damage by pressure on the metal of the second conductive layer 123, or will
First dielectric layer 122 crushes, and can avoid the first connection pad portion 1232 in this way because the first dielectric layer 122 collapses under pressure and touches first
Circuit 124 and it is short-circuit.
In addition, as shown in Figure 1B, the outer diameter (or internal diameter of the first through hole 122a) of the riveting part 1231 of riveted construction R1
Can be depending on the area of the first conductive layer 121 of lower section, when the area of the first conductive layer 121 is bigger, the outer diameter of riveting part 1231
Can be bigger, the right embodiment of the present invention is not limited.In addition, the around the area view of the first conductive layer 121 below riveted construction R1
Depending on the distribution of one circuit 124.For example, it is relatively close to work as the distance between multiple first circuits 124 around the first conductive layer 121
When, the area of the first conductive layer 121 is smaller, makes the outer diameter of the riveting part 1231 of top also can be smaller.
In the present embodiment, the first conductive layer 121 of riveted construction R1 protrudes past the outer peripheral surface of riveting part 1231
1231s, and form between the first dielectric layer 122 interface area 199 of handover.During routing, interface area 199 is mentioned
It has supplied to resist the required strength that the second conductive layer 123 and the first dielectric layer 122 are removed, therefore can be to avoid the second conductive layer
It is removed from the first dielectric layer 122, bonding pad structure 120 is made to become a firm bonding pad structure.
Articulamentum 130 and second circuit 140 are formed on the upper surface 110u of three-five substrate 110, wherein second circuit
140 are isolated from each other with bonding pad structure 120, but the first circuit that can be electrically connected at by articulamentum 130 in bonding pad structure 120
124.Second circuit 140 is, for example, Anti-static circuit, active circuits or passive circuit.In another embodiment, if woth no need to,
Articulamentum 130 can also be omitted.In addition, articulamentum 130 can be formed with the first conductive layer 121 in same technique, therefore connect
Layer 130 and the first conductive layer 121 belong to same layer structure (a part that articulamentum 130 can be considered as the first conductive layer 121), and
It can be without apparent interface between articulamentum 130 and the first conductive layer 121.
Fig. 2A is painted the top view of the semiconductor chip 200 according to another embodiment of the present invention, and Fig. 2 B is painted Fig. 2A's
Cross-sectional view of the semiconductor chip 200 along direction 2B-2B '.
Semiconductor chip 200 includes three-five substrate 110, at least a bonding pad structure 220, articulamentum 130 and second circuit
140.Bonding pad structure 220 includes the first conductive layer 121, the first dielectric layer 122, the second conductive layer 123 and the first circuit 124 first
Dielectric layer 122 is formed on the first conductive layer 121 and has several first through hole 122a, these first through hole 122a to expose
First conductive layer 121.Bonding pad structure 220 has structure that is similar or being same as aforementioned bonding pad structure 120, is different in connection pad knot
For first circuit 124 of structure 220 between 2 first through hole 122a, riveted construction R1 is located at the two sides of the first circuit 124.
Fig. 3 is painted the top view of the semiconductor chip 300 according to another embodiment of the present invention.Semiconductor chip 300 includes
Three-five substrate 110, at least a bonding pad structure 320.Unlike aforementioned bonding pad structure, the riveting part of bonding pad structure 320
1231 and first circuit 124 quantity and/or configuration mode it is different, such as in Fig. 3, passed through by riveting part 1231 with corresponding first
The riveted construction R1 (not being illustrated in Fig. 3) for 122a and the first conductive layer 121 (the not being illustrated in Fig. 3) composition of perforating, arrangement are formed
One " ten " fonts, and the first circuit 124 is located at the region other than riveted construction R1.So, as long as being avoided that the first conductive layer 121
It is removed in routing technique, the metal of the second conductive layer 123 is avoided to damage by pressure and avoid the first dielectric layer 122 to collapse under pressure,
The embodiment of the present invention does not limit the quantity and/or configuration mode of riveting part 1231.
Fig. 4 is painted the cross-sectional view of the semiconductor chip 400 according to another embodiment of the present invention.Semiconductor chip 400 includes
Three-five substrate 110 and at least a bonding pad structure 420.Bonding pad structure 420 is formed in the upper surface 110u of three-five substrate 110
On.In another embodiment, semiconductor chip 400 can further include aforementioned articulamentum 130 and second circuit 140.
Bonding pad structure 420 include the first conductive layer 121, the first dielectric layer 122, the second conductive layer 123, the first circuit 124,
Second dielectric layer 424 and third conductive layer 425.The material of third conductive layer 425 similar to the second conductive layer 123 material, and
The material of two dielectric layers 424 is repeated no more similar to the material of the first dielectric layer 122 in this.
Second dielectric layer 424 is formed on the second conductive layer 123 and has at least one second through hole 424a, the second through hole
424a exposes the first connection pad portion 1232.
Due to the design of riveted construction R1, so that being beaten produced by the bonding wire on third conductive layer 425 in bonding process
Pressure and pulling force be not easy to remove the second conductive layer 123 from the first dielectric layer 122, and be not easy first dielectric layer that crushes
122.As long as the present invention is implemented in addition, being avoided that conductive layer is removed in routing technique and dielectric layer is avoided to collapse under pressure
Example does not limit the quantity and/or configuration mode of riveted construction R1.
Fig. 5 is painted the cross-sectional view of the semiconductor chip 500 according to another embodiment of the present invention.Semiconductor chip 500 includes
Three-five substrate 110 and at least a bonding pad structure 520.In another embodiment, semiconductor chip 500 can further include aforementioned connection
Layer 130 and second circuit 140.
Bonding pad structure 520 is formed on the upper surface 110u of three-five substrate 110.Bonding pad structure 520 includes first conductive
The 121, first dielectric layer 122 of layer, the second conductive layer 123, the first circuit 124, the second dielectric layer 424 and third conductive layer 425.The
Two dielectric layers 424 are formed on the second conductive layer 123 and have at least one second through hole 424a, and the second through hole 424a exposes the
One connection pad portion 1232.Unlike the bonding pad structure 420 of previous embodiment, the first electricity of the bonding pad structure 520 of the present embodiment
Road 124 is between 2 first through hole 122a.
Fig. 6 A~6D is please referred to, the process drawing of the bonding pad structure 120 of Figure 1B is painted.
As shown in Figure 6A, three-five substrate 110 is provided, three-five substrate 110 has upper surface 110u.
As shown in Figure 6B, e.g. photolithography techniques can be used, form the first circuit 124, second circuit 140, first
Conductive layer 121 and articulamentum 130 are in three-five substrate 110.It in one embodiment, can be in advance at the first circuit 124 and the second electricity
Then road 140 re-forms the first conductive layer 121 and articulamentum 130, wherein the first conductive layer 121 connects multiple first circuits
124, and articulamentum 130 connects second circuit 140 and the first conductive layer 121.
As shown in Figure 6 C, e.g. coating technique can be used, form the first dielectric material 122 ' and cover the first conductive layer 121
And first circuit 124.
As shown in Figure 6 D, e.g. lithography or laser puncturing technique can be used, form at least one first through hole
122a runs through the first dielectric material 122 ' and removes uncertain one part, to form the first dielectric layer 122, wherein the first through hole
122a exposes the first conductive layer 121.
Then, e.g. photolithography techniques can be used, form the second conductive layer 123 as shown in Figure 1B in the first dielectric
Layer 122, to form bonding pad structure 120 as shown in Figure 1B.
System of the manufacturing process of the bonding pad structure 220,320,420 and 520 of other embodiments similar to aforementioned bonding pad structure 120
Process is made, is repeated no more in this.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape all should fall within the scope of protection of the appended claims of the present invention.
Claims (11)
1. a kind of bonding pad structure is formed on three-five substrate characterized by comprising
One first conductive layer:
One first circuit is connected to first conductive layer；
One first dielectric layer, is formed on first conductive layer and has at least one first through hole, which exposes
First conductive layer；
First through hole and company are filled up in one second conductive layer, including an at least riveting part and one first connection pad portion, the riveting part
Be connected to first conductive layer, and the first connection pad portion is formed in first dielectric layer, the riveting part, first through hole with
First conductive layer constitutes a riveted construction.
2. bonding pad structure according to claim 1, which is characterized in that first dielectric layer is more than one dielectric material weights
It is folded to be formed.
3. bonding pad structure according to claim 1, which is characterized in that the entire outer peripheral surface of the riveting part is by first dielectric
Layer cladding.
4. bonding pad structure according to claim 1, which is characterized in that first conductive layer is connected to one by an articulamentum
Second circuit.
5. bonding pad structure according to claim 1, which is characterized in that further include:
One second dielectric layer, is formed on second conductive layer and has one second through hole, second through hole expose this first
Connection pad portion；And
One third conductive layer, including a filling portion and one second connection pad portion, the filling portion fill up second through hole and are connected to
The first connection pad portion, and the second connection pad portion is formed in second dielectric layer.
6. bonding pad structure according to claim 5, which is characterized in that the quantity of second through hole is one.
7. bonding pad structure according to claim 5, which is characterized in that there is second dielectric layer multiple this second to run through
Hole, the third conductive layer include multiple filling portions, those the second through holes are filled up in those filling portions.
8. a kind of semiconductor chip characterized by comprising
One three-five substrate；And
One bonding pad structure as described in claim 1 is formed on the three-five substrate.
9. semiconductor chip according to claim 8, which is characterized in that further include:
One second circuit is formed on the three-five substrate and is spaced each other with the bonding pad structure；And
One articulamentum is formed on the three-five substrate and connects the second circuit and first conductive layer.
10. a kind of manufacturing method of bonding pad structure characterized by comprising
One first circuit is formed on a three-five substrate；
One first conductive layer is formed on the three-five substrate；
It forms one first dielectric material and covers first conductive layer and first circuit；
One first through hole is formed through first dielectric material, to form one first dielectric layer, which exposes should
First conductive layer；And
One second conductive layer is formed on first dielectric layer, which includes that at least one riveting part and one first connect
Pad portion, the riveting part fill up first through hole and are connected to first conductive layer, and the first connection pad portion be formed in this first
Dielectric layer.
11. manufacturing method according to claim 10, which is characterized in that in formed first conductive layer in the three-five base
Step on plate further includes:
A second circuit and an articulamentum are formed on the three-five substrate, wherein the second circuit and the bonding pad structure be to each other
Every the articulamentum connects second circuit and the first conductive layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107103192A TWI644410B (en) | 2018-01-30 | 2018-01-30 | Pad structure, semiconductor die using the same and manufacturing method thereof |
| TW107103192 | 2018-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110098165A true CN110098165A (en) | 2019-08-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810249228.2A Pending CN110098165A (en) | 2018-01-30 | 2018-03-22 | Bonding pad structure, semiconductor chip and its manufacturing method using the bonding pad structure |
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| Country | Link |
|---|---|
| CN (1) | CN110098165A (en) |
| TW (1) | TWI644410B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI731431B (en) * | 2019-10-04 | 2021-06-21 | 旺宏電子股份有限公司 | Pad structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043144A (en) * | 1998-05-25 | 2000-03-28 | United Microelectronics Corp. | Bonding-pad structure for integrated circuit and method of fabricating the same |
| CN103094293A (en) * | 2011-11-03 | 2013-05-08 | 全视科技有限公司 | Pad Design For Circuit Under Pad In Semiconductor Devices |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6881072B2 (en) * | 2002-10-01 | 2005-04-19 | International Business Machines Corporation | Membrane probe with anchored elements |
| EP2352168A1 (en) * | 2008-11-25 | 2011-08-03 | Sumitomo Bakelite Co., Ltd. | Electronic component package and electronic component package manufacturing method |
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| US9955587B2 (en) * | 2015-04-02 | 2018-04-24 | Jiaxing Super Lighting Electric Appliance Co., Ltd. | LED tube lamp |
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- 2018-03-22 CN CN201810249228.2A patent/CN110098165A/en active Pending
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| US6043144A (en) * | 1998-05-25 | 2000-03-28 | United Microelectronics Corp. | Bonding-pad structure for integrated circuit and method of fabricating the same |
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| TWI644410B (en) | 2018-12-11 |
| TW201933567A (en) | 2019-08-16 |
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