CN110097861A - The gate driving circuit and its display of leakage current can be reduced - Google Patents
The gate driving circuit and its display of leakage current can be reduced Download PDFInfo
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- CN110097861A CN110097861A CN201910417706.0A CN201910417706A CN110097861A CN 110097861 A CN110097861 A CN 110097861A CN 201910417706 A CN201910417706 A CN 201910417706A CN 110097861 A CN110097861 A CN 110097861A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of gate driving circuit, it includes multiple drive element of the grid, N grades of drive element of the grid are used to export N grades of grid impulse signals in output end.The N grades of drive element of the grid include pull-up control circuit, pull-up circuit, drop-down holding circuit, pull-down circuit and under conduct electricity road.The road that conducts electricity under described includes third transistor, the 4th transistor and the 5th transistor.The grid of the third transistor connects the N grades of pre-charge pressure nodes, and drain electrode connects first clock signal, and source electrode exports N grades of initial pulse signals.The grid of 4th transistor connects the drop-down holding circuit, and drain electrode connects the N grades of initial pulse signals.The grid of 5th transistor connects the grid of the 4th transistor, and drain electrode connects the N grades of pre-charge pressure nodes, and source electrode connects the N grades of initial pulse signals.The design on road of conducting electricity under described can reduce the leakage current of the pre-charge pressure node.
Description
Technical field
It is espespecially a kind of to use gate driving (Gate driver on array, GOA) electricity the present invention relates to a kind of display
The display on road.
Background technique
In the necessary condition that liquid crystal display panel low-cost high-quality is industrial technology.Grid array (gate on array,
It GOA is) a kind of method for commonly reducing cost, it is that the function of transistor gate is passed through Thin Film Transistor-LCD
(TFT LCD) processing procedure is done on the glass substrate, is saved gate side drive integrated circuit (IC) and may be used also while cost is reduced
To accomplish Rimless, the competitiveness of product in market is promoted.However work as GOA work at high temperature, it will increase the leakage of transistor in GOA
Electric current makes corresponding node that can not maintain its required voltage quasi position, and then influences GOA performance.
Summary of the invention
It is an object of the present invention to provide a kind of gate driving circuit and its display, by improved circuit design with
The problem of improving the electric leakage of GOA, achievees the effect that the performance for improving GOA is stable.
For the above problem for solving the prior art, the embodiment of the present invention provides a kind of gate driving circuit, and it includes multiple
Drive element of the grid, multiple drive element of the grid couple in series, and N grades of drive element of the grid are used to exporting
N grades of grid impulse signals of end output.The N grades of drive element of the grid include pull-up control circuit, pull-up circuit, drop-down dimension
Hold circuit, pull-down circuit and under conduct electricity road.The pull-up control circuit includes the first transistor, grid and its drain electrode connection the
N-4 grades of initial pulse signals or N-4 grades of grid impulse signals.The pull-up circuit includes second transistor, grid connection
In N grades of pre-charge pressure nodes, drain electrode the first clock signal of connection, source electrode connects the output end.The drop-down maintains
Circuit is electrically connected the pull-up control circuit and first voltage source.The pull-down circuit is electrically connected the N grades of preliminary fillings
Voltage node and the output end.The road that conducts electricity under described includes third transistor, the 4th transistor and the 5th transistor.It is described
The grid of third transistor connects the N grades of pre-charge pressure nodes, and drain electrode connects first clock signal, and source electrode is defeated
N grades of initial pulse signals out.The grid of 4th transistor connects the drop-down holding circuit, drain electrode connection described the
N grades of initial pulse signals, source electrode connect the first voltage source.The grid of 5th transistor connects the 4th crystal
The grid of pipe, drain electrode connect the N grades of pre-charge pressure nodes, and source electrode connects the N grades of initial pulse signals.Wherein
N is positive integer.
Embodiment according to the present invention, the gate driving circuit separately include capacitor, and the both ends of the capacitor are separately connected
The N grades of pre-charge pressure nodes and the output end.
Embodiment according to the present invention, first clock signal and the second clock pulse signal reverse phase each other.
Embodiment according to the present invention, the drop-down holding circuit include the 6th transistor, the 7th transistor, the 8th crystal
Pipe and the 9th transistor.The grid of 6th transistor and its drain electrode connect first clock signal.7th crystal
The grid of pipe connects the N grade pre-charge pressure nodes, and drain electrode connects the source electrode of the 6th transistor, and source electrode connects the
One voltage source.The grid of 8th transistor connects the source electrode of the 6th transistor, and drain electrode connects first clock
Signal, source electrode connect the grid of the 4th transistor.The grid of 9th transistor connects the N grades of pre-charge pressures
Node, drain electrode connect the grid of the 4th transistor, and source electrode connects the first voltage source.
Embodiment according to the present invention, the drop-down holding circuit separately includes the tenth transistor, and grid is described in connection
The source electrode of 8th transistor, drain electrode connect the N grades of pre-charge pressure nodes, and source electrode connects the output end.
Embodiment according to the present invention, the drop-down holding circuit separately include the 11st transistor, the tenth two-transistor with
And the 13rd transistor.The grid of 11st transistor is the source electrode for connecting the 8th transistor, drain electrode connection institute
Output end is stated, source electrode connects the first voltage source.The grid of tenth two-transistor connects second clock signal, leakage
Pole connects the N grades of pre-charge pressure nodes, and source electrode receives the N-4 grades of initial pulse signals or the N-4 grades of grid
Pole pulse signal.The grid of 13rd transistor connects the second clock signal, and drain electrode connects the output end,
Source electrode connects the first voltage source.
Embodiment according to the present invention, the pull-down circuit include the 14th transistor and the 15th transistor.Described
The grids of 14 transistors connects N+4 grade initial pulse signals or N+4 grade grid impulse signals, drains and connects described the
N grades of pre-charge pressure nodes, source electrode connect the first voltage source.The grid of 15th transistor receives the N+4
The grade initial pulse signal or N+4 grade grid impulse signals, drain electrode connect the output end, and source electrode connects described the
One voltage source.
The duty ratio of embodiment according to the present invention, first clock signal and the second clock pulse signal is all
50%.
Embodiment according to the present invention, the gate driving circuit are used for amorphous silicon (a-si) liquid crystal display or oxidation
Indium gallium zinc (indium gallium zinc oxide, IGZO) liquid crystal display.
The present invention separately provides a kind of display, including liquid crystal display panel and the above-mentioned gate driving circuit.It is described
Liquid crystal display panel is for showing image, and the gate driving circuit is integrated in the liquid crystal display panel.
Compared to the prior art, the present invention provides a kind of gate driving circuit and its display, gate driving circuit include
Multiple drive element of the grid.Each N grades of drive element of the grid include pull-up control circuit, pull-up circuit, drop-down maintenance
Circuit, pull-down circuit and under conduct electricity road.The road that conducts electricity under described includes third transistor, the 4th transistor and the 5th transistor.Institute
The grid for stating third transistor connects the N grades of pre-charge pressure nodes, and drain electrode connects first clock signal, source electrode
Export N grades of initial pulse signals.The grid of 4th transistor connects the drop-down holding circuit, drains described in connection
N grades of initial pulse signals.The grid of 5th transistor connects the grid of the 4th transistor, drains described in connection
N grades of pre-charge pressure nodes, source electrode connect the N grades of initial pulse signals.The design on road of conducting electricity under described can be reduced
The leakage current of the pre-charge pressure node.
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will make below to required in the embodiment of the present invention
Attached drawing is briefly described, it should be apparent that, drawings described below is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is painted the schematic diagram of inventive display.
Fig. 2 is the equivalent circuit diagram of the drive element of the grid of Fig. 1.
Fig. 3 be each drive element of the grid of the gate driving circuit of Fig. 1 applied clock signal CK1-CK8, N grades
Initial pulse signal ST (N) to N+4 grades initial pulse signal ST (N+4) and N grades of grid impulse signal G (N) are to N+4
The timing diagram of grade grid impulse signal G (N+4).
Fig. 4 is the circuit diagram of one embodiment of drive element of the grid of Fig. 2.
Fig. 5 is painted Fig. 3 embodiment figure compared with N grades of pre-charge pressure node Q (N) current potentials of the prior art.
Specific embodiment
The explanation of following embodiment is to can be used to the particular implementation of implementation to illustrate the present invention with reference to additional schema
Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "top", "bottom", " water
It is flat ", " vertical " etc., be only the direction for referring to annexed drawings.Therefore, the direction term used is to illustrate and understand this hair
It is bright, rather than to limit the present invention.
Referring to Fig. 1, Fig. 1 is painted the schematic diagram of inventive display 10.Display 10 can be amorphous silicon (a-si) liquid
Crystal display or indium gallium zinc (indium gallium zinc oxide, IGZO) liquid crystal display.Display 10 includes
Liquid crystal display panel 20 and the gate driving circuit 30 being integrated on liquid crystal display panel 20.Further, since large-sized liquid crystal
In display panel, resistance (R) combines the delay (RCDelay) of capacitor (C) than more serious, therefore gate driving circuit 30 is to use
8 clock signal CK1-CK8 drive.The duty ratio (duty ratio) of 8 clock signal CK1-CK8 is all 50%, and
And phase sequentially postpones 45 degree.That is, the phase that the phase of clock signal CK2 falls behind clock signal CK1 is 45 degree, clock
The phase that the phase of signal CK3 falls behind clock signal CK1 is 90 degree, and so on.Gate driving circuit 30 has multiple grids to drive
Moving cell 100 forms, and multiple drive element of the grid 100 couple in series, and N grades of drive element of the grid 100 are used to
Output end exports N grades of grid impulse signals.First order drive element of the grid 100 is driven by clock signal CK1 and CK5,
Second level drive element of the grid 100 is driven by clock signal CK2 and CK6, and third level drive element of the grid 100 is by clock
Signal CK3 and CK7 are driven, and so on.
Referring to Fig. 2, Fig. 2 is the equivalent circuit diagram of the drive element of the grid 100 of Fig. 1.N grades of drive element of the grid 100
Including pull-up control circuit 200, pull-up circuit 300, drop-down holding circuit 400, pull-down circuit 500, under conduct electricity road 600 and capacitor
Cb.It pulls down holding circuit 400 and is electrically connected pull-up control circuit 200 and first voltage source VSS.Pull-down circuit 500 electrically connects
Meet N grades of pre-charge pressure node Q (N) and output end G (N).Under conduct electricity road 600 be electrically connected pull-up control circuit 200 and under
Holding circuit 400 is drawn, is used to reduce the electric leakage of N grades of pre-charge pressure node Q (N) according to N grades of initial pulse signal ST (N)
Stream.
Fig. 2 and Fig. 3 are please referred to, Fig. 3 is that each drive element of the grid 100 of the gate driving circuit 30 of Fig. 1 is applied
Clock signal CK1-CK8, N grades of initial pulse signal ST (N) to N+4 grades of initial pulse signal ST (N+4) and N grades of grid
Pole pulse signal G (N) to N+4 grades of grid impulse signal G (N+4) timing diagram.
Referring to Fig. 4, Fig. 4 is the circuit diagram of 100 1 embodiment of drive element of the grid of Fig. 2.The depicted pull-up control of Fig. 4
Circuit 200, pull-up circuit 300, drop-down holding circuit 400 and the circuit design of pull-down circuit 500 are a reference implementation example, and
It is non-to be used to limit the present invention.Pull-up control circuit 200 includes the first transistor T1, and grid and its N-4 grades of drain electrode connection rise
Initial pulse signal ST (N-4) or N-4 grades of grid impulse signal G (N-4).Pull-up circuit 300 includes second transistor T2, grid
Pole is connected to N grades of pre-charge pressure node Q (N), drain electrode the first clock signal CKV1 of connection, and source electrode connects output end G
(N).Under conduct electricity road 600 include third transistor T3, the 4th transistor T4 and the 5th transistor T5.The grid of third transistor T3
N grades of pre-charge pressure node Q (N), drain electrode the first clock signal CKV1 of connection are connected, source electrode exports N grades of initial pulses
Signal ST (N).The grid connection drop-down holding circuit 400 of 4th transistor T4, N grades of initial pulse signal ST of drain electrode connection
(N), source electrode connects first voltage source VSS.The grid of 5th transistor T5 connects the grid of the 4th transistor T4, and drain electrode connects
N grades of pre-charge pressure node Q (N) are connect, source electrode connects N grades of initial pulse signal ST (N).This example demonstrates that in, N is
Positive integer greater than 4.
Pulling down holding circuit 400 includes the 6th transistor T6, the 7th transistor T7, the 8th transistor T8 and the 9th transistor
T9.The first clock signal CKV1 of the grid of 6th transistor T6 and its drain electrode connection.The grid of 7th transistor T7 connects N grades
Pre-charge pressure node Q (N), the source electrode of the 6th transistor T6 of drain electrode connection, source electrode connect first voltage source VSS.8th is brilliant
The grid of body pipe T8 connects the source electrode of the 6th transistor T6, drain electrode the first clock signal CKV1 of connection, source electrode connection the 4th
The grid of transistor T4.The grid of 9th transistor T9 connects N grades of pre-charge pressure node Q (N), drain electrode the 4th crystal of connection
The grid of pipe T4, source electrode connect first voltage source VSS.
Pull down holding circuit 400 separately include the tenth transistor T10, the 11st transistor T11, the tenth two-transistor T12 with
And the 13rd transistor T13.The grid of tenth transistor T10 is the source electrode for connecting the 8th transistor T8, N grades of drain electrode connection
Pre-charge pressure node Q (N), source electrode connect output end G (N).The grid of 11st transistor T11 is the 8th transistor T8 of connection
Source electrode, drain electrode connection output end G (N), source electrode connect first voltage source VSS.The grid of tenth two-transistor T12 connects
Second clock signal CKV2, drain electrode N grades of pre-charge pressure node Q (N) of connection, source electrode receive N-4 grades of initial pulse letters
Number ST (N-4) or N-4 grades of grid impulse signal G (N-4).The grid of 13rd transistor T13 connects second clock signal
CKV2, drain electrode connection output end G (N), source electrode connect first voltage source VSS.
Pull-down circuit 500 includes the 14th transistor T14 and the 15th transistor T15.The grid of 14th transistor T14
Connect N+4 grades of initial pulse signal ST (N+4) or N+4 grades of grid impulse signal G (N+4), drain electrode N grades of preliminary fillings of connection
Voltage node Q (N), source electrode connect first voltage source VSS.The grid of 15th transistor T15 receives N+4 grades of initial pulses
Signal ST (N+4) or N+4 grades of grid impulse signal G (N+4), drain electrode connection output end G (N), the first electricity of source electrode connection
Potential source VSS.The both ends of capacitor Cb are separately connected N grades of pre-charge pressure node Q (N) and output end G (N).
By taking first order drive element of the grid 100 as an example, the first clock signal CKV1 and second clock signal CKV2 are respectively
Clock signal CK1 and clock signal CK5 shown in FIG. 1.First clock signal CKV1 of second level drive element of the grid 100 and
Two clock signal CKV2 are clock signal CK2 and clock signal CK6 shown in FIG. 1 respectively, third level drive element of the grid 100
First clock signal CKV1 and second clock signal CKV2 is clock signal CK3 and clock signal CK7 shown in FIG. 1 respectively, with
This analogizes.
N grades of pre-charge pressure node Q (N) of Fig. 3 embodiment and the prior art are painted also referring to Fig. 3 to Fig. 5, Fig. 5
The comparison figure of current potential.When the first clock signal CKV1 is high potential, N grades of initial pulse signal ST (N) are also high potential, this
When, the output signal P (N) of drop-down holding circuit 400 is low potential.Therefore the cross-pressure Vgs between the grid and source electrode of transistor T5
It can be very low low potential, so that transistor T5 is almost closed, to make the charge of N grades of pre-charge pressure node Q (N) not
It is easy to run off, and N grades of pre-charge pressure node Q (N) is made to maintain stable current potential.As shown in figure 5, compared to the prior art,
Current potential (curve 202) of the current potential (curve 201) of N grades of pre-charge pressure node Q (N) of the invention than prior art Q (N) is high,
This indicates that the charge of N grades of pre-charge pressure node Q (N) of the invention is higher, that is, the leakage current of pre-charge pressure node Q (N)
It is less.
Transistor T1-T15 depicted in Fig. 4 is N-type transistor, however those skilled in the art can be through the invention
Disclosure it is understood that transistor T1-T15 may be P-type transistor.
In summary, it includes multiple grid that the present invention, which provides a kind of gate driving circuit and its display, gate driving circuit,
Pole driving unit.Each N grades of drive element of the grid include pull-up control circuit, pull-up circuit, drop-down holding circuit, under
Puller circuit and under conduct electricity road.The road that conducts electricity under described includes third transistor, the 4th transistor and the 5th transistor.The third is brilliant
The grid of body pipe connects the N grades of pre-charge pressure nodes, and drain electrode connects first clock signal, and source electrode exports N
Grade initial pulse signal.The grid of 4th transistor connects the drop-down holding circuit, and described N grades of drain electrode connection are risen
Initial pulse signal.The grid of 5th transistor connects the grid of the 4th transistor, and described N grades of drain electrode connection pre-
Charging voltage node, source electrode connect the N grades of initial pulse signals.The design on road of conducting electricity under described can reduce the preliminary filling
The leakage current of voltage node.
Although the preferred embodiment is not to limit in conclusion the present invention has been disclosed as a preferred embodiment
The present invention, those of ordinary skill in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of gate driving circuit includes multiple drive element of the grid, multiple drive element of the grid are in series
Coupling, N grades of drive element of the grid are used to export N grades of grid impulse signals in output end, which is characterized in that described N grades
Drive element of the grid includes:
Pull-up control circuit, comprising:
The first transistor, grid and its drain electrode N-4 grades of initial pulse signal of connection or N-4 grades of grid impulse signals；
Pull-up circuit, comprising:
Second transistor, grid are connected to N grades of pre-charge pressure nodes, drain electrode the first clock signal of connection, and source electrode connects
Connect the output end；
Holding circuit is pulled down, the pull-up control circuit and first voltage source are electrically connected；
Pull-down circuit is electrically connected the N grades of pre-charge pressure nodes and the output end；
Under conduct electricity road, comprising:
Third transistor, grid connect the N grades of pre-charge pressure nodes, and drain electrode connects first clock signal,
Source electrode exports N grades of initial pulse signals；
4th transistor, grid connect the drop-down holding circuit, and drain electrode connects the N grades of initial pulse signals,
Source electrode connects the first voltage source；And
5th transistor, grid connect the grid of the 4th transistor, and drain electrode connects the N grades of pre-charge pressure sections
Point, source electrode connect the N grades of initial pulse signals,
Wherein N is positive integer.
2. gate driving circuit according to claim 1, which is characterized in that it separately includes capacitor, the both ends of the capacitor
It is separately connected the N grades of pre-charge pressure nodes and the output end.
3. gate driving circuit according to claim 1, which is characterized in that first clock signal and it is described second when
Clock signal reverse phase each other.
4. gate driving circuit according to claim 1, which is characterized in that the drop-down holding circuit includes:
6th transistor, grid and its drain electrode connect first clock signal；
7th transistor, grid connect the N grades of pre-charge pressure nodes, and drain electrode connects the source of the 6th transistor
Pole, source electrode connect the first voltage source；
8th transistor, grid connect the source electrode of the 6th transistor, and drain electrode connects first clock signal, source
Pole connects the grid of the 4th transistor；And
9th transistor, grid connect the N grades of pre-charge pressure nodes, and drain electrode connects the grid of the 4th transistor
Pole, source electrode connect the first voltage source.
5. gate driving circuit according to claim 4, which is characterized in that the drop-down holding circuit separately includes:
Tenth transistor, grid are the source electrodes for connecting the 8th transistor, and drain electrode connects the N grades of pre-charge pressure sections
Point, source electrode connect the output end.
6. gate driving circuit according to claim 4, which is characterized in that the drop-down holding circuit separately includes:
11st transistor, grid are the source electrodes for connecting the 8th transistor, and drain electrode connects the output end, source electrode
Connect the first voltage source；
Tenth two-transistor, grid connect second clock signal, and drain electrode connects the N grades of pre-charge pressure nodes, source
Pole receives the N-4 grades of initial pulse signals or the N-4 grades of grid impulse signals；And
13rd transistor, grid connect the second clock signal, and drain electrode connects the output end, and source electrode connects institute
State first voltage source.
7. gate driving circuit according to claim 1, which is characterized in that the pull-down circuit includes:
14th transistor, grid connect N+4 grades of initial pulse signals or N+4 grades of grid impulse signals, and drain electrode connects
The N grades of pre-charge pressure nodes are connect, source electrode connects the first voltage source；And
15th transistor, grid receive the N+4 grades of initial pulse signals or the N+4 grades of grid impulse signals,
It, which drains, connects the output end, and source electrode connects the first voltage source.
8. gate driving circuit according to claim 1, which is characterized in that first clock signal and it is described second when
The duty ratio of clock signal is all 50%.
9. gate driving circuit according to claim 1, which is characterized in that the gate driving circuit is used for amorphous silicon
(a-si) liquid crystal display or indium gallium zinc (indium gallium zinc oxide, IGZO) liquid crystal display.
10. a kind of display, comprising liquid crystal display panel and according to claim 1 gate driving circuit described in -9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910417706.0A CN110097861A (en) | 2019-05-20 | 2019-05-20 | The gate driving circuit and its display of leakage current can be reduced |
| PCT/CN2019/091634 WO2020232781A1 (en) | 2019-05-20 | 2019-06-18 | Gate driving circuit capable of reducing leakage current, and display including gate driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910417706.0A CN110097861A (en) | 2019-05-20 | 2019-05-20 | The gate driving circuit and its display of leakage current can be reduced |
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| Publication Number | Publication Date |
|---|---|
| CN110097861A true CN110097861A (en) | 2019-08-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910417706.0A Pending CN110097861A (en) | 2019-05-20 | 2019-05-20 | The gate driving circuit and its display of leakage current can be reduced |
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| Country | Link |
|---|---|
| CN (1) | CN110097861A (en) |
| WO (1) | WO2020232781A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110890077A (en) * | 2019-11-26 | 2020-03-17 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and liquid crystal display panel |
| CN112071250A (en) * | 2020-09-04 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN115050338A (en) * | 2022-06-15 | 2022-09-13 | Tcl华星光电技术有限公司 | Grid driving circuit, display panel and display device |
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| WO2022047951A1 (en) * | 2020-09-04 | 2022-03-10 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
| US11640778B2 (en) | 2020-09-04 | 2023-05-02 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | GOA circuit |
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| WO2020232781A1 (en) | 2020-11-26 |
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Application publication date: 20190806 |