CN110086463A - Delay circuit and semiconductor device including the delay circuit - Google Patents
Delay circuit and semiconductor device including the delay circuit Download PDFInfo
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- CN110086463A CN110086463A CN201910415211.4A CN201910415211A CN110086463A CN 110086463 A CN110086463 A CN 110086463A CN 201910415211 A CN201910415211 A CN 201910415211A CN 110086463 A CN110086463 A CN 110086463A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
Abstract
This application discloses delay circuit and including the semiconductor device of the delay circuit.The delay circuit includes: the first delay lock loop, it includes the first delay chain connect with clock signal input terminal and comprising first group of delay cell, and first delay cell in first group of delay cell is configured as being output to the outside the first postpones signal；Second delay lock loop, it includes the second delay chain connect with clock signal input terminal and comprising second group of delay cell and third group delay cell interconnected, and second delay cell corresponding with above-mentioned first delay cell in second group of delay cell is configured as being output to the outside the second postpones signal, the delay time of this three groups of delay cells is different, and the delay time of first group of delay cell is greater than the delay time of third group delay cell.By technical solution provided by the present application, the delay-time difference between the postpones signal that different delays locking ring is exported can reduce.
Description
Technical field
This application involves technical field of integrated circuits, in particular to delay circuit and the semiconductor dress including the delay circuit
It sets.
Background technique
The description of this part only provides and discloses relevant background information to the application, without constituting the prior art.
The quantization time of the delay time less than gate circuit may be implemented in time-to-digit converter (TDC) based on vernier method
Therefore precision is used widely in high-precision time measurement system.The basic principle of TDC based on vernier method is such as
Shown in Fig. 1, time difference of this two-way clock signal is T=(n1-n2) * T1+n2* (T1-T2), wherein T1 and T2 is respectively the
The period of one clock signal and second clock signal, and T1 is greater than the phase that T2, n1 and n2 are respectively this two-way clock signal
Counting when consistent.This two-way clock signal can be realized by delay circuit.
Delay circuit in the prior art generally includes fast delay lock loop (DLL), slow DLL, phase frequency detector (PFD)
With charge pump (CP) etc., as shown in Figure 2.Wherein, fast DLL and slow DLL includes identical multiple delay cells, can be used
According to the corresponding postpones signal of the received clock signal generation of institute.PFD can be used for judging the delay in fast DLL and slow DLL
The postpones signal of unit output and the frequency/phase difference of clock signal (CLK), and control CP adjustment reference voltage VCTRLFWith
VCTRLSAnd the delay time of adjustment delay cell, until clock signal reaches consistent with the frequency of postpones signal with phase, i.e.,
Locking is formed, at this time reference voltage VCTRLFWith VCTRLSIt keeps constant.When fast DLL and slow DLL are locked, the two is exported
Postpones signal between delay-time difference beWherein, TSAnd TFPoint
Not Wei delay cell output in slow DLL and fast DLL delay time, TCLKFor the period of clock signal, N is delay cell
Number.
During realizing the application, at least there are the following problems in the prior art for inventor's discovery:
In order to reduce delay-time difference, it usually needs increase the number of delay cell, this will occupy biggish chip face
Product.Moreover, being limited to the factors such as integrated circuit fabrication process, there are minimum delay times for delay cell, so if for reality
Existing the smallest delay-time difference, then will increase the difficulty of integrated circuit fabrication process.
Summary of the invention
The purpose of the embodiment of the present application is to provide a kind of delay circuit and the semiconductor device including the delay circuit, to subtract
The delay-time difference between postpones signal that small different delays locking ring is exported.
In order to solve the above-mentioned technical problem, the embodiment of the present application provides a kind of delay circuit, which can wrap
It includes:
First delay lock loop comprising being connect with clock signal input terminal and comprising first group of delay cell first
Delay chain, and first delay cell in first group of delay cell is configured as being output to the outside the first delay
Signal；And
Second delay lock loop comprising being connect with the clock signal input terminal and include second group interconnected
Second delay chain of delay cell and third group delay cell, and in second group of delay cell with export described the
Corresponding second delay cell of first delay cell of one postpones signal is configured as being output to the outside the second delay
Signal,
Wherein, first group of delay cell, second group of delay cell and the third group delay cell are prolonged
The slow time is different, and the delay time of first group of delay cell is greater than the delay of the third group delay cell
Time.
Optionally, first delay lock loop further includes first voltage generation circuit, first voltage output end and institute
The first input end for stating first group of delay cell is connected in parallel, and its first feedback signal input terminal prolongs with described first group
The postpones signal output end connection of first delay cell of the end positioned at first delay chain in slow unit；Described
Two delay lock loops further include second voltage generation circuit and tertiary voltage generation circuit, wherein the second voltage generates electricity
The second voltage output end on road and the first input end of second group of delay cell are connected in parallel, and its second feedback letter
The delay of the third delay cell of the end positioned at second delay chain in number input terminal and the third group delay cell
Signal output end connection；The of the tertiary voltage output end of the tertiary voltage generation circuit and the third group delay cell
The connection of one input terminal.
Optionally, when the first voltage generation circuit be supplied to the first reference voltage of first group of delay cell with
The second voltage generation circuit be supplied to second group of delay cell the second reference voltage it is identical when, described first group
Delay cell is different from second group of delay cell；Or work as first reference voltage and second reference voltage not
Meanwhile first group of delay cell and second group of delay cell are identical or different.
Optionally, first group of delay cell and second group of delay include different voltage-controlled delay units or voltage-controlled
Inverting delay cells, or including being connected with each other and different one or more phase inverters.
Optionally, the first voltage generation circuit include sequentially connected first phase frequency detector, the first charge pump and
First loop filter, wherein be provided on first phase frequency detector first feedback signal input terminal and with it is described
Clock signal input terminal connection, and the first voltage output end is provided on first loop filter；Described second
Voltage generation circuit includes sequentially connected second phase frequency detector, the second charge pump and the second loop filter, wherein institute
It states and is provided with second feedback signal input terminal on the second phase frequency detector and is connect with the clock signal input terminal, and
And the second voltage output end is provided on second loop filter.
Optionally, the tertiary voltage generation circuit includes fixed voltage generation circuit or adjustable voltage generation circuit.
Optionally, the fixed voltage generation circuit includes the bias voltage feed end of the delay circuit.
Optionally, when in the third group delay cell only comprising a third delay cell or it includes it is multiple described
When third delay cell is all the same, the adjustable voltage generation circuit includes third delay lock loop, the third delay lock
Determining ring includes the third delay chain and the 4th voltage generation circuit being made of the 4th group of delay cell, and the 4th voltage
The first input end and the third group delay cell of 4th voltage output end of generation circuit and the 4th group of delay cell
First input end be connected in parallel, and be located at institute in its 4th feedback signal input terminal and the 4th group of delay cell
State the postpones signal output end connection of the 4th delay cell of the end of third delay chain.
Optionally, when in the third group delay cell only comprising a third delay cell or it includes it is multiple described
When third delay cell is all the same, the adjustable voltage generation circuit includes sequentially connected 4th delay lock loop to M
Delay lock loop, and the 4th delay lock loop the prolonging to each of M delay lock loop delay lock loop
Slow control of the time by reference voltage caused by next delay lock loop connected to it, M are just whole greater than 4
Number.
Optionally, the 4th delay lock loop to the M-1 delay lock loop includes by sequentially connected two groups
The delay chain and provide reference voltage for one group of delay cell into two groups of delay cell that delay cell is constituted
Voltage generation circuit, the reference voltage of another group of delay cell in two groups of delay cell is by connected to it next
Voltage generation circuit in delay lock loop provides.
Optionally, the M delay lock loop includes the delay chain being made of one group of delay cell and for described
The voltage that another group of delay cell in one group of delay cell and the M-1 delay lock loop provides reference voltage generates electricity
Road.
Optionally, delay cell included by delay cell described in same group is identical, and the different group delay cells
Included delay cell is different.
Optionally, the delay cell for providing reference voltage by the same voltage generation circuit is identical.
Optionally, described adjustable when the third group delay cell includes different multiple third delay cells groupings
Section voltage generation circuit includes multiple delay lock loops corresponding with multiple third delay cell groupings, and multiple institutes
State each of delay lock loop and include the delay chain being made of one group of delay cell and for one group of delay
Unit and the corresponding third delay cell grouping provide the voltage generation circuit of third reference voltage.
Optionally, described adjustable when the third group delay cell includes different multiple third delay cells groupings
Section voltage generation circuit includes multiple groups delay lock loop corresponding with multiple third delay cell groupings, and every group of institute
State delay lock loop and include sequentially connected multiple delay lock loops, and each of multiple described delay lock loops
Control of the delay time of delay lock loop by reference voltage caused by next delay lock loop connected to it.
Optionally, the delay circuit further include: the first multiple selector is configured as from first group of delay list
Selection is output to the outside first delay cell of the first postpones signal and postpones selected described first single in member
First postpones signal that member generates is output to outside；And/or second multiple selector, it is configured as from described second
Selection is output to the outside second delay cell of the second postpones signal and by selected described the in group delay cell
Second postpones signal that two delay cells generate is output to outside.
Optionally, the delay circuit further include: clock signal generating circuit passes through the clock signal input terminal point
The first clock signal and second clock signal are not provided to first delay lock loop and second delay lock loop.
The embodiment of the present application also provides a kind of semiconductor device, which may include above-mentioned delay circuit.
As can be seen from the technical scheme provided by the above embodiments of the present application, the embodiment of the present application can be by locking different delays
Determine the delay cell in ring and be embodied as the delay time for having different, is exported so as to reducing different delays locking ring
Delay-time difference between postpones signal, and then can reduce occupied resources of chip.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, in the premise of not making the creative labor property
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the schematic illustration of the TDC in the prior art based on vernier method；
Fig. 2 is the structural schematic diagram of delay circuit in the prior art；
Fig. 3 is a kind of structural schematic diagram of delay circuit provided by the present application；
Fig. 4 is a kind of structural schematic diagram for delay circuit that embodiments herein provides；
Fig. 5 is the structural schematic diagram of first voltage generation circuit；
Fig. 6 is the structural schematic diagram of second voltage generation circuit；
Fig. 7 is the structural schematic diagram for another delay circuit that embodiments herein provides；
Fig. 8 is the structural schematic diagram for another delay circuit that embodiments herein provides；
Fig. 9 is the structural schematic diagram for another delay circuit that embodiments herein provides；
Figure 10 is the structural schematic diagram for another delay circuit that embodiments herein provides；
Figure 11 is the structural schematic diagram for another delay circuit that embodiments herein provides；
Figure 12 is the structural schematic diagram of one group of delay lock loop in the delay circuit in Figure 11；
Figure 13 is the structural schematic diagram for another delay circuit that embodiments herein provides；
Figure 14 is the structural schematic diagram for another delay circuit that embodiments herein provides.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiment is only used for illustrating a part of the embodiment of the application, rather than complete
The embodiment in portion, it is undesirable that limitation scope of the present application or claims.Based on the embodiment in the application, this field
This all should belong in those of ordinary skill's all other embodiment obtained without making creative work
Apply for the range of protection.
It should be noted that it can be arranged directly on another when element is referred to as on " setting exists " another element
On element or there may also be elements placed in the middle.When element is referred to as " connection/connection " to another element, it be can be
It is directly connected to/is attached to another element or may be simultaneously present centering elements.Term as used herein " connection/connection
Connect " it may include electrical and/or mechanical-physical connection/connection.Term as used herein "comprises/comprising" refers to feature, step
Or the presence of element, but the presence or addition of one or more other features, step or element is not precluded.Made herein
Term "and/or" includes any and all combinations of one or more related listed items.
Unless otherwise defined, all technical and scientific terms used herein and the technical field for belonging to the application
The normally understood meaning of technical staff is identical.Term used herein is intended merely to the purpose of description specific embodiment, and
It is not intended to limitation the application.
In addition, term " first ", " second ", " third " etc. are used for description purposes only and distinguish in the description of the present application
Similar object between the two and is not present sequencing, can not be interpreted as indication or suggestion relative importance.In addition,
In the description of the present application, unless otherwise indicated, the meaning of " plurality " is two or more.
Delay circuit provided by the embodiments of the present application and semiconductor device are described in detail with reference to the accompanying drawing.
As shown in figure 3, the embodiment of the present application provides a kind of delay circuit 1000, may include:
First delay lock loop 100 comprising being connect with clock signal input terminal and comprising first group of delay cell
First delay chain 110, and first delay cell 111 in first group of delay cell is configured as being output to the outside
One postpones signal；And
Second delay lock loop 200 comprising being connect with clock signal input terminal and include second group interconnected
Second delay chain 210 of delay cell and third group delay cell, and postpone in second group of delay cell with output first
Corresponding second delay cell 211 of the first delay cell 111 of signal is configured as being output to the outside the second delay letter
Number,
Wherein, the delay time of first group of delay cell, second group of delay cell and third group delay cell each not phase
Together, and the delay time of first group of delay cell be greater than third group delay cell delay time.
According to the first time information and the output of the second delay cell in the first postpones signal of the first delay cell output
The second postpones signal in the second temporal information and combine the first delay cell in first group of delay cell and second group is prolonged
The quantity of the second delay cell in slow unit, can determine postpones signal that the two delay lock loops are exported it
Between delay-time difference.
It can under the conditions of integrated circuit fabrication process same as the prior art by the above-mentioned technical proposal of the application
With by the delay time for being embodied as the delay cell in different delays locking ring to have different, so as to reduce difference
Delay-time difference between the postpones signal of delay lock loop output.
The specific implementation of the embodiment of the present application is described below with several specific examples.
Referring to Fig. 4, it may include the first delay lock loop that the embodiment of the present application, which provides a kind of delay circuit 1000,
100 and second delay lock loop 200, and the first delay lock loop 100 and the second delay lock loop 200 can pass through clock
Signal input part 300 connects.First delay lock loop 100 can be configured as to be received according to by clock signal input terminal 300
The first clock signal clk 1 generate corresponding first postpones signal, the second delay lock loop 200 can be configured as according to logical
The received second clock signal CLK2 of oversampling clock signal input part generates corresponding second postpones signal.According to the first delay letter
The second temporal information in first time information and the second postpones signal in number, can determine the first delay lock loop 100
Delay-time difference between first postpones signal of output and the second postpones signal of the second delay lock loop 200 output.
First delay lock loop 100 may include the first delay chain 110 and the first electricity connecting with clock signal input terminal
Press generation circuit 120.Wherein, the first delay chain 110 can be configured as produces under the control of first voltage generation circuit 120
Raw the first postpones signal corresponding with received first clock signal of institute, and prolong to the feedback of first voltage generation circuit 120 first
Slow signal.First voltage generation circuit 120, which can be configured as, generates corresponding first according to received first clock signal of institute
Reference voltage is (corresponding to the V in Fig. 3ref1), to the first delay chain 110 provide the first reference voltage, and according to first delay
The first postpones signal that chain 110 is fed back adjusts the first reference voltage.
First delay chain 110 may include by identical and sequentially connected N1(N1For the positive integer greater than 1, for example, it is
4) first group of delay cell that a first delay cell 111 is constituted.This N1A first delay cell 111 may each comprise first
Input terminal, the second input terminal and postpones signal output end, and the first postpones signal (1) can be exported respectively to the first delay
Signal (N1).Wherein, this N1The first input end of a first delay cell 111 can be connected in parallel to first voltage and generate electricity
The first voltage output end on road 120 to receive the first reference voltage of the offer of first voltage generation circuit 120, and is located at the
Second input terminal of first the first delay cell 111 of the starting point of one delay chain 110 can connect to clock signal and generate
Device 300, the N of the second input terminal of second the first delay cell 111 to the end for being located at the first delay chain 1101A
Second input terminal of one delay cell 111 can be respectively connected to first the first delay cell 111 to N1- 1 first is prolonged
The postpones signal output end of slow unit, and N1The postpones signal output end of a first delay cell 111 can connect to
The feedback signal input terminal of one voltage generation circuit 120, to feed back the first postpones signal to first voltage generation circuit 120
(N1).In addition, this N1Any one first delay cell 111 in a first delay cell 111 is (for example, second first is prolonged
Slow unit 111) postpones signal output end may be used to be output to the outside the first postpones signal, that is to say, that the first delay
Signal can be the first postpones signal (1) to the first postpones signal (N1) in any one.
This N1A first delay cell 111 may each be voltage-controlled delay unit or voltage-controlled inverting delay cells, can also be
It is made of one or more phase inverters.In addition, the first delay time of each first delay cell 111 is identical, and can be with
It is expressed as follows:Wherein, T1Indicate the first delay time, TCLK1Indicate the period of the first clock signal.In addition, every
First delay time of a first delay cell 111, can be with the first reference voltage by the control of the first reference voltage
Increase and be decreased or increased, and the first postpones signal of each first delay cell 111 output is when can be locked in first
Clock signal, that is, when the first delay lock loop 100 is locked, the first postpones signal and the first clock signal have consistent frequency
Rate and phase simultaneously keep stable.Moreover, when the first delay lock loop 100 is locked, the of each first delay cell 111
One delay time can be greater than the minimum delay time of first delay cell 111, which can be according to this
The manufacturing process of first delay cell determines, for example, can be 2ns.
As shown in figure 5, first voltage generation circuit 120 may include sequentially connected first phase frequency detector (PFD)
121, the first charge pump (CP) 122 and the first loop filter (LF) 123.It wherein, can be on the first phase frequency detector 121
Clock signal input terminal connection, and can be set and N1The postpones signal output end of a first delay cell 111 connects
The first feedback signal input terminal, and its can be used for comparing clock signal generating apparatus 300 transmission first clock signal
With N1The first postpones signal (N that a first delay cell 111 is fed back1) frequency and phase, and according to comparing result control
It makes the first charge pump 122 and adjusts generated first reference voltage；First charge pump 122 can be used in the first frequency and phase discrimination
The first reference voltage is adjusted under the control of device 121；It has been can be set on first loop filter 123 for prolonging to each first
Slow unit 111 exports the first voltage output end of the first reference voltage, and its wave that can be used for stablizing the first reference voltage
It is dynamic, to adjust the first delay time of each first delay cell 111, to make the first postpones signal (1) to the first delay letter
Number (N1) with the first clock signal have consistent frequency and phase.
Second delay lock loop 200 may include the second delay chain 210, second voltage generation circuit 220 and tertiary voltage
Generation circuit 230.Wherein, the second delay chain 210 can be connect with clock signal input terminal 300, and may include mutually interconnecting
Second group of delay cell that is connecing and being located at its front and rear and third group delay cell, and can be configured as
Generated under the control of second voltage generation circuit 120 with corresponding second postpones signal of received second clock signal and
Third postpones signal.Second voltage generation circuit 220, which can be configured as, generates correspondence according to the received second clock signal of institute
The second reference voltage (corresponding to the V in Fig. 3ref2), the second reference voltage is provided to second group of delay cell, and according to
The third postpones signal of third group delay cell feedback adjusts the second reference voltage.Tertiary voltage generation circuit 230 can be matched
It is set to and provides third reference voltage (corresponding to the V in Fig. 3 to third group delay cellref3)。
Second group of delay cell may include identical and sequentially connected N2(N2It, can be with N for the positive integer greater than 11
It is identical or different, for example, it is 3) a second delay cell 211.This N2A second delay cell 211 also may each comprise
One input terminal, the second input terminal and postpones signal output end, and the second postpones signal (1) can be exported respectively and prolonged to second
Slow signal (N2).Wherein, this N2The first input end of a second delay cell 211 can be connected in parallel to second voltage generation
The second voltage output end of circuit 220 to receive the second reference voltage of the offer of second voltage generation circuit 120, and is located at
Second input terminal of first the second delay cell 211 of the starting point of the second delay chain 210 can connect to clock signal and produce
Generating apparatus 300, the N of the second input terminal of second the second delay cell 211 to the end for being located at the second delay chain 2102It is a
Second input terminal of the second delay cell 211 can be respectively connected to first the second delay cell 211 to N2- 1 second
The postpones signal output end of delay cell 211, and N2The postpones signal output end of a second delay cell 211 can connect
It is connected to the second input terminal of first third delay cell in third group delay cell.In addition, this N2A second delay cell
In 211 the second delay cell corresponding with the first delay cell 111 of the first postpones signal is output to the outside 211 (for example,
Second the second delay cell 211) postpones signal output end can be used for being output to the outside the second postpones signal, this second
Postpones signal is also possible to the second postpones signal (1) to the second postpones signal (N2) in any one.It should be noted that
Here the second delay cell 211 is corresponding with the first delay cell 111 can to refer to the two institute in the delay chain where respective
The position at place is identical, for example, all in the starting point of respective place delay chain, that is, is respectively the first of respectively place delay chain
A delay cell.
Second group of delay cell can be identical or different with first group of delay cell.Specifically, when the first reference voltage with
When second reference voltage is identical, second group of delay cell can be different from first group of delay cell；Or when the first reference voltage
When with the second reference voltage difference, second group of delay cell can be identical or different with first group of delay cell, so as to so that
It is different from the first delay time that first group of delay cell generates to obtain the second delay time that second group of delay cell generates.
In addition, the N in second group of delay cell2A second delay cell 211 may each be voltage-controlled delay unit or voltage-controlled
Inverting delay cells can also be made of one or more phase inverters, but the second all delay cell 211 can be with institute
The first delay cell 111 having is different.In addition, the second delay time of each second delay cell 211 is by second with reference to electricity
The control of pressure can be decreased or increased with the increase of the second reference voltage, and each second delay cell 211 is defeated
The second postpones signal out can be locked in second clock signal, that is, when the second delay lock loop 200 is locked, second prolongs
Slow signal (1) is to the second postpones signal (N2) there is consistent frequency and phase with second clock signal and keep stable.And
And when the second delay lock loop 200 is locked, the second delay time of each second delay cell 211 can be greater than should
The minimum delay time of second delay cell 211, but it is different from the first delay time of the first delay cell 111.
Third group delay cell may include sequentially connected N3(N3For positive integer, for example, 1) a third delay cell
212, third postpones signal (1) can be exported respectively to third postpones signal (N3), and any one postpones signal therein
It can be third postpones signal.Wherein, this N3The first input end of a third delay cell 212 can be connected in parallel to
Three voltage generation circuits 230, to receive third reference voltage from tertiary voltage generation circuit 230.Moreover, the delay of third group is single
The second input terminal and N of first third delay cell 212 in member2The postpones signal of a second delay cell 211 exports
End connection, the N positioned at the end of the second delay chain 2103The postpones signal output end and second of a third delay cell 212
The second feedback signal input terminal connection of voltage generation circuit 220 is to feed back third postpones signal (N to it3).It needs to illustrate
It is that the quantity of third delay cell 212 included in third group delay cell can be arranged as the case may be, although
It is not shown in the drawings, but it can only include a third delay cell 212.
This N3A third delay cell 212 is also possible to voltage-controlled delay unit or voltage-controlled inverting delay cells, can also be
It is made of one or more phase inverters, for example, can be buffer.In addition, this N3A third delay cell 212 can be identical,
It can also be different, for example, it may include different multiple third delay cells grouping, and multiple third delay cells are grouped
It can respectively include containing N31The first third delay cell grouping of a third delay cell contains N32A third delay is single
The second third delay cell grouping of member ... and contain N3nN-th of third delay cell of a third delay cell
Grouping.Wherein, these third delay cells are grouped included third delay cell difference, and N3=N31+N32+...N3n,
N is positive integer.
In addition, third delay cell 212 in third group delay cell can completely or partially with second group of delay cell
In the second delay cell 211 it is identical, for example, only N31A third delay cell 212 is identical as the second delay cell 211.
When the second delay lock loop 200 is locked, under the control of third reference voltage, each third delay cell
212 third delay time can be less than the first delay time of the first delay cell 111, and can be greater than or equal to
The minimum delay time of the third delay cell 212, specific size can control according to actual needs.When all
Three delay cells 212 it is all identical and for be made of multiple phase inverters buffer when, third delay time can satisfy
The following conditions:
Wherein, T3Indicate third delay time.
When the third delay cell 212 in third group delay cell is different, the third of different third delay cell 212
Delay time is different, they meet the following conditions:
T31*N31+T32*N32+K T3n*N3n<T1*|N1-N2|, wherein T31To T3nIt is single to respectively indicate first third delay
The third delay time that member grouping is grouped to n-th of third delay cell.
As shown in fig. 6, second voltage generation circuit 220 also may include sequentially connected second phase frequency detector (PFD)
221, the second charge pump (CP) 222 and the second loop filter (LF) 223.It wherein, can be on the second phase frequency detector 221
Clock signal input terminal connection, and can be set thereon and N3The postpones signal output end of a third delay cell 212
Second feedback signal input terminal of connection, and when it can be used for comparing through clock signal input terminal 300 received second
Clock signal and N3Third postpones signal (the N that a third delay cell 212 is fed back3) frequency and phase, and according to comparison
As a result it controls the second charge pump 222 and adjusts generated second reference voltage；Second charge pump 222 can be used in the second frequency discrimination
The second reference voltage is adjusted under the control of phase discriminator 221；It has been can be set on second loop filter 223 for each second
Delay cell 211 exports the second voltage output end of the second reference voltage, and it can be used for stablizing the second reference voltage
Fluctuation, to adjust the second delay time of each second delay cell 111, so that third postpones signal (1) to third be made to postpone
Signal (N3) with second clock signal have consistent frequency and phase.
Tertiary voltage generation circuit 230 may include fixed voltage generation circuit or adjustable voltage generation circuit.Wherein,
Fixed voltage generation circuit can be used for providing fixed third reference voltage to third group delay cell, may include this
The bias voltage feed end of delay circuit, as shown in Figure 7.Adjustable voltage generation circuit can be used for connecting 210 to the second delay
In third group delay cell adjustable third reference voltage is provided.
In the embodiment of the application, when in third group delay cell only comprising a third delay cell 212 or its
When the multiple third delay cells 212 for including are all the same, adjustable voltage generation circuit may include third delay lock loop
400, as shown in Figure 8.The third delay lock loop 400 can also be connect with clock signal input terminal 300, and also can wrap
Include the third delay chain 410 and the 4th voltage generation circuit 420 being made of the 4th group of delay cell.Wherein, third delay chain
410 can be configured as generated under the control of the 4th voltage generation circuit 420 with received third clock signal it is corresponding
4th postpones signal, and the 4th postpones signal is fed back to the 4th voltage generation circuit 420.4th voltage generation circuit 420 can
To be configured as generating corresponding third reference voltage according to the received third clock signal of institute, to third delay chain 410 and the
Third group delay cell in two delay chains 210 provides third reference voltage, and the fed back according to third delay chain 410
Four postpones signals adjust third reference voltage.
4th group of delay cell also may include sequentially connected N4(N4For the positive integer greater than 1, for example, 4) a 4th prolonging
Slow unit 411, and these the 4th delay cells 411 can be identical as third delay cell 212, these the 4th delay cells
411 can also export the 4th postpones signal (1) to the 4th postpones signal (N respectively4).N in 4th group of delay cell4A 4th
The N in third group delay cell in the first input end of delay cell 411 and the second delay chain 2103A third delay cell
212 first input end is all connected in parallel to the 4th voltage output end of the 4th voltage generation circuit 420, to produce from the 4th voltage
Raw circuit receives third reference voltage, and the 4th of the end positioned at third delay chain 410 in the 4th group of delay cell prolongs
The postpones signal output end of slow unit 411 is connect with the 4th feedback signal input terminal of the 4th voltage generation circuit 420.4th
Voltage generation circuit 420 also may include sequentially connected third phase frequency detector 421, third charge pump 422 and third loop
Filter 423.
About the detailed description of third delay chain 410, it is referred to above-mentioned to the first delay chain 110 or third delay chain
210 detailed description；About the detailed description of the 4th voltage generation circuit 420, it is referred to above-mentioned to first voltage generation electricity
The detailed description of road 120 or second voltage generation circuit 220, it is no longer superfluous herein to chat.
In another embodiment of the application, when in third group delay cell only comprising a third delay cell 212 or
It includes multiple third delay cells 212 it is all the same when, adjustable voltage generation circuit can also include sequentially connected the
Four delay lock loops 500 are to M delay lock loop 700, as shown in figure 9, M is the positive integer greater than 4.Preferably, voltage is adjusted
Generation circuit 242 can only include the 4th delay lock loop 500 and the 5th delay lock loop 700.4th delay lock loop 500
It can also be connect to M delay lock loop 700 with clock signal input terminal 300, it is corresponding with the received clock signal of institute to generate
Postpones signal.Moreover, the delay time of each of these delay lock loops delay lock loop is all by connected to it
The control of reference voltage caused by next delay lock loop.For example, the delay time of i-th of delay lock loop is by i-th
The control of reference voltage caused by+1 delay lock loop, wherein positive integer of the i between 4~M-1.
4th delay lock loop 500 to M-1 delay lock loop 600 may each comprise by sequentially connected two groups of delay lists
Member constitute delay chain (for example, 510 ... ..., 610,710) and for one group of delay cell into two groups of delay cells
The voltage generation circuit (for example, 520 ... ..., 620,720) of reference voltage is provided, another group in this two groups of delay cells is prolonged
The reference voltage of slow unit is provided by the voltage generation circuit in next delay lock loop connected to it.For example, the 4th prolongs
The reference voltage of another group of delay cell in slow locking ring can be mentioned by the voltage generation circuit in the 5th delay lock loop
For.M delay lock loop 700 may include the delay chain being made of one group of delay cell and be used for as this group of delay cell
And another group of delay cell in M-1 delay lock loop provides the voltage generation circuit of reference voltage.
In addition, every group of delay cell can include sequentially connected one or more delay cells (for example, 511,
512 ... ..., 611,612,711), and the delay cell in same group of delay cell can be identical, difference group delay cell
In delay cell can be different (for example, the quantity of delay cell and/or structure are different).In addition, being generated by the same voltage
The delay cell that circuit provides reference voltage can be identical.Reference voltage caused by each voltage generation circuit can phase
With or it is different, and can include sequentially connected phase frequency detector, charge pump and loop filter etc., but not limited to this.
In addition, for the 4th delay lock loop 500 to M-1 delay lock loop 600, it can be all or part of different,
It can also be all or part of identical.Moreover, two groups of delay cells in the same delay lock loop can be identical, it can also not
Together.
About the detailed description of the 4th delay lock loop 500 to M-1 delay lock loop 600, it is referred to above-mentioned to
The associated description of two delay lock loops 200, it is no longer superfluous herein to chat.M delay lock loop 700 can postpone to lock with above-mentioned third
It is identical to determine ring 400, about its detailed description, is referred to the above-mentioned associated description to third delay lock loop 400, herein
It is no longer superfluous to chat.
In addition, though be not shown in Fig. 9, but the reference of another group of delay cell 512 in the 4th delay lock loop
Voltage Vref5It can be provided by the voltage generation circuit in the 5th delay lock loop, the voltage in M-1 delay lock loop generates
Circuit 620 can provide reference voltage V to another group of delay cell in M-2 delay lock loopref(M-1)。
In another embodiment of the application, when the third group delay cell in the second delay chain 210 includes different more
When a third delay cell is grouped, adjustable voltage generation circuit may include that multiple third delay cell groupings are corresponding more
A delay lock loop (for example, 800 and 900), as shown in Figure 10.Each of the multiple delay lock loop can wrap
Include the delay chain (for example, 810 or 910) being made of one group of delay cell and for this group of delay cell and corresponding the
The grouping of three delay cells provides the voltage generation circuit (for example, 820 or 920) of third reference voltage.In addition, the voltage generates
The third reference voltage that circuit is supplied to each third delay cell grouping can be different, can also be identical.
Every group of delay cell in each delay lock loop also may include that identical and sequentially connected one or more is prolonged
Slow unit (for example, 811 or 911), and delay cell included by different delay lock loops or different group delay cells
Structure and/or quantity can be different.
About the detailed description of multiple delay lock loops, it is referred to the above-mentioned description to third delay lock loop 400,
This no longer goes to live in the household of one's in-laws on getting married and chats.
In another embodiment of the application, when the third group delay cell in the second delay chain 210 includes different more
When a third delay cell is grouped, adjustable voltage generation circuit may include corresponding with multiple third delay cell groupings
Multiple groups delay lock loop (for example, 850 and 950), as shown in figure 11.Every group of delay lock loop may each comprise sequentially connected
Multiple delay lock loops (for example, as shown in figure 12), and the delay of each of multiple delay lock loops delay lock loop
Control of the time by reference voltage caused by next delay lock loop connected to it.
About the detailed description of every group of delay lock loop, it is referred to above-mentioned to the 4th delay lock loop 500 to M delay
The associated description of locking ring 700, it is no longer superfluous herein to chat.
In the above-described embodiments, when all third delay cells included by the third group delay cell are all identical, second
Second delay time T of delay lock loop2It can be expressed as follows:When tertiary voltage generation circuit is solid
T when constant voltage generation circuit (for example, as shown in Figure 7), in above formula3For fixed value, for example, 2ns, so as to according to upper
Formula directly calculates the second delay time T2.When tertiary voltage generation circuit is adjustable voltage generation circuit (for example, such as Fig. 8
It is shown), the 4th delay lock loop to M-1 delay lock loop include (N2+ 1) a delay cell and only one delay
When control of the unit by the reference voltage of next delay lock loop, the second delay time T of the second delay lock loop2It can be with
It is expressed as follows:
T2=(TCLK2-T3)/N2=TCLK2*(1/N2/(-N2)M-2/N2+1/(N2+2))
When third group delay cell includes different multiple third delay cells groupings, the second of the second delay lock loop
Delay time T2It can be expressed as follows:Wherein, T31To T3nRespectively
The third delay time being grouped to n-th of third delay cell is grouped for first third delay cell.
In another embodiment of the application, as shown in figure 13, which can also include that the first multichannel is selected
Select device 1100 and/or the second multiple selector 1200.Wherein, the first multiple selector 1100 can be used for from the first delay lock
Determine in first group of delay cell of ring 100 selection and is output to the outside the first delay cell 111 of the first postpones signal (for example, the
One the first delay cell) and the first postpones signal that selected first delay cell 111 generates is output to outside；
Second multiple selector 1200 can be used for from second group of delay cell of the second delay lock loop 200 selecting to external defeated
The second delay cell 211 (for example, second second delay cell) of the second postpones signal and selected second is prolonged out
The second postpones signal that slow unit 211 generates is output to outside.First multiple selector 1100 and/or the second multiple selector
1200 can be independently arranged, and also can integrate in one.
In another embodiment of the application, as shown in figure 14, which can also include that clock signal produces
Raw circuit 1300 can be used as clock source and be prolonged by clock signal input terminal to the first delay lock loop 100 and second
Slow locking ring 200 provides the first clock signal and second clock signal, can also provide to other delay lock loops corresponding
Clock signal.The clock signal generating circuit 1300 can be set in the inside of delay circuit, also can be set on the outside.
It should be noted that the quantity of delay lock loop shown in the accompanying drawings and delay cell is only example, the deferred telegram
Road may include more or fewer delay lock loops, and each delay lock loop or every group of delay cell also may include
More or fewer delay cells.In addition, though the clock signal for being supplied to each delay lock loop is indicated with CLK in attached drawing,
But it can indicate different clock signals, herein and be not limited.
By above description as can be seen that the embodiment of the present application is by can be by by the delay in different delays locking ring
Unit is embodied as the delay time for having different, so as to reduce between the postpones signal that different delays locking ring is exported
Delay-time difference.In addition, the embodiment of the present application can the third group in different ways into the second delay lock loop prolong
Slow unit provides third reference voltage, this makes delay chain can satisfy different application demands, to increase its application
Range.In addition, this can neatly select the delay cell for exporting postpones signal outward by two multiple selector of setting,
So as to improve the ease of use of the delay circuit.
It may include deferred telegram described in above-described embodiment the embodiment of the present application also provides a kind of semiconductor device
Road.The semiconductor device herein and can also be not limited according to practical application and including other modules or unit.Example
It such as, can also include lead-lag detecting module when the semiconductor device is time-to-digit converter.
Device, circuit, unit that above-described embodiment illustrates etc., specifically can be by chip and/or entity (for example, discrete member
Part) it realizes, or realized by the product with certain function.For convenience of description, it describes to divide when apparatus above with function
It is described respectively for various units.Certainly, the function of each unit can be integrated in when implementing the embodiment of the present application it is same or
It is realized in multiple chips.
Although this application provides the component as described in above-described embodiment or attached drawing, based on routine or without creativeness
Labour in said device may include more or less component.Each embodiment in this specification, which is all made of, passs
Into mode describe, the same or similar parts between the embodiments can be referred to each other, and each embodiment stresses
It is differences from other embodiments.
Above-described embodiment be for convenient for those skilled in the art it will be appreciated that and being described using the application
's.Person skilled in the art obviously easily can make various modifications to these embodiments, and described herein
General Principle is applied in other embodiments without having to go through creative labor.Therefore, the application is not limited to above-mentioned implementation
Example, for those skilled in the art according to the announcement of the application, not departing from improvement that the application scope is made and modification all should be
Within the protection scope of the application.
Claims (18)
1. a kind of delay circuit, which is characterized in that the delay circuit includes:
First delay lock loop comprising the first delay connect with clock signal input terminal and comprising first group of delay cell
Chain, and first delay cell in first group of delay cell is configured as being output to the outside the first postpones signal；
And
Second delay lock loop comprising being connect with the clock signal input terminal and include second group of delay interconnected
Second delay chain of unit and third group delay cell, and postpone in second group of delay cell with output described first
Corresponding second delay cell of first delay cell of signal is configured as being output to the outside the second postpones signal,
Wherein, when the delay of first group of delay cell, second group of delay cell and the third group delay cell
Between it is different, and the delay time of first group of delay cell be greater than the third group delay cell delay time.
2. delay circuit according to claim 1, which is characterized in that
First delay lock loop further includes first voltage generation circuit, first voltage output end and first group of delay
The first input end of unit is connected in parallel, and its first feedback signal input terminal and being located in first group of delay cell
The postpones signal output end of first delay cell of the end of first delay chain connects；
Second delay lock loop further includes second voltage generation circuit and tertiary voltage generation circuit, wherein described second
The second voltage output end of voltage generation circuit and the first input end of second group of delay cell are connected in parallel, and its
The third of the end positioned at second delay chain in two feedback signal input terminals and the third group delay cell postpones single
The postpones signal output end connection of member；The tertiary voltage output end of the tertiary voltage generation circuit and third group delay are single
The first input end connection of member.
3. delay circuit according to claim 2, which is characterized in that
When the first voltage generation circuit is supplied to the first reference voltage and second electricity of first group of delay cell
Pressure generation circuit be supplied to second group of delay cell the second reference voltage it is identical when, first group of delay cell and institute
It is different to state second group of delay cell；Or
When first reference voltage and when the second reference voltage difference, first group of delay cell with described second group
Delay cell is identical or different.
4. delay circuit according to claim 3, which is characterized in that first group of delay cell and described second group prolong
It late include different voltage-controlled delay unit or voltage-controlled inverting delay cells, or including being connected with each other and different one or more
Phase inverter.
5. delay circuit according to claim 2, which is characterized in that
The first voltage generation circuit includes sequentially connected first phase frequency detector, the first charge pump and the first loop filtering
Device, wherein be provided on first phase frequency detector first feedback signal input terminal and with the clock signal input
End connection, and the first voltage output end is provided on first loop filter；
The second voltage generation circuit includes sequentially connected second phase frequency detector, the second charge pump and the second loop filtering
Device, wherein be provided on second phase frequency detector second feedback signal input terminal and with the clock signal input
End connection, and the second voltage output end is provided on second loop filter.
6. delay circuit according to claim 2, which is characterized in that the tertiary voltage generation circuit includes fixed voltage
Generation circuit or adjustable voltage generation circuit.
7. delay circuit according to claim 6, which is characterized in that the fixed voltage generation circuit includes the delay
The bias voltage feed end of circuit.
8. delay circuit according to claim 6, which is characterized in that when in the third group delay cell only include one
Third delay cell or it includes multiple third delay cells it is all the same when, the adjustable voltage generation circuit includes
Third delay lock loop, the third delay lock loop include the third delay chain being made of the 4th group of delay cell and the 4th electricity
Press generation circuit, and the first of the 4th voltage output end of the 4th voltage generation circuit and the 4th group of delay cell
Input terminal and the first input end of the third group delay cell are connected in parallel, and its 4th feedback signal input terminal with it is described
The postpones signal output end of 4th delay cell of the end positioned at the third delay chain in the 4th group of delay cell connects.
9. delay circuit according to claim 6, which is characterized in that when in the third group delay cell only include one
Third delay cell or it includes multiple third delay cells it is all the same when, the adjustable voltage generation circuit includes
Sequentially connected 4th delay lock loop is to M delay lock loop, and the 4th delay lock loop postpones to lock to the M
The delay time of each of ring delay lock loop is determined by ginseng caused by next delay lock loop connected to it
The control of voltage is examined, M is the positive integer greater than 4.
10. delay circuit according to claim 9, which is characterized in that the 4th delay lock loop to the M-1 prolongs
Slow locking ring includes the delay chain being made of sequentially connected two groups of delay cell and for two groups of delay cell
In one group of delay cell the voltage generation circuit of reference voltage, another group of delay cell in two groups of delay cell are provided
Reference voltage by next delay lock loop connected to it voltage generation circuit provide.
11. delay circuit according to claim 10, which is characterized in that the M delay lock loop includes being prolonged by one group
The delay chain and prolong for another group into one group of delay cell and the M-1 delay lock loop that slow unit is constituted
Slow unit provides the voltage generation circuit of reference voltage.
12. delay circuit described in 0 or 11 according to claim 1, which is characterized in that included by delay cell described in same group
Delay cell is identical, and delay cell included by the different group delay cells is different.
13. delay circuit described in 0 or 11 according to claim 1, which is characterized in that provide ginseng by the same voltage generation circuit
The delay cell for examining voltage is identical.
14. delay circuit according to claim 6, which is characterized in that when the third group delay cell includes different
When multiple third delay cells are grouped, the adjustable voltage generation circuit includes and multiple third delay cell groupings pair
The multiple delay lock loops answered, and each of multiple described delay lock loops include being made of one group of delay cell
Delay chain and for providing third reference voltage to one group of delay cell and the grouping of the corresponding third delay cell
Voltage generation circuit.
15. delay circuit according to claim 6, which is characterized in that when the third group delay cell includes different
When multiple third delay cells are grouped, the adjustable voltage generation circuit includes and multiple third delay cell groupings pair
The multiple groups delay lock loop answered, and delay lock loop described in every group includes sequentially connected multiple delay lock loops, and
The delay time of each of multiple delay lock loops delay lock loop is locked by next delay connected to it
Determine the control of reference voltage caused by ring.
16. delay circuit according to claim 1, which is characterized in that the delay circuit further include:
First multiple selector is configured as the selection from first group of delay cell and is output to the outside the first postpones signal
First delay cell and first postpones signal that selected first delay cell generates is output to
It is external；And/or
Second multiple selector is configured as the selection from second group of delay cell and is output to the outside the second postpones signal
Second delay cell and second postpones signal that selected second delay cell generates is output to
It is external.
17. delay circuit according to claim 1, which is characterized in that the delay circuit further include:
Clock signal generating circuit, by the clock signal input terminal respectively to first delay lock loop and described the
Two delay lock loops provide the first clock signal and second clock signal.
18. a kind of semiconductor device, which is characterized in that the semiconductor device includes described in any one of claim 1-17
Delay circuit.
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| CN201910415211.4A CN110086463A (en) | 2019-05-17 | 2019-05-17 | Delay circuit and semiconductor device including the delay circuit |
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