CN110069216B - Memory management method and device - Google Patents
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- CN110069216B CN110069216B CN201910279796.1A CN201910279796A CN110069216B CN 110069216 B CN110069216 B CN 110069216B CN 201910279796 A CN201910279796 A CN 201910279796A CN 110069216 B CN110069216 B CN 110069216B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0622—Securing storage systems in relation to access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0637—Permissions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application discloses a management method and device of a memory. The method comprises the following steps: judging whether a lock register of Flash is in an unlocking state or not; and after the lock register is judged to be in the unlocking state, judging whether the erasing operation of the Flash is allowed to be started or not according to the operation request information of erasing the Flash.
Description
Technical Field
The present application relates to the field of information processing, and more particularly, to a method and apparatus for managing a memory.
Background
Flash (Flash Memory) is a Non-Volatile (Non-Volatile) Memory. The physical characteristics of the flash memory are fundamentally different from those of a common memory; the common memory belongs to a volatile memory, and data in the memory cannot be maintained as long as the current supply is stopped, so that the data needs to be reloaded into the memory every time the power is re-turned on; flash can hold data for a long time without current supply, and the storage characteristic of Flash is equivalent to a hard disk, and the characteristic is the basis of Flash memory which becomes a storage medium of various portable digital devices.
A SOC (System on Chip) is an integrated circuit with a dedicated target that contains the complete System and has the full contents of embedded software. The method is the chip integration of the core of an information system, and integrates key components of the system on one chip.
With the evolution of technology, Flash has become the main embedded memory in SOC. In practical applications, data stored in Flash may be wrongly rewritten for various reasons, thereby affecting the security of the data stored in Flash.
Disclosure of Invention
In order to solve the technical problem, embodiments of the present application provide a method and an apparatus for managing a memory, which can improve the security of data storage in Flash.
To achieve the purpose of the present application, an embodiment of the present application provides a method for managing a memory, including:
judging whether a lock register of Flash is in an unlocking state or not;
and after the lock register is judged to be in the unlocking state, judging whether to allow the erasing operation of the Flash to be started or not according to the operation request information of the erasing Flash.
In an exemplary embodiment, the determining whether the lock register of Flash is in the unlocked state includes:
after detecting that a first lock register of Flash is in an unlocking state, acquiring a locking state of a second lock register newly added to the Flash;
and when the locking state of the second lock register is unlocking, determining that the lock register of the Flash is in an unlocking state.
In an exemplary embodiment, determining whether to allow starting of an erasing operation on a Flash according to operation request information for erasing the Flash includes:
detecting whether management information for performing erasing operation on Flash is received or not, wherein the management information comprises a target address to be operated;
and if the management information is received, determining that an operation request for erasing the Flash is received.
In an exemplary embodiment, after determining that the operation request for erasing Flash is received, the method further includes:
judging whether the operation request has the operation authority on the target address or not according to the operation authority of each address in the prestored Flash;
and if the judgment result shows that the target address has the operation authority, the erasing operation of the Flash is allowed to be started.
In an exemplary embodiment, the determining whether the operation request has an operation right to the target address includes:
judging whether the target address to be operated is in a storage area of an on-Chip Operating System (COS) of a system level chip (SOC);
and if the target address to be operated is in the storage area, determining that the operation request has no operation authority on the target address.
In an exemplary embodiment, after determining whether to allow the Flash operation to be started according to the Flash erasing operation request information, the method further includes:
when a target address to be operated is sent to Flash, judging whether an address latch signal corresponding to the target address is effective or not;
and if the address latch signal is effective, controlling to execute the erasing operation of the Flash.
In one exemplary embodiment, the method further comprises:
and judging whether the first lock register and the newly added second lock register in the Flash are both in an unlocking state, and allowing the corresponding operation to be executed when the judgment result is that the first lock register and the newly added second lock register are both in the unlocking state.
In an exemplary embodiment, the default address to be operated in the Flash erase/write operation is an invalid address or a last page.
In one exemplary embodiment, the method further comprises:
before the system of the software stored in the Flash is reset, judging whether COS data stored in the Flash accord with a preset correctness judgment strategy or not;
and if the COS data conforms to the correctness judgment strategy, allowing the system resetting operation of releasing the software to be executed.
In an exemplary embodiment, the determining whether the COS data stored in Flash conforms to a preset correctness determination policy includes:
dividing the content of COS data according to pages by taking a preset data size as a detection unit to obtain n detection data blocks, wherein n is a positive integer;
selecting one or at least two words from each detection data block as target detection content;
and judging whether the target detection content meets a preset correctness judgment strategy.
In one exemplary embodiment, the method further comprises:
and outputting an alarm prompt when the Flash is detected to have a safety risk.
To achieve the above object, an embodiment of the present application provides a management apparatus for a memory, including a processor and a memory, where the memory stores a computer program, and the processor calls the computer program stored in the memory to implement any one of the above methods.
According to the technical scheme provided by the embodiment of the application, whether the lock register of the Flash is in an unlocked state or not is judged, after the lock register is judged to be in the unlocked state, whether the erasing operation of the Flash is allowed to be started or not is judged according to the operation request information for erasing the Flash, the erasing operation of the Flash is allowed to be started or not is judged sequentially through the lock register and the operation request information, the purpose of managing the erasing of the Flash in a process checking mode is achieved, and through a simple method for checking an entry line in the related technology, the erasing operation of the Flash is managed more finely, the occurrence of error in rewriting of the Flash is reduced, and the safety of data stored in the Flash is improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the subject matter and together with the description serve to explain the principles of the subject matter and not to limit the subject matter.
Fig. 1 is a flowchart of a method for managing a memory according to an embodiment of the present disclosure;
fig. 2 is a flowchart of another memory management method according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Fig. 1 is a flowchart of a method for managing a memory according to an embodiment of the present disclosure. The method shown in fig. 1 comprises:
latches are used to store data for exchange, allowing the data to settle and remain unchanged for a period of time until it is replaced by new data.
In an exemplary embodiment, the determining whether the lock register of Flash is in the unlocked state includes:
after detecting that a first lock register of Flash is in an unlocking state, acquiring a locking state of a newly added second lock register of the Flash;
and when the locking state of the second lock register is unlocking, determining that the lock register of the Flash is in the unlocking state.
In the exemplary embodiment, a lock register is newly added in Flash, and after a first lock register of the Flash is in an unlocked state, whether a second lock register which is newly added is in an unlocked state is judged; when both are in an unlocking state, determining that the Flash allows erasing operation on the Flash configuration; otherwise, an alarm is generated. Whether the Flash configuration is allowed to be erased or written is further determined through the newly-added lock register, and the occurrence probability of misjudgment is reduced.
And 102, after the lock register is judged to be in the unlocking state, judging whether the erasing operation of the Flash is allowed to be started or not according to the operation request information of the erasing Flash.
After the Flash configuration is allowed to be erased and written, the erasing and writing of the Flash can be managed according to the operation request information of erasing and writing the Flash, and the safety of erasing and writing management is improved.
In an exemplary embodiment, determining whether to allow starting of an erasing operation on a Flash according to operation request information for erasing the Flash includes:
detecting whether management information for performing erasing operation on Flash is received or not, wherein the management information comprises a target address to be operated;
and if the management information is received, determining that an operation request for erasing the Flash is received.
In the exemplary embodiment, whether an external request for performing an erasing operation on Flash is determined by determining whether management information of a corresponding erasing operation is received, and when the management information is received, it is determined that the erasing request is received, otherwise, an alarm is generated. Based on the judgment, the Flash is subjected to erasable configuration management, and the probability of occurrence of error erasing is reduced.
The method provided by the embodiment of the application judges whether a lock register of Flash is in an unlocked state, judges whether to allow the starting of the erasing operation on the Flash according to the operation request information for erasing the Flash after judging that the lock register is in the unlocked state, and judges sequentially through the lock register and the operation request information, thereby realizing the purpose of controlling whether to allow the starting of the erasing operation on the Flash, achieving the purpose of managing the erasing of the Flash by using a process check mode, managing the erasing operation of the Flash more finely by using a simple method for entry line check in the related art, reducing the occurrence of mistaken rewriting of the Flash, and improving the safety of data stored in the Flash.
The methods provided in the examples of the present application are further illustrated below:
in an exemplary embodiment, after determining that the operation request for erasing Flash is received, the method further includes:
judging whether the operation request has the operation authority on the target address or not according to the operation authority of each address in the prestored Flash;
and if the judgment result shows that the target address has the operation authority, the erasing operation of the Flash is allowed to be started.
In the exemplary embodiment, the inventor finds that Flash is used as a storage medium, and an internal partial storage area is configured to store specific data in advance, and once the specific data is rewritten, the normal operation of the relevant chip is affected.
After receiving an operation request for writing Flash, the operation supported by the target address in Flash, namely the operation authority, is obtained by calling the target address of the operation required by the operation request, and the operation request is responded according to the permission of the operation request, so that the occurrence of Flash misoperation is effectively reduced.
In an exemplary embodiment, the determining whether the operation request has an operation permission for the target address includes:
judging whether the target address to be operated is in a storage area of a Chip Operating System (COS) of a System On Chip (SOC);
and if the target address to be operated is in the storage area, determining that the operation request has no operation authority on the target address.
In the exemplary embodiment, the COS data in the Flash-based SOC system is read from the outside and then stored in the Flash, and after the COS data is downloaded, the COS data is stored in a preset storage area, and by setting corresponding authority control, it can be ensured that the erasing operation hitting the COS area is ignored and an alarm is generated, thereby preventing the COS data from being erased by mistake.
In an exemplary embodiment, after determining whether to allow the Flash operation to be started according to the Flash erasing operation request information, the method further includes:
when a target address to be operated is sent to Flash, judging whether an address latch signal corresponding to the target address is effective or not;
and if the address latch signal is effective, controlling to execute the erasing operation of the Flash.
In the exemplary embodiment, when the target address is transferred to Flash according to the Flash time sequence, the effectiveness of the erasing operation is judged again by using the address latch signal which is the same as that of the Flash, if the erasing operation is effective, the control signal for executing the erasing of the Flash is controlled, and the Flash erasing is carried out; otherwise, an alarm is generated.
By judging the validity of the address latching signal, whether the address can be erased or not can be judged, so that whether the address can execute Flash erasing operation or not can be obtained, the purpose of judging whether the erasing operation can be executed or not is achieved, the occurrence of mistaken erasing is reduced, and the safety of data storage in Flash is improved.
In one exemplary embodiment, the method further comprises:
and judging whether the first lock register and the newly added second lock register in the Flash are both in an unlocking state, and allowing the corresponding operation to be executed when the judgment result is that the first lock register and the newly added second lock register are both in the unlocking state.
In the present exemplary embodiment, in the course of performing at least one operation, the steps of the above exemplary embodiment are performed, including:
A. detecting whether management information for performing erasing operation on Flash is received or not, wherein the management information comprises a target address to be operated;
B. judging whether the operation request has the operation authority on the target address or not according to the operation authority of each address in the prestored Flash;
C. when a target address to be operated is sent to Flash, whether an address latch signal corresponding to the target address is effective or not is judged.
The above-mentioned A is implemented by software, B and C operations are implemented by hardware, and the judgment precision can be improved and the occurrence of Flash error rewriting can be reduced by combining the judgment of the hardware mode of locking the register.
In an exemplary embodiment, the address to be operated in the Flash erasing operation is an invalid address or the last page by default, so that the address of the page 0 (usually, the page 0 contains valid information) is prevented from being wrongly rewritten.
In one exemplary embodiment, the method further comprises:
before the system of software stored in the Flash is reset by the Flash, judging whether COS data stored in the Flash accords with a preset correctness judgment strategy or not;
and if the COS data conforms to the correctness judgment strategy, allowing the system resetting operation of releasing the software to be executed.
In an exemplary embodiment, after the SOC chip is powered on, the SOC chip, except for loading necessary hardware initialization information, performs a check on COS data in Flash before the system reset for releasing software, so as to ensure the correctness of COS, ensure the normal operation of the SOC chip, and improve the security of data.
In an exemplary embodiment, the determining whether the COS data stored in Flash conforms to a preset correctness determination policy includes:
dividing the content of COS data according to pages by taking a preset data size as a detection unit to obtain n detection data blocks, wherein n is a positive integer;
selecting one or at least two bytes from each detection data block as target detection content;
and judging whether the target detection content meets a preset correctness judgment strategy.
In the present exemplary embodiment, the inventors found that, since the COS data is different in size, the time overhead required to perform the inspection operation is also different, and it takes a long time to perform the data inspection for data of how large the storage amount of the COS data is. Therefore, one or a few bytes in the COS are checked page by page to execute data check operation, such as CRC calculation, and the like, the check result is compared with a pre-stored reference result, if the check result is correct, the COS is safe, and otherwise, an alarm reset system is generated.
In one exemplary embodiment, the method further comprises:
and outputting an alarm prompt when the Flash is detected to have a safety risk.
In the exemplary embodiment, when the detection and/or determination steps are executed and the obtained result is that the preset condition is not met, the security risk of the Flash storage is determined, and an alarm prompt is sent out in time.
Fig. 2 is a flowchart of another memory management method according to an embodiment of the present disclosure. The method shown in fig. 2 comprises:
step 01, configuring a LOCK1 register to be in an unlocking state;
step 02, configuring a LOCK2 register to be in an unlocked state;
step 03, judging whether the LOCK1 and LOCK2 registers are both in an unlocked state;
if yes, executing step 04, otherwise, outputting an alarm signal.
Step 04, configuring the erasing operation register in a working state;
through steps 01 to 04, before Flash erasing, unlocking registers LOCK1 and LOCK2 are configured; after both LOCK1 and LOCK2 are correct, the erase operation register can be configured;
step 05, judging whether the LOCK1 and LOCK2 registers are both in an unlocked state; detecting whether an address and/or data to be operated in the Flash is received or not;
when the operation type is write operation, the received information is written address and data; if the operation type is an erasing operation, the received information is an address to be erased;
if the LOCK1 and LOCK2 registers are both in an unlocked state and the address and/or data to be operated is received, then step 06 is performed; otherwise, outputting an alarm signal.
Step 06, configuring the erasing confirmation register to be in a working state;
if yes, go to step 06, otherwise, output alarm signal.
Giving out addresses and data to be operated through erasing \ writing operation through the steps 05 and 06, and then setting up an erasing confirmation register;
step 07, judging whether the LOCK1 and LOCK2 registers are both in an unlocked state; judging whether the address to be operated has an operation authority or not;
when the LOCK1 and the LOCK2 registers are both in an unlocked state and the address to be operated has an operation right, executing step 08; otherwise, outputting an alarm signal.
Step 08, configuring the erasing start register to be in a working state;
through steps 07 and 08, the trigger condition for erasing and writing Flash can be determined through the judgment.
Step 09, judging whether the LOCK1 and LOCK2 registers are both in an unlocked state; judging whether the address to be operated has an operation authority or not; judging whether the address latch signal of the Flash is effective or not;
if the registers of LOCK1 and LOCK2 are both in an unlocked state, the address to be operated has operation authority, and the address latching signal of Flash is effective, the Flash is allowed to be erased and written, otherwise, an alarm signal is output.
After the erasing state controlled by the system is started, the address to be operated is transmitted to Flash according to the Flash time sequence, meanwhile, the effectiveness of the erasing operation is judged by using the address latching signal which is the same as the Flash, and when the address latching signal is effective, a control signal for controlling the erasing of the Flash is set, so that the erasing of the Flash is allowed.
According to the method provided by the embodiment of the application, before Flash erasing, the registers LOCK1 and LOCK2 are unlocked, and the erasing registers can be configured only after the registers LOCK1 and LOCK2 are correct; then the software gives out the address and data to be operated through erasing/writing operation, and then sets up the confirmation erasing register; meanwhile, the system can always judge the effectiveness of the registers and the authority of the address to be operated, only when the effectiveness and the authority are correct, the system can start the erasing operation of the Flash, otherwise, an alarm is generated and the erasing operation is not carried out; the erasing state controlled by the system is started, when the address is transmitted to Flash according to the Flash time sequence, the validity of the operation is judged again by using the same latching address signal as the Flash, and only if the operation is valid, the control signal for controlling the erasing of the Flash can be really set up to erase the Flash; otherwise, generating an alarm and not erasing and writing; based on the management mode, the purpose of preventing Flash from being rewritten by mistake by adopting a process inspection method is realized through the cooperation of software and hardware, and the safety of data storage in Flash is improved.
The management device of the memory provided by the embodiment of the application comprises a processor and a memory, wherein the memory stores a computer program, and the processor calls the computer program stored in the memory to realize the following steps:
judging whether a lock register of Flash is in an unlocking state or not;
and after the lock register is judged to be in the unlocking state, judging whether the erasing operation of the Flash is allowed to be started or not according to the operation request information of erasing the Flash.
In an exemplary embodiment, the step of the processor calling the computer program stored in the memory to determine whether the lock register of Flash is in an unlocked state includes:
after detecting that a first lock register of Flash is in an unlocking state, acquiring a locking state of a second lock register newly added to the Flash;
and when the locking state of the second lock register is unlocking, determining that the lock register of the Flash is in the unlocking state.
In an exemplary embodiment, the step of the processor calling the computer program stored in the memory to determine whether to allow the Flash operation of the Flash to be started according to the operation request information for erasing the Flash includes:
detecting whether management information for performing erasing operation on Flash is received or not, wherein the management information comprises a target address to be operated;
and if the management information is received, determining that an operation request for erasing the Flash is received.
In an exemplary embodiment, after the step of calling the computer program stored in the memory by the processor to realize that the operation request for erasing Flash is received, the step of calling the computer program stored in the memory by the processor further realizes the following steps comprising:
judging whether the operation request has the operation authority on the target address or not according to the operation authority of each address in the prestored Flash;
and if the judgment result shows that the target address has the operation authority, the erasing operation of the Flash is allowed to be started.
In an exemplary embodiment, the processor calls a computer program stored in the memory to implement the step of determining whether the operation request has an operation right to the target address, including:
judging whether the target address to be operated is in a storage area of an on-Chip Operating System (COS) of a system level chip (SOC);
and if the target address to be operated is in the storage area, determining that the operation request has no operation authority on the target address.
In an exemplary embodiment, after the processor calls the computer program stored in the memory to determine whether to allow the Flash operation to be started according to the Flash erasing operation request information, the processor calls the computer program stored in the memory to further implement the following steps, including:
when a target address to be operated is sent to Flash, judging whether an address latch signal corresponding to the target address is effective or not;
and if the address latch signal is effective, controlling to execute the erasing operation of the Flash.
In an exemplary embodiment, the processor invoking the computer program stored in the memory further implements steps comprising:
and judging whether the first lock register and the newly added second lock register in the Flash are both in an unlocking state, and allowing the corresponding operation to be executed when the judgment result is that the first lock register and the newly added second lock register are both in the unlocking state.
In an exemplary embodiment, before the processor calls the computer program stored in the memory to implement the step of determining whether the lock register of Flash is in the unlocked state, the processor calls the computer program stored in the memory to further implement the following steps, including:
the default of the address to be operated in Flash erasing operation is an invalid address or the last page, so that the error rewriting of the address of the page 0 (usually, the page 0 contains valid information) is avoided.
In an exemplary embodiment, the processor invoking the computer program stored in the memory further implements steps comprising:
before the system of the software stored in the Flash is reset, judging whether COS data stored in the Flash accord with a preset correctness judgment strategy or not;
and if the COS data conform to the correctness judgment strategy, allowing the system reset operation of releasing the software to be executed.
In an exemplary embodiment, the step of calling a computer program stored in the memory by the processor to determine whether the COS data stored in Flash conforms to a preset correctness determination policy includes:
dividing COS data by pages by taking a preset data amount as a detection unit to obtain n detection data blocks;
selecting one or at least two bytes from each detection data block as target detection content;
and judging whether the target detection content meets a preset correctness judgment strategy or not.
In an exemplary embodiment, the processor invoking the computer program stored in the memory further implements steps comprising:
and outputting an alarm prompt when the Flash is detected to have a safety risk.
The device embodiment provided by the application embodiment judges whether a lock register of Flash is in an unlocked state, judges whether to allow starting of erasing operation on the Flash according to operation request information for erasing the Flash after judging that the lock register is in the unlocked state, and judges through the lock register and the operation request information in sequence to realize the purpose of controlling whether to allow starting of erasing operation on the Flash, thereby achieving the purpose of managing erasing of the Flash by using a procedural check mode.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (10)
1. A method for managing memory, comprising:
judging whether a lock register of Flash is in an unlocking state or not;
after the lock register is judged to be in the unlocking state, judging whether the erasing operation of the Flash is allowed to be started or not according to the operation request information of erasing the Flash;
before the system of software stored in the Flash is reset by releasing the Flash, judging whether COS data stored in the Flash accords with a preset correctness judgment strategy or not;
if the COS data accords with the correctness judgment strategy, the system reset operation of releasing the software is allowed to be executed;
the judging whether COS data stored in the Flash accords with a preset correctness judging strategy comprises the following steps:
dividing the content of COS data according to pages by taking a preset data size as a detection unit to obtain n detection data blocks, wherein n is a positive integer;
selecting one or at least two words from each detection data block as target detection content;
and judging whether the target detection content meets a preset correctness judgment strategy.
2. The method according to claim 1, wherein the determining whether the lock register of Flash is in an unlocked state comprises:
after detecting that a first lock register of Flash is in an unlocking state, acquiring a locking state of a second lock register newly added to the Flash;
and when the locking state of the second lock register is unlocking, determining that the lock register of the Flash is in the unlocking state.
3. The method of claim 1, wherein determining whether to allow the Flash operation of Flash to be started according to the Flash erasing operation request information comprises:
detecting whether management information for performing erasing operation on Flash is received or not, wherein the management information comprises a target address to be operated;
and if the management information is received, determining that an operation request for erasing the Flash is received.
4. The method of claim 3, wherein after determining that the Flash erase operation request is received, the method further comprises:
judging whether the operation request has the operation authority on the target address or not according to the operation authority of each address in the prestored Flash;
and if the judgment result shows that the target address has the operation authority, the erasing operation of the Flash is allowed to be started.
5. The method of claim 4, wherein the determining whether the operation request has an operation right for the target address comprises:
judging whether the target address to be operated is in a storage area of an on-Chip Operating System (COS) of a system level chip (SOC);
and if the target address to be operated is in the storage area, determining that the operation request has no operation authority on the target address.
6. The method according to claim 1, wherein after determining whether to allow the Flash operation of the Flash to be started according to the operation request information for erasing the Flash, the method further comprises:
when a target address to be operated is sent to Flash, judging whether an address latch signal corresponding to the target address is effective or not;
and if the address latch signal is effective, controlling to execute the erasing operation of the Flash.
7. The method of any of claims 3 to 6, further comprising:
and judging whether the first lock register and the newly added second lock register in the Flash are both in an unlocking state, and allowing the corresponding operation to be executed when the judgment result is that the first lock register and the newly added second lock register are both in the unlocking state.
8. The method of claim 1, wherein the default address to be operated in the Flash erase/write operation is an invalid address or a last page.
9. The method of claim 1, further comprising:
and outputting an alarm prompt when the Flash is detected to have a safety risk.
10. An apparatus for managing a memory, comprising a processor and a memory, the memory storing a computer program, the processor calling the computer program stored in the memory to implement the method according to any one of claims 1 to 9.
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| CN105718208A (en) * | 2014-12-04 | 2016-06-29 | 中国科学院微电子研究所 | Flash program memory protection design method and hardware implementation device |
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