CN110047941A - The manufacturing method and array substrate of array substrate - Google Patents
The manufacturing method and array substrate of array substrate Download PDFInfo
- Publication number
- CN110047941A CN110047941A CN201910267618.7A CN201910267618A CN110047941A CN 110047941 A CN110047941 A CN 110047941A CN 201910267618 A CN201910267618 A CN 201910267618A CN 110047941 A CN110047941 A CN 110047941A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- insulating layer
- array substrate
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 117
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000002243 precursor Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000020 Nitrocellulose Substances 0.000 claims abstract description 15
- 229920001220 nitrocellulos Polymers 0.000 claims abstract description 15
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 30
- 235000019441 ethanol Nutrition 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000004090 dissolution Methods 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 11
- 239000001301 oxygen Substances 0.000 description 11
- 229910052760 oxygen Inorganic materials 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 229910010272 inorganic material Inorganic materials 0.000 description 6
- 239000011147 inorganic material Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000007717 exclusion Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 239000004926 polymethyl methacrylate Substances 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Polymers C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000012046 mixed solvent Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229920005573 silicon-containing polymer Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the present application discloses the manufacturing method and array substrate of a kind of array substrate；Wherein, the manufacturing method of the array substrate includes: to provide a substrate, and the substrate includes substrate layer and the grid layer being set in turn on the substrate layer, the first insulating layer, semiconductor layer and source-drain electrode layer；A precursor solution is provided, the precursor solution includes nitrocellulose；The precursor solution is coated on the source-drain electrode layer, second insulating layer is formed；Photoresist layer is set on the second insulating layer, development is exposed to form first through hole on the photoresist layer with second insulating layer described in expose portion to the photoresist layer；The second insulating layer for using etching solution etching to be exposed is to form the second through-hole in the second insulating layer with expose portion source-drain electrode layer.The stability of array substrate can be improved in this programme.
Description
Technical field
This application involves field of display technology more particularly to the manufacturing methods and array substrate of a kind of array substrate.
Background technique
With the development of display technology, liquid crystal display panel (Liquid Crystal Display, LCD) because its is light,
The advantages that Low emissivity, is more and more welcomed by the people.
Liquid crystal display panel generally includes array substrate, in the array substrate, as the switch member for opening/closing pixel
Part, i.e. thin film transistor (TFT) (Thin Film Transistor, TFT) are formed in each pixel.And carry on the back channel-etch type film
Transistor is widely used due to the advantages that exposure mask (Mask) quantity is few, small in size.Wherein, channel etch type film crystal is carried on the back
Passivation protection layer on pipe can play the role of exclusion of water and oxygen enters back channel, to prevent the resistance value of back channel from becoming
Change, and causes threshold voltage that huge drift occurs.
Current passivation protection layer material is mainly with SiO2, Al2O3, Y2O3Etc. based on inorganic material, inorganic material is mostly
High temperature process is not suitable for flexible base board；And the most bendability of inorganic material is poor, frangible, leads to the stability of thin film transistor (TFT)
It is poor, and then influence the stability of array substrate.
Summary of the invention
The embodiment of the present application provides the manufacturing method and array substrate of a kind of array substrate, and array substrate can be improved
Stability.
The embodiment of the present application provides a kind of manufacturing method of array substrate, comprising:
A substrate is provided, the substrate includes substrate layer and the grid layer being set in turn on the substrate layer, first
Insulating layer, semiconductor layer and source-drain electrode layer；
A precursor solution is provided, the precursor solution includes nitrocellulose；
The precursor solution is coated on the source-drain electrode layer, second insulating layer is formed；
Photoresist layer is set on the second insulating layer, development is exposed on the photoresist layer to the photoresist layer
First through hole is formed with second insulating layer described in expose portion；
The second insulating layer for using etching solution etching to be exposed is to form the second through-hole in the second insulating layer
With expose portion source-drain electrode layer.
In the manufacturing method of array substrate provided by the embodiments of the present application, one substrate of the offer, the substrate includes
Substrate layer and the grid layer being set in turn on the substrate layer, the first insulating layer, semiconductor layer and source-drain electrode layer, comprising:
A substrate is provided, the substrate includes substrate layer；
The depositing layers on the substrate layer；
The first insulating layer is deposited on the grid layer；
Deposited semiconductor layer on the first insulating layer；
The depositing second metal layer on the semiconductor layer, and the second metal layer is carried out using back channel etching method
Etching forms source-drain electrode layer.
In the manufacturing method of array substrate provided by the embodiments of the present application, the precursor solution further includes ethyl alcohol.
In the manufacturing method of array substrate provided by the embodiments of the present application, the precursor solution be by the ethyl alcohol and
The collodion is formed according to preset ratio mixed dissolution.
In the manufacturing method of array substrate provided by the embodiments of the present application, the precursor solution be by the ethyl alcohol and
The collodion is formed according to volume ratio 3:7 to 4:6 mixed dissolution.
It is described that the precursor solution is coated on institute in the manufacturing method of array substrate provided by the embodiments of the present application
It states on source-drain electrode layer, forms second insulating layer, comprising:
The precursor solution is coated on the source-drain electrode layer, a film is formed；
The film is toasted, forms second insulating layer to solidify the film, wherein baking temperature is taken the photograph 110
Family name's degree is between 150 degrees Celsius, toasting duration between 1 hour to 2 hours.
In the manufacturing method of array substrate provided by the embodiments of the present application, the second insulating layer is by nitrocellulose structure
At.
In the manufacturing method of array substrate provided by the embodiments of the present application, the etching solution includes ethyl alcohol.
In the manufacturing method of array substrate provided by the embodiments of the present application, the concentration of the ethyl alcohol is more than or equal to 95%.
The embodiment of the present application provides a kind of array substrate, comprising: substrate layer, grid layer, the first insulating layer, semiconductor
Layer, source-drain electrode layer, second insulating layer and photoresist layer；Wherein:
The grid layer is arranged on the substrate layer；
First insulating layer is covered on the grid layer and the substrate；
The semiconductor layer setting is on the first insulating layer；
The source-drain electrode layer is located on first insulating layer and semiconductor layer；
The second insulating layer is covered on the source-drain electrode layer；
The photoresist layer setting is on the second insulating layer；
Wherein, the second insulating layer is made of nitrocellulose.
The manufacturing method of array substrate provided by the embodiments of the present application includes providing a substrate, and the substrate includes substrate layer
And it is set in turn in grid layer, the first insulating layer, semiconductor layer and source-drain electrode layer on the substrate layer；One presoma is provided
Solution, the precursor solution include nitrocellulose；The precursor solution is coated on the source-drain electrode layer, forms second
Insulating layer；Photoresist layer is set on the second insulating layer, development is exposed on the photoresist layer to the photoresist layer
First through hole is formed with second insulating layer described in expose portion；Use the etching solution second insulating layer that is exposed of etching with
The second through-hole is formed in the second insulating layer with expose portion source-drain electrode layer.Second insulating layer in this programme is by nitrocellulose
It constitutes, water and oxygen can effectively be isolated, avoid water and oxygen from entering semiconductor layer and the resistance value of semiconductor layer is become
Change, and cause threshold voltage that huge drift occurs, influences the stability of array substrate.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those skilled in the art, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow diagram of the manufacturing method of array substrate provided by the embodiments of the present application.
Fig. 2 is the first structure diagram of array substrate provided by the embodiments of the present application.
Fig. 3 is the second structural schematic diagram of array substrate provided by the embodiments of the present application.
Fig. 4 is the third structural schematic diagram of array substrate provided by the embodiments of the present application.
Fig. 5 is the 4th structural schematic diagram of array substrate provided by the embodiments of the present application.
Fig. 6 is the 5th structural schematic diagram of array substrate provided by the embodiments of the present application.
Fig. 7 is the 6th structural schematic diagram of array substrate provided by the embodiments of the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description.Obviously, described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, those skilled in the art's every other implementation obtained without creative efforts
Example, shall fall in the protection scope of this application.
It should be noted that the manufacturing method of array substrate provided by the embodiments of the present application is the manufacturing process of array substrate
In a part, about the manufacturing method of array substrate other parts, such as the isostructural system of grid line, pixel electrode, data line
Method is made, is not the emphasis of the application concern, therefore not described in detail herein.
Wherein, back channel-etch type thin film transistor because Mask quantity is few, the advantages that small in size due to be widely used,
In, the passivation protection layer on back channel etch type thin film transistor (TFT) can play the role of exclusion of water and oxygen enters back channel,
To prevent the resistance value of back channel from changing, and cause threshold voltage that huge drift occurs.
And most passivation protection layer material is mainly with SiO at present2, Al2O3, Y2O3Etc. based on inorganic material, inorganic material is big
Mostly high temperature process is not suitable for flexible base board；And the most bendability of inorganic material is poor, frangible, leads to the steady of thin film transistor (TFT)
It is qualitative poor, and then influence the stability of array substrate.
Currently, existing such as dimethyl silicone polymer (polydimethylsiloxane, PDMS), poly-methyl methacrylate
The organic materials such as ester (poly methyl methacrylate, PMMA) are the passivation protection layer material of representative, but because of its material
The permeability of itself, the effect that water and oxygen is isolated are poor.
In this regard, the embodiment of the present application provides the manufacturing method and array substrate of a kind of array substrate, in detail below
Explanation.
Referring to Fig. 1, Fig. 1 is the flow diagram of the manufacturing method of array substrate provided by the embodiments of the present application, specifically
Process can be such that
101, a substrate is provided, the substrate include substrate layer and the grid layer being set in turn on the substrate layer,
First insulating layer, semiconductor layer and source-drain electrode layer.
Wherein, the material of substrate may include glass, quartz, sapphire or tin indium oxide etc., it should be noted that substrate
Material include but is not limited to the above material, can also include other materials.The substrate may include substrate layer.
Specifically, can on substrate layer depositing layers；The first insulating layer is deposited on the grid layer；Described
Deposited semiconductor layer on one insulating layer；The depositing second metal layer on the semiconductor layer, and using back channel etching method to institute
It states second metal layer to perform etching, forms source-drain electrode layer.
In some embodiments, referring to Fig. 2, can be by physical gas phase deposition technology, for example metal sputtering is in substrate
The first metal layer is deposited on layer 10, photoetching treatment then is carried out to the metal layer again and forms grid layer 20.Wherein, grid layer 20
Material may include the metals such as Al, Mo, Cu, Ag.
Then, the first insulating layer 30 can be formed on grid layer 20, which covers substrate layer 10 and grid
Pole layer 20.The material of first insulating layer 30 may include SiNx or SiOx etc., mainly pass through chemical vapor deposition process system
It is standby to be formed.
Later, can by physical gas phase deposition technology on the first insulating layer 30 deposited semiconductor layer 40.It wherein, should be partly
The material of conductor layer 40 may include amorphous silicon membrane.Form structure as shown in Figure 2.
In some embodiments, referring to Fig. 3, can by physical gas phase deposition technology depositing second metal layer 50,
In, which covers semiconductor layer 40 and the first insulating layer 30.The material of the second metal layer 50 may include Ni,
Mo, Ti, Cu, W or the alloy between them etc..
It in some embodiments, referring to Fig. 4, can be using the wet etching in back channel etching method to second metal layer
50 perform etching, and form source-drain electrode layer.Wherein, source-drain electrode layer includes source electrode 52, drain electrode 51 and part of semiconductor layer 40.
102, a precursor solution is provided, the precursor solution includes nitrocellulose.
Wherein, precursor solution may include organic solvent and nitrocellulose solute.Organic solvent may include ethyl alcohol, first
Alcohol or isopropanol etc..Nitrocellulose solute includes but is not limited to collodion.
In some embodiments, the precursor solution can by ethyl alcohol and collodion according to preset ratio mixed dissolution and
At.It should be noted that under normal circumstances, ethyl alcohol and collodion can be according to volume ratio 3:7 or 4:6 mixed dissolutions.
It is analyzed through X-ray photoelectron spectroscopic analysis (X-ray photoelectron spectroscopy, XPS), nitrification
Fiber is because wherein containing a large amount of N element, and N element will be migrated to semiconductor layer back channel region, and N element coordination ability pole
By force, it is combined with the Ga in IGZO, Zn etc..With the lone pair electrons of the N of the N-Zn (Ga) after metal bonding by the weak bond oxygen in IGZO
It is attracted to back channel, channel Lacking oxygen increases before causing, therefore carrier increases, and Ion becomes larger；Correspondingly, therefore back channel lacks
It falls into state oxygen to reduce, Ioff is reduced, and Ion/Ioff increases.Nitrocellulose can play exclusion of water as a result, and oxygen enters back channel
Effect.
103, the precursor solution is coated on the source-drain electrode layer, forms second insulating layer.
Specifically, precursor solution can be coated on source-drain electrode layer, a film is formed；The film is toasted,
Second insulating layer is formed to solidify the film, forms structure as shown in Figure 5.Wherein, baking temperature can be at 110 degrees Celsius extremely
Between 150 degrees Celsius, baking duration can be between 1 hour to 2 hours.Wherein, coating method can be similar with light blockage coating,
The second insulating layer can be made of nitrocellulose.
104, photoresist layer is set on the second insulating layer, development is exposed in the photoresist to the photoresist layer
First through hole is formed on layer with second insulating layer described in expose portion.
In some embodiments, referring to Fig. 6, can coat a layer photoresist material in second insulating layer 60 forms light
Resistance layer 70, and the photoresist layer 70 is exposed using mask plate and then is developed again, to form first on photoresist layer 70
Through-hole 71 is with expose portion second insulating layer 60.
105, the second insulating layer for using etching solution etching to be exposed is to form second in the second insulating layer
Through-hole is with expose portion source-drain electrode layer.
In some embodiments, photoresist layer 70 can be subjected to wet process erosion to exposed second insulating layer 60 as exposure mask
It carves, to form the second through-hole 72 in second insulating layer 60 with expose portion source-drain electrode layer, ultimately forms structure as shown in Figure 7.
Wherein, etching solution used by the wet etching may include the ethyl alcohol of high concentration (concentration is 95% or more).It needs to illustrate
, the organic solvent that etching solution can also chemically react for other with nitrocellulose, for example, alcohol, ether or they
Mixed solvent etc.；Array base manufactured by the manufacturing method for the array substrate that structure shown in Fig. 7 as provides through this embodiment
Plate.
The manufacturing method of array substrate provided in this embodiment include provide a substrate, the substrate include substrate layer and
Grid layer, the first insulating layer, semiconductor layer and the source-drain electrode layer being set in turn on the substrate layer；It is molten to provide a presoma
Liquid, the precursor solution include nitrocellulose；The precursor solution is coated on the source-drain electrode layer, forms second absolutely
Edge layer；Photoresist layer is set on the second insulating layer, development is exposed with the shape on the photoresist layer to the photoresist layer
At first through hole with second insulating layer described in expose portion；Use the etching solution second insulating layer that is exposed of etching with
The second insulating layer forms the second through-hole with expose portion source-drain electrode layer.The second insulating layer of this programme is by nitrocellulose structure
At, water and oxygen can effectively be isolated, avoid water and oxygen from entering semiconductor layer and the resistance value of semiconductor layer is changed,
And cause threshold voltage that huge drift occurs, influence the stability of array substrate.
The embodiment of the present application also provides a kind of array substrate, as shown in fig. 7, the array substrate may include: substrate layer 10,
Grid layer 20, the first insulating layer 30, semiconductor layer 40, source-drain electrode layer (source electrode 52, drain electrode 51 and part of semiconductor layer 40), the
Two insulating layers 60 and photoresist layer 70；Wherein:
The grid layer 20 is arranged on the substrate layer 10；
First insulating layer 30 is covered on 10 on the grid layer 20 and the substrate；
The semiconductor layer 40 is arranged on 30 first insulating layer；
The source-drain electrode layer is located on first insulating layer 30 and semiconductor layer 40；
The second insulating layer 60 is covered on the source-drain electrode layer；
The photoresist layer 70 is arranged in the second insulating layer 60；
Wherein, the second insulating layer 60 is made of nitrocellulose.
It should be noted that the manufacturing method of array substrate provided by the present embodiment and above-mentioned array substrate was formed
Array base-plate structure is consistent, is specifically referred to above-described embodiment, and this will not be repeated here.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, there is no the portion being described in detail in some embodiment
Point, reference can be made to the related descriptions of other embodiments.
The manufacturing method of a kind of array substrate provided by the embodiment of the present application and array substrate have been carried out in detail above
It introduces, specific examples are used herein to illustrate the principle and implementation manner of the present application, the explanation of above embodiments
It is merely used to help understand the technical solution and its core concept of the application；Those skilled in the art should understand that: its
It is still possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is equal
Replacement；And these are modified or replaceed, the technical solution of each embodiment of the application that it does not separate the essence of the corresponding technical solution
Range.
Claims (10)
1. a kind of manufacturing method of array substrate characterized by comprising
A substrate is provided, the substrate includes substrate layer and the grid layer being set in turn on the substrate layer, the first insulation
Layer, semiconductor layer and source-drain electrode layer；
A precursor solution is provided, the precursor solution includes nitrocellulose；
The precursor solution is coated on the source-drain electrode layer, second insulating layer is formed；
Photoresist layer is set on the second insulating layer, development is exposed to be formed on the photoresist layer to the photoresist layer
First through hole is with second insulating layer described in expose portion；
The second insulating layer for using etching solution etching to be exposed is to form the second through-hole in the second insulating layer with sudden and violent
Reveal part source-drain electrode layer.
2. the manufacturing method of array substrate as described in claim 1, which is characterized in that one substrate of the offer, the substrate packet
Substrate layer and the grid layer being set in turn on the substrate layer, the first insulating layer, semiconductor layer and source-drain electrode layer are included, is wrapped
It includes:
A substrate is provided, the substrate includes substrate layer；
The depositing layers on the substrate layer；
The first insulating layer is deposited on the grid layer；
Deposited semiconductor layer on the first insulating layer；
The depositing second metal layer on the semiconductor layer, and the second metal layer is carved using back channel etching method
Erosion forms source-drain electrode layer.
3. the manufacturing method of array substrate as described in claim 1, which is characterized in that the precursor solution further includes ethyl alcohol.
4. the manufacturing method of array substrate as claimed in claim 3, which is characterized in that the precursor solution is by the ethyl alcohol
It is formed with the collodion according to preset ratio mixed dissolution.
5. the manufacturing method of array substrate as claimed in claim 4, which is characterized in that the precursor solution is by the ethyl alcohol
It is formed with the collodion according to volume ratio 3:7 to 4:6 mixed dissolution.
6. the manufacturing method of array substrate as described in claim 1, which is characterized in that described to be coated on the precursor solution
On the source-drain electrode layer, second insulating layer is formed, comprising:
The precursor solution is coated on the source-drain electrode layer, a film is formed；
The film is toasted, forms second insulating layer to solidify the film, wherein baking temperature is at 110 degrees Celsius
To between 150 degrees Celsius, duration is toasted between 1 hour to 2 hours.
7. the manufacturing method of array substrate as claimed in claim 1 or 6, which is characterized in that the second insulating layer is fine by nitrification
Dimension is constituted.
8. the manufacturing method of array substrate as described in claim 1, which is characterized in that the etching solution includes ethyl alcohol.
9. the manufacturing method of array substrate as claimed in claim 8, which is characterized in that the concentration of the ethyl alcohol is more than or equal to
95%.
10. a kind of array substrate characterized by comprising substrate layer, grid layer, the first insulating layer, semiconductor layer, source-drain electrode
Layer, second insulating layer and photoresist layer；Wherein:
The grid layer is arranged on the substrate layer；
First insulating layer is covered on the grid layer and the substrate；
The semiconductor layer setting is on the first insulating layer；
The source-drain electrode layer is located on first insulating layer and semiconductor layer；
The second insulating layer is covered on the source-drain electrode layer；
The photoresist layer setting is on the second insulating layer；
Wherein, the second insulating layer is made of nitrocellulose.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910267618.7A CN110047941A (en) | 2019-04-03 | 2019-04-03 | The manufacturing method and array substrate of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910267618.7A CN110047941A (en) | 2019-04-03 | 2019-04-03 | The manufacturing method and array substrate of array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110047941A true CN110047941A (en) | 2019-07-23 |
Family
ID=67275915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910267618.7A Pending CN110047941A (en) | 2019-04-03 | 2019-04-03 | The manufacturing method and array substrate of array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110047941A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5306653A (en) * | 1991-08-27 | 1994-04-26 | Goldstar Co., Ltd. | Method of making thin film transistors |
| KR20150074825A (en) * | 2013-12-24 | 2015-07-02 | 엘지디스플레이 주식회사 | Thin film transistor array substrate using oxide semiconductor and method for fabricating the same |
| US20170323904A1 (en) * | 2016-05-03 | 2017-11-09 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
| KR20180031979A (en) * | 2016-09-21 | 2018-03-29 | 연세대학교 산학협력단 | Oxide thin film transistor and method of manufacturing the same |
-
2019
- 2019-04-03 CN CN201910267618.7A patent/CN110047941A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5306653A (en) * | 1991-08-27 | 1994-04-26 | Goldstar Co., Ltd. | Method of making thin film transistors |
| KR20150074825A (en) * | 2013-12-24 | 2015-07-02 | 엘지디스플레이 주식회사 | Thin film transistor array substrate using oxide semiconductor and method for fabricating the same |
| US20170323904A1 (en) * | 2016-05-03 | 2017-11-09 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
| KR20180031979A (en) * | 2016-09-21 | 2018-03-29 | 연세대학교 산학협력단 | Oxide thin film transistor and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107342345B (en) | A kind of phototransistor based on ferroelectricity gate medium and thin layer molybdenum disulfide channel | |
| CN106684037B (en) | Optimize the tft array preparation method of 4M processing procedure | |
| CN106505033B (en) | Array substrate and preparation method thereof, display device | |
| CN104576542B (en) | Array substrate and preparation method thereof, display device | |
| US20180212043A1 (en) | Method for manufacturing thin film transistor | |
| WO2016150056A1 (en) | Thin-film transistor and manufacturing method therefor, and display device | |
| TW449929B (en) | Structure and manufacturing method of amorphous-silicon thin film transistor array | |
| US8728861B2 (en) | Fabrication method for ZnO thin film transistors using etch-stop layer | |
| CN106653774B (en) | Array substrate and manufacturing method thereof, mask and display device | |
| US10050151B2 (en) | Dual-gate TFT array substrate and manufacturing method thereof, and display device | |
| CN105428245B (en) | Dot structure and preparation method thereof, array substrate and display device | |
| WO2019114357A1 (en) | Array substrate, manufacturing method therefor, and display device | |
| WO2015165174A1 (en) | Thin film transistor and manufacturing method therefor, display substrate, and display device | |
| WO2018161874A1 (en) | Display substrate, manufacturing method therefor and display device | |
| CN103715272A (en) | Metallic oxide thin film transistor and preparing method thereof | |
| CN103337462B (en) | Preparation method of thin film transistor | |
| JPS62131578A (en) | Manufacture of thin film transistor | |
| TWI546850B (en) | Method for manufacturing display panel | |
| CN103820784A (en) | Etchant composition, method for fabricating metal pattern, and method for manufacturing array substrate | |
| WO2015024337A1 (en) | Array substrate, manufacturing method of same, and display device | |
| CN107706199A (en) | A kind of preparation method of thin-film transistor array base-plate | |
| CN110085601A (en) | A kind of array substrate and preparation method thereof, display panel, terminal device | |
| CN110047941A (en) | The manufacturing method and array substrate of array substrate | |
| CN103400802B (en) | Array base palte and preparation method thereof and display unit | |
| CN106328693B (en) | Display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190723 |
|
| RJ01 | Rejection of invention patent application after publication |