CN110047767A - A kind of apparatus for testing chip and its design method, direct fault location analysis method - Google Patents
A kind of apparatus for testing chip and its design method, direct fault location analysis method Download PDFInfo
- Publication number
- CN110047767A CN110047767A CN201810036167.1A CN201810036167A CN110047767A CN 110047767 A CN110047767 A CN 110047767A CN 201810036167 A CN201810036167 A CN 201810036167A CN 110047767 A CN110047767 A CN 110047767A
- Authority
- CN
- China
- Prior art keywords
- chip
- fluting
- tested
- substrate
- installation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention provides a kind of apparatus for testing chip and its design methods, direct fault location analysis method, a fluting is opened up on installation region by the installation chip to be tested of the PCB substrate in apparatus for testing chip, the substrate of chip to be tested is exposed by the fluting, device based on this kind design carries out the direct fault location analysis of chip, the injection of its laser error can be directly injected on the substrate of chip by fluting, the verifying that maximum probability promotes the chip checking stage is comprehensive, the unqualified risk of security performance after reduction chip throwing piece；Further, the design method of the fluting not only will not influence the normal work of chip, but also the substrate surface neat and tidy of chip, it gets twice the result with half the effort for laser error injection analysis, solves the problems, such as that patch can not be normally carried out laser error injection analysis in the chip on PCB.
Description
Technical field
The present invention relates to chip testing technology field more particularly to a kind of apparatus for testing chip and its design methods, failure
Inject analysis method.
Background technique
With the development of information security technology, various safety products are more more and more universal, not only include financial IC card, social security
These safety products, Iots and the smart machine field such as card, the USBKey for Web bank, encrypted U disk, it is also desirable to which safety can
The chip leaned on guarantees the reliability of its product.Therefore it analyzes and researches to the security feature of safety chip, guarantees that its safety is logical
It crosses each evaluation standard to be even more important, and the analysis of the security function must be accomplished comprehensively in the Qualify Phase before chip throws piece
Assessment.
In safety chip field, the safety of chip is more ancient constant topic, in existing technology, for
The safety analysis of chip can substantially be divided into three kinds of analysis modes, respectively non-intrusion type attack, half intrusive attack and intrusion
Formula attack, wherein half intrusive attack has very important status between non-intrusion type attack and intrusive attack, and
Optical errors injection is considered as one of maximally efficient ground attack means in half intrusive attack at present.So how to accomplish accurate
Light attack, necessarily will appear corresponding attack equipment, laser injection platform just comes into being.Laser light source point in Attack Platform
For two wave bands of 1064nm and 808nm, wherein 1064nm attack for the back side of chip especially effective, but carries out this and swash
The premise of light analysis is the bulk silicon portion that must expose chip.
For the error injection means of chip, laser error injection is the most accurate and effective a kind of, therefore chip is thrown
Verifying before piece, laser error injection is particularly important link.Chip front side and core can be divided into the laser injection of chip
Two kinds of the piece back side, wherein when carrying out laser error injection analysis to chip back, it is necessary to the bulk silicon portion of chip is exposed, but
It is that in actual chips in analysis Qualify Phase, after chip is arranged on PCB, the back side of chip is blocked, and laser can not
It is injected on the back side, can not be normally carried out so as to cause laser error injection analysis.
Summary of the invention
The present invention provides a kind of apparatus for testing chip and its design method, direct fault location analysis method, existing to solve
Chip is all patch on PCB in Qualify Phase, causes the back side silicon substrate of chip that can not be normally carried out laser error injection
The problem of analysis.
In order to solve the above technical problems, the invention adopts the following technical scheme:
A kind of apparatus for testing chip, the safety test applied to chip are analyzed, comprising: PCB substrate and chip to be tested, institute
Stating PCB substrate includes for installing the installation region of the chip to be tested, subtest circuit and pin, and the pin passes through
The subtest circuit is electrically connected with the output pin circuit of the chip to be tested；
It is additionally provided with the fluting through the installation region on the installation region, and by the core to be tested after installation
The substrate of piece is exposed from the installation region.
Further, it is described fluting be set to the installation region middle position on, and the size of the fluting with it is described
The size of the substrate of chip to be tested matches.
Further, the apparatus for testing chip further includes support plate, and the support plate is set to the position of the fluting
On, and connect with the edge of the fluting.
Further, the support plate includes the binding face being arranged on its surface, passes through the coating adhesive on the binding face
Layer fixes the chip to be tested.
Further, the support plate is the connecting plate that shape is convex shape.
Further, the raised side of the connecting plate is connect with the inward flange of the fluting, and in the connecting plate
A U-shaped gap is formed between the inward flange of the fluting.
Further, it is additionally provided at least one supporting point between the support plate and the edge of the fluting, is used for
The support plate is fixed on the intermediate empty region of the fluting.
Further, when the particular number of at least one supporting point is two, described two supporting points are set respectively
It sets in the support plate on two opposite sides, and forms two between the support plate and the inward flange of the fluting
A symmetrical U-shaped gap.
In order to solve the above-mentioned technical problem, the present invention also provides a kind of design method of apparatus for testing chip, the PCB
Substrate and the chip to be tested being arranged in the PCB substrate, the design method include:
It is arranged in the PCB substrate for installing the installation region of the chip to be tested, for the auxiliary of subtest
Help test circuit, and the pin for connecting external test facility；
Setting runs through the fluting of the installation region on the installation region；
The chip to be tested is fixed on the installation region, and the substrate of the chip to be tested face it is described
Fluting, the substrate is exposed from the fluting.
In order to solve the above-mentioned technical problem, the present invention also provides a kind of direct fault location analysis methods, which comprises
Installation region for installing chip to be tested, the subtest electricity for subtest are set in PCB substrate
Road, and the pin for connecting external test facility；
Setting runs through the fluting of the installation region on the installation region；
The chip to be tested is fixed on the installation region, and the substrate of the chip to be tested face it is described
Fluting, the substrate is exposed from the fluting；
By the chip bonding to be tested in the PCB substrate, and connect the chip to be tested, subtest circuit
Circuit between pin；
Laser injection is carried out to the substrate of the chip to be tested from the position of the fluting by external detection equipment；
To the safety Analysis of the chip to be tested after laser injection.
The utility model has the advantages that
The present invention provides a kind of apparatus for testing chip and its design methods, direct fault location analysis method, by chip
A fluting is opened up on the installation region of the installation chip to be tested of PCB substrate in test device, it will be to be measured by the fluting
The substrate of examination chip exposes, and the device based on this kind design carries out the direct fault location analysis of chip, laser error injection
It can be directly injected on the substrate of chip by fluting, the verifying that maximum probability promotes the chip checking stage is comprehensive, reduces core
The unqualified risk of security performance after piece throwing piece；Further, the design method of the fluting not only will not influence the normal of chip
Work, and the substrate surface neat and tidy of chip get twice the result with half the effort for laser error injection analysis, solve patch in PCB
On chip can not be normally carried out laser error injection analysis the problem of.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for the apparatus for testing chip that the embodiment of the present invention one provides；
Fig. 2 is the first structure diagram for the PCB substrate that the embodiment of the present invention one provides；
Fig. 3 is the second structural schematic diagram of the PCB substrate that the embodiment of the present invention one provides；
Fig. 4 is the third structural schematic diagram for the PCB substrate that the embodiment of the present invention one provides；
Fig. 5 is the flow chart of the design method of apparatus for testing chip provided by Embodiment 2 of the present invention；
Fig. 6 is the flow chart of direct fault location analysis method provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram of the apparatus for testing chip after binding chip provided in an embodiment of the present invention.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.
Embodiment one:
Fig. 1 is the apparatus for testing chip that the embodiment of the present invention one provides, referring to FIG. 1, the apparatus for testing chip 10 includes
PCB substrate 101 and chip to be tested 102, wherein the PCB substrate 101 includes installation region 1011, subtest circuit 1012
With pin 1013, the chip 102 to be tested is mounted on the installation region 1011, and its output pin is by described auxiliary
Test circuit 1012 is helped to be electrically connected with pin 1013.
In the present embodiment, the fluting through the installation region 1011 is additionally provided on the installation region 1011
1014, and the substrate of chip to be tested 102 is installed against the fluting 1014, so that chip to be tested 102 after mounting
Substrate exposes completely, and at this moment when carrying out direct fault location analysis, laser injection device is directly from the position pair of fluting 1014
Chip 102 to be tested carries out laser injection, and such fluting design on pcb board carries out the scheme of direct fault location analysis,
When not increasing the volume of Innovation Input cost, it can accomplish that chip back fast and safely removes PCB hardboard and do not influence core
Piece works normally, and the verifying that maximum probability promotes the chip checking stage is comprehensive, and it is unqualified to reduce security performance after chip throws piece
Risk.
In practical applications, chip 102 to be tested is fallen from fluting 1014 during installation in order to prevent, and the present invention is implemented
The fluting 1014 is specifically located on the middle position of installation region 1011 by example, and the size of the fluting 1014 is set
It is set to and is matched with the size of the substrate of chip 102 to be tested, optionally, be arranged to be slightly less than the size of substrate, so not only
It can ensure that the exposed of substrate, laser is freely injected into chip, chip can also be avoided from fluting 1014
In fall down.
In practical applications, the shape of the fluting 104 can be set to rectangle, circle, semicircle, moon shape, annular
The shape of circle etc. exposes the substrate of chip 102 to be tested as long as being able to achieve.
In the present embodiment, as shown in Fig. 2, the apparatus for testing chip 10 further includes support plate 103, the support plate 103
Shape with it is described fluting 1014 shape it is identical, and its size be less than fluting 1014 size；The support plate 103 is arranged
On the position of fluting 1014, and by connecting with the edge of fluting 1014, and there are gaps therebetween, fix from realizing
Installation, and the support plate 103 is only for used in the blocking when install the chip 102 to be tested positions, when will be to be tested
After chip 102 is welded on installation region 1011, which is to need to remove to expose the substrate of chip to hold
The analysis of row direct fault location.
Certain support plate 103 nor is it necessary that and eliminate, when the gap formed between fluting 1014 and support plate 103
It is enough to expose substrate and realizes that laser fluence is fashionable, then can not removes.
In practical applications, the connection between the support plate 103 and fluting 1014 is particular by setting in the two
Between tie point realize fix, optionally, be provided with mutually matched buckle structure on the corresponding position of the two to realize.
In practical applications, forming shape can also be arranged in the support plate 103 and be the connecting plate of "convex" shaped, and passed through
The position of protrusion on connecting plate is fixedly connected with the inward flange of fluting 1014, at this moment will form between connecting plate and fluting 104
The gap of one similar " u "-shaped shape；And in the actual fabrication PCB substrate 101, the support plate 103 and fluting 1014 are
It is integrally formed, the gap of a " u "-shaped shape is set especially by the middle position in installation region 1011, such as Fig. 2 institute
Show.
In the present embodiment, the fixation between the support plate 103 and fluting 1014 specifically can also be by being arranged two
At least one supporting point 1015 between person is realized, as shown in figure 3, when the particular number of at least one supporting point 1015
When being two, described two supporting points 1015 be respectively set in the support plate 103 on two opposite sides, and in institute
It states and forms two symmetrical U-shaped gaps 104 between support plate 103 and the inward flange of the fluting 1014.
In the present embodiment, when the quantity of the supporting point 1015 is 4, four supporting points 1015 are respectively set
With in the support plate 103 on four sides, and formed between the support plate 103 and the inward flange of the fluting 1014
Four symmetrical L shape gaps 104.
In practical applications, as shown in figure 4, the subtest circuit 1012 includes binding line 1012a and at least one
Electronic component 1012b, at least one electronic component 1012b are connected in binding line 1012a by series-parallel mode, and
Binding line 1012a is used to be separately connected the output pin of chip 102 to be tested, and by electronic component 1012b to core to be tested
Piece 102 is protected, and in addition binding line 1012a is also used to realize being electrically connected between electronic component 1012b and pin 1013.
In practical applications, in the binding line 1012a being arranged in installation region 1011, binding line and fluting need to be designed
There are enough surpluses at edge, as shown in Figure 4, are arranged on the marginal position of installation region 1011.
In the present embodiment, for the ease of by chip 102 to be tested be mounted on fluting 1014 on, and realize output pin with
The gold certainly position of binding line 1012a, is additionally provided with binding face 1031, which is used on the surface of support plate 103
Fixed chip 102 to be tested uses, and in practical applications, the binding face 1031 is equipped with the metal layer of a fritter, is installing
When chip, it is covered with one layer of glue-line or High temperature-resistanadhesive adhesive tape by applying on the metal layer, which needs to guarantee will fluting
1014 and flying shore plate 103 paste binding that is complete and not influencing chip.
In conclusion a kind of apparatus for testing chip is provided through this embodiment, the PCB substrate in apparatus for testing chip
Installation chip to be tested installation region on open up a fluting, the substrate of chip to be tested is exposed by the fluting
Come, the device design of this kind fluting scheme allows and saves some unnecessary chip package forms, example when testing chip
Such as the common card class wrapper form in safety chip field, improving when PCB production can be realized the more kinds of sides a PCB
Case is verified；And using after PCB fluting, the test for being conducive to improve chip secure is comprehensive, compensates on existing PCB
The chip of binding can not carry out the limitation of laser error injection.
Further, it by carrying out the injection of laser at PCB fluting, can be extended in the multiple foot positions of binding chip
In the case where periphery, it can not be carried out when realizing the purpose of safety analysis, while security protection can be had to avoid chip front side
The drawbacks of test, the safety test of raising it is comprehensive, so that laser can not be normally carried out in the chip on PCB by solving patch
The problem of error injection is analyzed.
Embodiment two:
Fig. 5 is the design method of apparatus for testing chip provided by Embodiment 2 of the present invention, wherein the apparatus for testing chip packet
PCB substrate is included, and the chip to be tested being arranged in the PCB substrate, referring to FIG. 5, design side provided in this embodiment
Method specifically includes the following steps:
The installation region for installing the chip to be tested is arranged in the PCB substrate, is used for subtest by S501
Subtest circuit, and the pin for connecting external test facility；
S502, setting runs through the fluting of the installation region on the installation region；
The chip to be tested is fixed on the installation region by S503, and the substrate face of the chip to be tested
The fluting, the substrate is exposed from the fluting.
In the present embodiment, when the fluting is arranged, optionally the fluting is set in the installation region
Between on position, and the size of the fluting is matched with the size of the substrate of the chip to be tested.
In practical applications, chip to be tested is fallen from the fluting of design during installation in order to prevent, and the present invention is implemented
Example by it is described fluting be specifically located on the middle position of installation region, and by the fluting be dimensioned to it is to be tested
The size of the substrate of chip matches, and optionally, is arranged to be slightly less than the size of substrate, not only can ensure that substrate
It is exposed, laser is freely injected into chip, chip can also be avoided and fallen down from fluting, it is optionally, described to open
The shape of slot can be set to the shape of rectangle, circle, semicircle, moon shape, annular circle etc., will be to be measured as long as being able to achieve
The substrate of examination chip exposes.
In the present embodiment, the apparatus for testing chip further includes support plate, the shape of the support plate and the fluting
Shape is identical, and its size is less than the size of fluting；The support plate is arranged on the position of fluting, and by with fluting
Edge connection, and therebetween there are gap, is fixedly mounted from realizing, and the support plate be only for install it is described to be measured
Try chip when blocking positioning used in, after chip to be tested is welded on installation region, the support plate be need remove from
And the substrate of chip is exposed and executes direct fault location analysis.Certainly in practical applications, the support plate is being set up
After chip to be tested, according to the actual situation, the structure for not removing support plate can choose, as long as shape between fluting and support plate
At gap be enough to expose substrate and realize that laser fluence is fashionable, then can not remove.
In the present embodiment, the fixation between the support plate and fluting specifically can also be by being arranged between
At least one supporting point realizes, as shown in figure 3, when the particular number of at least one supporting point is two, described two
A supporting point be respectively set in the support plate on two opposite sides, and in the support plate and the fluting
Two symmetrical U-shaped gaps are formed between edge.
In the present embodiment, when the quantity of the supporting point is 4, four supporting points are respectively set and the branch
On fagging on four sides, and four symmetrical L shapes are formed between the support plate and the inward flange of the fluting
Gap.
In practical applications, it can also be the connecting plate of "convex" shaped by the way that forming shape is arranged in the support plate, and lead to
The position for the protrusion crossed on connecting plate is fixedly connected with the inward flange of fluting, at this moment will form a class between connecting plate and fluting
Like the gap of " u "-shaped shape；And in the actual fabrication PCB substrate, the support plate and fluting are integrally formed.
Based on above-mentioned apparatus for testing chip structure, the present invention also provides a kind of direct fault location analysis methods, such as Fig. 6 institute
Show, the following processing step of this method:
The installation region for installing chip to be tested, the auxiliary survey for subtest is arranged in S601 in PCB substrate
Try circuit, and the pin for connecting external test facility；
S602, setting runs through the fluting of the installation region on the installation region；
The chip to be tested is fixed on the installation region by S603, and the substrate face of the chip to be tested
The fluting, the substrate is exposed from the fluting；
S604 by the chip bonding to be tested in the PCB substrate, and connects the chip to be tested, auxiliary survey
Try the circuit between circuit and pin；
S605 carries out laser to the substrate of the chip to be tested from the position of the fluting by external detection equipment
Injection；
S606, to the safety Analysis of the chip to be tested after laser injection.
It in practical applications, specifically can be by selecting an existing common test PCB for the design of PCB substrate
Plate determines the installation site of the chip to be tested on the test pcb board, then by opening up a slot in the installation site
Mouthful, in this way when chip to be tested is installed to the installation site, the back side of chip can expose completely, and should
The output pin of chip passes through in subtest circuit connection to pin.
Then, the apparatus for testing chip after the assembling is inserted into external detection equipment, which can will emit laser fluence
Enter, and laser injection is injected particular by from the notch opened up on pcb board；
Last external detection equipment carries out security performance by the acquisition that the chip after injecting to laser carries out output information
Analysis.
Optionally, in step s 604 binding chip when, can be by socket be arranged a support plate, and
High temperature gummed tape is pasted in support plate, then by the substrate attaching of chip on the region for being equipped with adhesive tape, to realize to chip
Binding；
Further, after binding, upper black glue can also be put on the position of chip in the back side of pcb board, to chip into
Row sealing；
Further, it is injected from notch for the ease of laser, it is also necessary to remove and be provided with support plate on notch, specifically
By the way that the supporting point of fixed support plate is cut section, then support plate is taken off, while slicing off tape-stripping part, so that exposed
The substrate of chip, specific structure signal are as shown in Figure 7；
Further, the adhesive tape on the substrate of exposed die is cleaned, laser error analysis is carried out；
Further, the data that acquisition laser error injects lower chip carry out analysis assessment security performance.
By the implementation of above embodiments it is found that the present invention have it is following the utility model has the advantages that
The present invention provides a kind of apparatus for testing chip and its design method, direct fault location analysis method, by
A fluting is opened up on the installation region of the installation chip to be tested of PCB substrate in apparatus for testing chip, it will by the fluting
The substrate of chip to be tested exposes, and the device based on this kind design carries out the direct fault location analysis of chip, laser error
Injection can by fluting be directly injected on the substrate of chip, solve patch can not be normally carried out in the chip on PCB it is sharp
The problem of light error injection is analyzed.
Further, support plate is arranged also on slotting position to connect with supporting point, by support plate to chip to be tested
Blocking limit during installation, adheres to before avoiding chip bonding without PCB, chip can be fallen from fluting, and and supporting point is kept away
The problem of chip can not remove PCB hardboard after binding is exempted from；The also direct fault location analysis of this kind setting simultaneously, so that in chip
PCB production, chip bonding and the non-normal safe functional verification of Qualify Phase test are a kind of new survey for chip checking
Try path.
The above content is specific embodiment is combined, further detailed description of the invention, and it cannot be said that this hair
Bright specific implementation is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection of the invention
Range.
Claims (10)
1. a kind of apparatus for testing chip, the safety test applied to chip is analyzed characterized by comprising PCB substrate and to be measured
Chip is tried, the PCB substrate includes for installing the installation region of the chip to be tested, subtest circuit and pin, institute
Pin is stated to be electrically connected by the subtest circuit with the output pin circuit of the chip to be tested；
It is additionally provided with the fluting through the installation region on the installation region, and by the chip to be tested after installation
Substrate is exposed from the installation region.
2. apparatus for testing chip as described in claim 1, which is characterized in that the fluting is set to the centre of the installation region
On position, and the size of the fluting is matched with the size of the substrate of the chip to be tested.
3. apparatus for testing chip as claimed in claim 1 or 2, which is characterized in that the apparatus for testing chip further includes support
Plate, the support plate are set on the position of the fluting, and are connect with the edge of the fluting.
4. apparatus for testing chip as claimed in claim 3, which is characterized in that the support plate includes the patch being arranged on its surface
The chip to be tested is fixed by coating glue-line on the binding face in conjunction face.
5. apparatus for testing chip as claimed in claim 4, which is characterized in that the support plate is the connection that shape is convex shape
Plate.
6. apparatus for testing chip as claimed in claim 5, which is characterized in that the raised side of the connecting plate and the fluting
Inward flange connection, and between the connecting plate and the inward flange of the fluting formed a U-shaped gap.
7. apparatus for testing chip as claimed in claim 4, which is characterized in that the edge of the support plate and the fluting it
Between be additionally provided at least one supporting point, for the support plate to be fixed on to the intermediate empty region of the fluting.
8. apparatus for testing chip according to claim 7, which is characterized in that when the specific number of at least one supporting point
When amount is two, described two supporting points be respectively set in the support plate on two opposite sides, and in the branch
Two symmetrical U-shaped gaps are formed between fagging and the inward flange of the fluting.
9. a kind of design method of apparatus for testing chip, which is characterized in that the PCB substrate and setting are in the PCB substrate
Chip to be tested, the design method includes:
Installation region for installing the chip to be tested, the auxiliary survey for subtest are set in the PCB substrate
Try circuit, and the pin for connecting external test facility；
Setting runs through the fluting of the installation region on the installation region；
The chip to be tested is fixed on the installation region, and the substrate of the chip to be tested faces described open
Slot exposes the substrate from the fluting.
10. a kind of direct fault location analysis method, which is characterized in that the described method includes:
Installation region for installing chip to be tested is set in PCB substrate, for the subtest circuit of subtest, with
And the pin for connecting external test facility；
Setting runs through the fluting of the installation region on the installation region；
The chip to be tested is fixed on the installation region, and the substrate of the chip to be tested faces described open
Slot exposes the substrate from the fluting；
By the chip bonding to be tested in the PCB substrate, and connects the chip to be tested, subtest circuit and draw
Circuit between foot；
Laser injection is carried out to the substrate of the chip to be tested from the position of the fluting by external detection equipment；
To the safety Analysis of the chip to be tested after laser injection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810036167.1A CN110047767B (en) | 2018-01-15 | 2018-01-15 | Chip testing device, design method thereof and fault injection analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810036167.1A CN110047767B (en) | 2018-01-15 | 2018-01-15 | Chip testing device, design method thereof and fault injection analysis method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110047767A true CN110047767A (en) | 2019-07-23 |
| CN110047767B CN110047767B (en) | 2023-06-20 |
Family
ID=67272786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810036167.1A Active CN110047767B (en) | 2018-01-15 | 2018-01-15 | Chip testing device, design method thereof and fault injection analysis method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110047767B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11150134A (en) * | 1997-11-19 | 1999-06-02 | Mitsumi Electric Co Ltd | Semiconductor device |
| CN102116838A (en) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | Emission microscope chip failure analyzing method and system |
| CN103680640A (en) * | 2013-12-11 | 2014-03-26 | 北京时代民芯科技有限公司 | Laser simulation single particle effect back irradiation test method for memory circuit |
| CN104931509A (en) * | 2015-06-19 | 2015-09-23 | 中国科学院空间科学与应用研究中心 | Focusing plane positioning device and method of laser micro-beam back irradiation chip test |
-
2018
- 2018-01-15 CN CN201810036167.1A patent/CN110047767B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11150134A (en) * | 1997-11-19 | 1999-06-02 | Mitsumi Electric Co Ltd | Semiconductor device |
| CN102116838A (en) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | Emission microscope chip failure analyzing method and system |
| CN103680640A (en) * | 2013-12-11 | 2014-03-26 | 北京时代民芯科技有限公司 | Laser simulation single particle effect back irradiation test method for memory circuit |
| CN104931509A (en) * | 2015-06-19 | 2015-09-23 | 中国科学院空间科学与应用研究中心 | Focusing plane positioning device and method of laser micro-beam back irradiation chip test |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110047767B (en) | 2023-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100578534C (en) | Smart card and the accounting system that utilizes this smart card | |
| CN103635819B (en) | Reflectometer test device for integrated circuit | |
| US9368529B2 (en) | Optical shielding device for separating optical paths | |
| TW200408029A (en) | Apparatus and method for dynamic diagnostic testing of integrated circuits | |
| DE112013006408B4 (en) | Flow sensor and manufacturing process for it | |
| CN110047767A (en) | A kind of apparatus for testing chip and its design method, direct fault location analysis method | |
| CN110082609A (en) | Portable airborne communication equipment electromagnet radiation detection instrument | |
| CN106952838A (en) | The parallel wafer test systems of dedicated RF ID and verification method | |
| US7129718B2 (en) | Method and structure for measuring a bonding resistance | |
| CN107680487A (en) | A kind of display module and display device | |
| CN210894601U (en) | Safety chip testing board and device thereof | |
| CN103576259B (en) | The joints of optical fibre and assemble method | |
| CN206863244U (en) | Integrative detection plate | |
| CN102608449A (en) | Electric stress limit evaluation method for gallium arsenide monolithic microwave power amplifier | |
| CN105547176B (en) | The automatic damage identification method of vehicle based on fibre optical sensor | |
| CN206990845U (en) | A kind of device for lifting optical filter box fitting efficiency | |
| CN106332543A (en) | Method of using internal diode to test IC (Integrated Circuit) pseudo soldering | |
| CN207743227U (en) | A kind of encapsulating structure of optical finger print chip | |
| CN100477140C (en) | Packing component of semiconductor and preparing method thereof | |
| CN105374773A (en) | MCSP power semiconductor device and manufacturing method | |
| US7745234B2 (en) | Method for reclaiming semiconductor package | |
| CN205539230U (en) | Quick debugging circuit through electric test | |
| CN215005520U (en) | Test fixture and test system | |
| CN109690566A (en) | A kind of optical finger print identification mould group and electronic device | |
| CN110197101A (en) | Optical finger print identifies mould group and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |