CN110047738B - Mask, thin film transistor, array substrate, manufacturing method and display device - Google Patents

Mask, thin film transistor, array substrate, manufacturing method and display device Download PDF

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Publication number
CN110047738B
CN110047738B CN201910332924.4A CN201910332924A CN110047738B CN 110047738 B CN110047738 B CN 110047738B CN 201910332924 A CN201910332924 A CN 201910332924A CN 110047738 B CN110047738 B CN 110047738B
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photoresist
partial
thin film
film transistor
region
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CN110047738A (en
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安晖
叶成枝
吕艳明
操彬彬
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention provides a mask, a thin film transistor, an array substrate, a manufacturing method of the thin film transistor and a display device, wherein the manufacturing method of the thin film transistor comprises the following steps: forming a grid electrode, a grid electrode insulating layer, an active layer and an insulating protective layer, forming light resistance on the insulating protective layer, and forming light resistance patterns by adopting a mask, wherein the light resistance patterns comprise: the photoresist full-retention area, the first photoresist partial-retention area, the second photoresist partial-retention area and the photoresist removal area, wherein the thickness of the second photoresist partial-retention area is smaller than that of the first photoresist partial-retention area; etching the photoresist pattern and the insulating protection layer to reduce the thickness of the photoresist full-retention area and the first photoresist partial-retention area, completely eliminating the photoresist in the second photoresist partial-retention area, and forming an opening in the part of the insulating protection layer which is not covered by the photoresist; forming a source drain metal layer; and stripping the residual photoresistor and the source drain metal layer positioned on the residual photoresistor to form a source electrode and a drain electrode. The invention can realize self-alignment of the grid and the source/drain.

Description

Mask, thin film transistor, array substrate, manufacturing method and display device
Technical Field
The invention relates to the technical field of display, in particular to a mask, a thin film transistor, an array substrate, a manufacturing method of the thin film transistor and the array substrate, and a display device.
Background
In the manufacturing process of the current thin film transistor, due to the deviation of exposure precision, self-alignment of a Gate (Gate) and a source/drain (S/D) is difficult to realize, that is, the Gate and the source/drain have a phenomenon of overlapping up-down projection areas, so that unfavorable coupling capacitance is generated.
Disclosure of Invention
In view of this, the invention provides a mask, a thin film transistor, an array substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the thin film transistor manufactured by the existing process is difficult to realize self-alignment of a gate and a source/drain.
In order to solve the above technical problem, the present invention provides a mask for manufacturing a thin film transistor, the mask comprising:
the first partial light-transmitting area corresponds to the grid electrode of the thin film transistor;
the second partial light-transmitting areas are positioned on two opposite sides of the first partial light-transmitting area, and the light transmittance of the second partial light-transmitting areas is smaller than or equal to that of the first partial light-transmitting areas;
the opaque regions are positioned on two sides of the second partial transparent region, which are far away from the first partial transparent region, wherein one opaque region and one second partial transparent region correspond to the source electrode or the drain electrode of the thin film transistor;
and the full light transmission region is positioned at the periphery of the first partial light transmission region, the second partial light transmission region and the non-light transmission region.
The invention provides a manufacturing method of a thin film transistor, which comprises the following steps:
providing a substrate base plate;
sequentially forming a grid electrode, a grid electrode insulating layer, an active layer and an insulating protection layer on the substrate, wherein the active layer is made of a transparent semiconductor material;
forming a photoresist on the insulating protection layer, and exposing and developing the photoresist by adopting the mask to form a photoresist pattern, wherein the photoresist pattern comprises: the photoresist stripping device comprises a photoresist full-reserved region corresponding to a full-light-transmitting region of the mask, a first photoresist partial-reserved region corresponding to a first partial-light-transmitting region of the mask, a second photoresist partial-reserved region corresponding to a second partial-light-transmitting region of the mask and a photoresist stripping region corresponding to a non-light-transmitting region of the mask, wherein the thickness of the second photoresist partial-reserved region is smaller than that of the first photoresist partial-reserved region;
etching the photoresist pattern and the insulating protection layer to reduce the thickness of the photoresist full-retention area and the first photoresist partial-retention area, completely eliminating the photoresist in the second photoresist partial-retention area, and forming an opening in the part of the insulating protection layer which is not covered by the photoresist;
forming a source drain metal layer, wherein the source drain metal layer covers the etched residual photoresist and the opening;
and stripping the residual photoresistor and the source drain metal layer positioned on the residual photoresistor to form a source electrode and a drain electrode.
Optionally, the gate is made of Cu, Al, or Ag.
Optionally, the step of etching the photoresist pattern and the insulating protection layer includes:
and synchronously etching the photoresist pattern and the insulating protection layer by adopting a dry etching process.
Optionally, the step of etching the photoresist pattern and the insulating protection layer includes:
and in the process of etching the photoresist pattern and the insulating protection layer, conducting conductor treatment on the active layer exposed by the opening to form a source contact region and a drain contact region.
The invention provides a manufacturing method of an array substrate, which comprises the step of manufacturing a thin film transistor by adopting the manufacturing method of the thin film transistor.
The invention provides a thin film transistor, which is manufactured by adopting the manufacturing method of the thin film transistor, and the thin film transistor comprises:
a substrate base plate;
a gate electrode;
a gate insulating layer;
the material of the active layer is a transparent semiconductor material;
the insulating protective layer is provided with an opening;
the source electrode and the drain electrode are in contact with the active layer through the opening, the orthographic projection of the source electrode and the drain electrode on the substrate is not overlapped with the orthographic projection of the grid electrode on the substrate, and the orthographic projection of the source electrode and the drain electrode on the substrate is overlapped with the orthographic projection of the opening on the substrate.
Optionally, the active layer includes: the active region is a semiconductor, the source electrode contact region and the drain electrode contact region are conductors, and orthographic projections of the source electrode contact region and the drain electrode contact region on the substrate are overlapped with orthographic projections of the opening holes on the substrate.
The invention provides an array substrate, which comprises the thin film transistor.
The invention provides a display device, which comprises the array substrate.
The technical scheme of the invention has the following beneficial effects:
1) the thin film transistor with the self-aligned grid electrode and the self-aligned source/drain electrode can be formed, and the overlapping of the projection of the grid electrode and the projection of the source/drain electrode is avoided, so that the unfavorable coupling capacitance is avoided.
2) Only 3 mask plates (grid → active layer → source/drain) are adopted, the exposure process is less, the cost is saved, and the yield advantage similar to a Back Channel (BCE) structure is possessed.
3) The active layer is directly protected by the insulating protection layer after being formed, so that the active layer can be prevented from being damaged by the subsequent source electrode and drain electrode manufacturing process, and the protective advantage similar to an etching barrier layer (ESL) structure is achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic structural diagram of a mask according to an embodiment of the present invention;
fig. 2-8 are schematic flow charts illustrating a method for fabricating a thin film transistor according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.
Referring to fig. 1, an embodiment of the present invention provides a mask for manufacturing a thin film transistor, where the mask includes:
a first partial light-transmitting region D corresponding to the gate of the thin film transistor;
the second partial light-transmitting areas C are positioned at two opposite sides of the first partial light-transmitting area D, and the light transmittance of the second partial light-transmitting areas C is smaller than or equal to that of the first partial light-transmitting area D; the light transmittance of the first partial light-transmitting area D and the second partial light-transmitting area C may be set as required, for example, both may be a semi-light-transmitting area, that is, the light transmittance is 50%.
The opaque regions B are positioned at two sides of the second partial transparent region C, which are far away from the first partial transparent region D, wherein one opaque region B and one second partial transparent region C correspond to the source electrode or the drain electrode of the thin film transistor;
and a full light transmission region A located at the periphery of the first partial light transmission region D, the second partial light transmission region C and the non-light transmission region B.
By adopting the mask in the embodiment of the invention, the self-aligned thin film transistor of the grid electrode and the source/drain electrode can be manufactured.
The following is a description of a process for fabricating a thin film transistor using the mask in the above embodiment.
Referring to fig. 2 to fig. 8, an embodiment of the invention further provides a method for manufacturing a thin film transistor, including the following steps:
step 21: referring to fig. 2, a substrate 101 is provided;
the base substrate 101 may be a glass substrate or the like.
Step 22: referring to fig. 3, a gate 102, a gate insulating layer 103, an active layer 104 and an insulating protection layer 105 are sequentially formed on the substrate 101, wherein the active layer 104 is made of a transparent semiconductor material;
the material of the gate 102 is an opaque metal material, and optionally, a metal material with a high reflectivity, such as copper (Cu), aluminum (Al), or silver (Ag), may be used.
The gate insulating layer 103 is made of a transparent insulating material, the gate insulating layer 103 may have a single-film structure or a multi-film structure, and in the case of the single-film structure, the material may be selected from one of silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx), and in the case of the multi-film structure, the material may be selected from any two or more of SiOx, SiON, and SiNx.
The material of the active layer 104 is a transparent semiconductor material, and may be Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Zinc Oxide (IZO), or the like.
In the embodiment of the invention, after the active layer 104 is prepared, the insulating protection layer 105 is directly covered on the active layer 104, so that the damage of the subsequent source and drain electrode processes to the active layer 104 can be avoided, and the protection advantage similar to an etching barrier layer (ESL) structure is realized.
Step 23: referring to fig. 4 and 5, a photoresist 106 is formed on the insulating protection layer 105, and the photoresist 106 is exposed and developed by using the mask described in the above embodiment to form a photoresist pattern, where the photoresist pattern includes: a photoresist full-reserved area 1061 corresponding to the full-light-transmitting area a of the mask, a first photoresist partial-reserved area 1062 corresponding to the first partial-light-transmitting area D of the mask, a second photoresist partial-reserved area 1063 corresponding to the second partial-light-transmitting area C of the mask, and a photoresist removed area 1064 corresponding to the light-transmitting area B of the mask, wherein the thickness of the second photoresist partial-reserved area 1063 is less than that of the first photoresist partial-reserved area 1062;
in embodiments of the invention, the lithography 106 is a negative photoresist, which is insoluble in the developer solution in the irradiated portions and soluble in the developer solution in the non-irradiated portions.
In the embodiment of the present invention, the second partially transparent region C exists for the following functions: the gate can be completely covered by a part of light-transmitting regions (C + D) on the mask, and the phenomenon that the source/drain electrode and the gate cannot be self-aligned due to the alignment deviation of the mask in the exposure process is avoided, namely the projection overlapping of the formed source/drain electrode and the gate is avoided.
In the exposure process, referring to fig. 5, since the insulating protection layer 105, the gate insulating layer 103 and the active layer 104 at the bottom of the second partial light-transmitting area C are made of transparent materials, the irradiation light (e.g., ultraviolet light) of the exposure machine is directly transmitted, and the exposure dose of the photoresist in the second partial light-transmitting area C is only the irradiation light. In contrast, since the gate 102 at the bottom of the first partial light-transmitting region D is made of a metal reflective material, the light irradiated by the exposure machine is reflected by the gate 102 after being projected, and the exposure dose of the photoresist in the first partial light-transmitting region D is epi-light + reflected light. Therefore, the thickness of the photoresist reserved in the first light-transmitting region D is greater than that of the photoresist reserved in the second light-transmitting region C, so that the selectivity of the photoresist thickness in different regions (the thickness of the photoresist directly above the gate (i.e., the channel) > the source and drain) is realized.
Step 24: referring to fig. 6, the photoresist pattern and the insulating protection layer 105 are etched, so that the thicknesses of the photoresist full-remaining area 1061 and the first photoresist partial-remaining area 1062 are reduced, the photoresist of the second photoresist partial-remaining area 1063 is completely removed, and an opening 1051 is formed in the portion of the insulating protection layer 105 not covered by the photoresist;
step 25: referring to fig. 7, forming a source drain metal layer 107, wherein the source drain metal layer 107 covers the etched residual photoresist and the opening 1051;
step 26: referring to fig. 8, the remaining photoresist and the source-drain metal layer on the remaining photoresist are stripped to form the source electrode 1071 and the drain electrode 1072, the source electrode 1071 and the drain electrode 1072 are connected to the active layer 104 through the opening 1051, and orthographic projections of the source electrode 1071 and the drain electrode 1072 on the substrate 101 are not overlapped with an orthographic projection of the gate electrode 102 on the substrate 101.
In this step, a lift-off process is used to prepare the source and drain. The thickness of the light resistance is in the magnitude of micrometers, and the thickness of the source drain metal layer is in the magnitude of hundreds of nanometers, so that the method is suitable for the stripping process.
It can be seen that, in the finally formed thin film transistor, the source and drain electrodes are strictly positioned in the areas corresponding to the second partial transparent area C and the opaque area B, the gate electrode (channel) is strictly positioned in the area corresponding to the first partial transparent area D, and the projected areas of the gate electrode and the source/drain electrodes are not overlapped, so that self-alignment is realized.
At present, in order to realize a complete thin film transistor structure, a thin film transistor with an ESL structure requires 4 masks (gate → active layer → etching barrier layer → source/drain electrode), a thin film transistor with a BCE structure requires 3 masks (gate → active layer → source/drain electrode), the former requires a large number of exposure processes and is high in cost, and the latter exposes the active layer surface for a long time and needs to undergo processes of film formation, etching and the like of the source/drain electrode, which may cause damage to the active layer surface.
The manufacturing method of the thin film transistor in the embodiment of the invention has the following advantages:
1) the thin film transistor with the self-aligned grid electrode and the self-aligned source/drain electrode can be formed, and the overlapping of the projection of the grid electrode and the projection of the source/drain electrode is avoided, so that the unfavorable coupling capacitance is avoided.
2) Only 3 mask plates (grid → active layer → source/drain) are adopted, the exposure process is less, the cost is saved, and the yield advantage similar to a Back Channel (BCE) structure is possessed.
3) After the active layer is formed, the active layer is directly protected by the insulating protection layer, so that the active layer can be prevented from being damaged by the subsequent source electrode and drain electrode manufacturing process, and the active layer has the protection advantage similar to an ESL structure.
In this embodiment of the present invention, optionally, the step of etching the photoresist pattern and the insulating protection layer includes: and synchronously etching the photoresist pattern and the insulating protection layer by adopting a dry etching process so as to save working procedures and reduce cost.
In an embodiment of the present invention, referring to fig. 6, optionally, the step of etching the photoresist pattern and the insulating protection layer includes: in the process of etching the photoresist pattern and the insulating protection layer 105, the active layer 104 exposed by the opening 1051 is subjected to a conductor treatment to form a source contact region 1041 and a drain contact region 1042. In the embodiment of the invention, specific gas can be selected to process the active layer 104 exposed by the opening in the etching process, and the region where the active layer 104 is contacted with the source/drain is made conductive, so that the contact resistance of the source and the drain is improved, the series resistance is reduced, and the characteristics of the thin film transistor are improved.
The embodiment of the invention also provides a manufacturing method of the array substrate, which comprises the step of manufacturing the thin film transistor by adopting the manufacturing method of the thin film transistor in any embodiment.
An embodiment of the present invention further provides a thin film transistor, which is manufactured by using the manufacturing method of the thin film transistor in any of the above embodiments, with reference to fig. 8, the thin film transistor includes:
a base substrate 101;
a gate electrode 102;
a gate insulating layer 103;
an active layer 104, wherein the material of the active layer 104 is a transparent semiconductor material;
the insulating protective layer 105 is provided with an opening;
a source electrode 1071 and a drain electrode 1072, the source electrode 1071 and the drain electrode 1072 contacting the active layer 107 through the opening, orthographic projections of the source electrode 1071 and the drain electrode 1072 on the substrate base plate 101 not overlapping with orthographic projections of the gate electrode 102 on the substrate base plate 101, and orthographic projections of the source electrode 1071 and the drain electrode 1072 on the substrate base plate 101 overlapping with orthographic projections of the opening on the substrate base plate 101.
The grid electrode and the source/drain electrode of the thin film transistor in the embodiment of the invention are self-aligned, and the overlapping of the projection of the grid electrode and the projection of the source/drain electrode is avoided, so that the unfavorable coupling capacitance is avoided.
In this embodiment of the present invention, optionally, the active layer 104 includes: an active region 1043, and a source contact region 1041 and a drain contact region 1042 located at two opposite sides of the active region 104, where the active region 1043 is a semiconductor, the source contact region 1041 and the drain contact region 1042 are conductors, and orthographic projections of the source contact region 1041 and the drain contact region 1042 on the substrate 101 are overlapped with orthographic projections of the openings on the substrate 101.
The embodiment of the invention also provides an array substrate which comprises the thin film transistor.
The array substrate can be a TFT-LCD or AMOLED type array substrate.
The embodiment of the invention also provides a display device which comprises the array substrate.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (9)

1. A method for manufacturing a thin film transistor includes:
providing a substrate base plate;
sequentially forming a grid electrode, a grid electrode insulating layer, an active layer and an insulating protection layer on the substrate, wherein the active layer is made of a transparent semiconductor material;
forming a light resistance on the insulation protection layer, exposing and developing the light resistance by adopting a mask plate to form a light resistance pattern, wherein the mask plate comprises: the first partial light-transmitting area corresponds to the grid electrode of the thin film transistor; the second partial light-transmitting areas are positioned on two opposite sides of the first partial light-transmitting area, and the light transmittance of the second partial light-transmitting areas is smaller than or equal to that of the first partial light-transmitting areas; the opaque regions are positioned on two sides of the second partial transparent region, which are far away from the first partial transparent region, wherein one opaque region and one second partial transparent region correspond to the source electrode or the drain electrode of the thin film transistor; a full light-transmitting region located at the periphery of the first partial light-transmitting region, the second partial light-transmitting region and the non-light-transmitting region; the photoresist pattern includes: the photoresist stripping device comprises a photoresist full-reserved region corresponding to a full-light-transmitting region of the mask, a first photoresist partial-reserved region corresponding to a first partial-light-transmitting region of the mask, a second photoresist partial-reserved region corresponding to a second partial-light-transmitting region of the mask and a photoresist stripping region corresponding to a non-light-transmitting region of the mask, wherein the thickness of the second photoresist partial-reserved region is smaller than that of the first photoresist partial-reserved region;
etching the photoresist pattern and the insulating protection layer to reduce the thickness of the photoresist full-retention area and the first photoresist partial-retention area, completely eliminating the photoresist in the second photoresist partial-retention area, and forming an opening in the part of the insulating protection layer which is not covered by the photoresist;
forming a source drain metal layer, wherein the source drain metal layer covers the etched residual photoresist and the opening;
and stripping the residual photoresistor and the source drain metal layer positioned on the residual photoresistor to form a source electrode and a drain electrode.
2. The method of manufacturing a thin film transistor according to claim 1, wherein a material of the gate electrode is Cu, Al, or Ag.
3. The method of manufacturing a thin film transistor according to claim 1, wherein the step of etching the photoresist pattern and the insulating protection layer comprises:
and synchronously etching the photoresist pattern and the insulating protection layer by adopting a dry etching process.
4. The method of manufacturing a thin film transistor according to claim 1, wherein the step of etching the photoresist pattern and the insulating protection layer comprises:
and in the process of etching the photoresist pattern and the insulating protection layer, conducting conductor treatment on the active layer exposed by the opening to form a source contact region and a drain contact region.
5. A method for manufacturing an array substrate, comprising the step of manufacturing a thin film transistor by using the method for manufacturing a thin film transistor according to any one of claims 1 to 4.
6. A thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of claims 1 to 4, the thin film transistor comprising:
a substrate base plate;
a gate electrode;
a gate insulating layer;
the material of the active layer is a transparent semiconductor material;
the insulating protective layer is provided with an opening;
the source electrode and the drain electrode are in contact with the active layer through the opening, the orthographic projection of the source electrode and the drain electrode on the substrate is not overlapped with the orthographic projection of the grid electrode on the substrate, and the orthographic projection of the source electrode and the drain electrode on the substrate is overlapped with the orthographic projection of the opening on the substrate.
7. The thin film transistor of claim 6, wherein the active layer comprises: the active region is a semiconductor, the source electrode contact region and the drain electrode contact region are conductors, and orthographic projections of the source electrode contact region and the drain electrode contact region on the substrate are overlapped with orthographic projections of the opening holes on the substrate.
8. An array substrate comprising the thin film transistor according to claim 6 or 7.
9. A display device comprising the array substrate according to claim 8.
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