CN110047537A - A kind of semiconductor storage and computer system - Google Patents
A kind of semiconductor storage and computer system Download PDFInfo
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- CN110047537A CN110047537A CN201910278401.6A CN201910278401A CN110047537A CN 110047537 A CN110047537 A CN 110047537A CN 201910278401 A CN201910278401 A CN 201910278401A CN 110047537 A CN110047537 A CN 110047537A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
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Abstract
The present invention provides a kind of semiconductor storage and computer systems, the semiconductor storage is connected by system bus with host, including volatile memory, first nonvolatile memory, storage control, power supply signal and control signal of the storage control in response to host, and data access operation alternatively is carried out with the volatile memory or the first nonvolatile memory, and the second nonvolatile memory being connected with storage control, storage control is according to the power supply signal of host, and it is saved in the form of power supply status data to second nonvolatile memory, kernel bypass module is set between storage control and host.In the present invention, power supply status data can be written in the second nonvolatile memory when computer is in normal shutdown, it avoids that power supply status data are continually written into the first nonvolatile memory, to improve the service life of the first nonvolatile memory in semiconductor storage significantly.
Description
Technical field
The present invention relates to technical field of semiconductor memory, more particularly to have emergency when outer power down favorite applied to computer
A kind of semiconductor storage of backup functionality, and a kind of computer system based on the semiconductor storage.
Background technique
With the continuous development of semiconductor devices process technique, the line width of central processing unit (CPU) and memory (Memory)
It is substantially improved with frequency, the I/O bottleneck problem of traditional mechanical hard disk (HDD) restricts mentioning for computer performance increasingly severely
It rises, then people begin to use flash memory (FLASH) to replace HDD.Flash memory generallys use single layer cell structure (Single-level
Cell, SLC) or multilevel-cell structure (Multi-level Cell, MLC).But the manufacturing cost of SLC type flash memory generally compared with
Height, so at present usually using MLC type flash memory, but such flash memory is there are certain service life, and usually 3,000
It is secondary or so.Simultaneously as DRAM is a kind of volatile memory, therefore when computer power down, the number temporarily stored in memory
According to can disappear；Therefore memory and flash memory can be combined into a kind of Nonvolatile memory (NVM, Non-volatile
Memory).When computer normal power supply, NVM using it includes memory (such as DRAM) rapidly process data；Work as meter
When calculation machine normal shutdown or unexpected power down, the metadata in computer operating system can be protected by the internal bus of the NVM
It deposits into flash memory.
Metadata may include for manage the mapping between logical address and physical address, bad piece of management, wear leveling,
For detecting or any information of the error correcting code of correction data mistake (" ECC ") data or any combination of them.Metadata
It may include the data as provided by the file system in computer together with user data, such as logical address.In this way, general
For, metadata can be about or be relevant to any information of user data, or deposit commonly used in managing non-volatile
The operation of reservoir and any information of storage unit.But when calculating is in normal shutdown and unexpected power down, it usually needs
Power supply status data are saved by controlling chip into flash memory.When computer power-on self-test, last computation machine is first determined whether
Shutdown is normal shutdown or unexpected power down, to read power supply status reading data from flash memory by control chip and determine certainly
Inspection sequence, above-mentioned power supply status data generally take up the memory space of one page (Page) size, this page of size is 4KB.
Since any data are when being written flash memory, it is necessary first to the legacy data in a certain Block (block number evidence) is first wiped,
And the data being written will be needed to be written in the Block of erasing data.In general, the size of a Block is 512KB (4KB*
128) or 1024KB (4KB*256), even more greatly.Which results under the service condition of computer normal shutdown, need
Power supply status data to be continually written to flash memory, to exacerbate the abrasion of flash memory, influence flash memory service life.
Meanwhile Ceph cluster is current most popular open source distributed storage architecture, in a set of architecture simultaneously
It supports block storage, object storage and file storage, supports PB grades of extended capability, be widely used in cloud computing environment.However,
Under the configuration of solid storage medium (such as nand memory), the storage performance that Ceph cluster is embodied only has hardware limit
40% or so of energy, therefore significantly limit computer system or the storage based on cloud platform constructed by computer system
Ability, especially when reading big file, there are certain performance deficiencies.
Summary of the invention
It is an object of the invention to disclose a kind of semiconductor storage, to avoid frequency when computer is in normal shutdown
Power supply status data are written into flash memory numerously, to improve the service life of flash memory in semiconductor storage, and realize
The ephemeral data in memory is saved when abnormal power-down；Present invention further teaches a kind of computer systems simultaneously, to shorten the road IO
Diameter promotes the IOPS of CPU, to improve the storage performance of Ceph cluster.
For achieving the above object, present invention firstly provides a kind of semiconductor storage, the semiconductor storages
Device is connected by system bus with host, comprising:
Volatile memory, passes through the storage control of interface module and host communication, institute at the first nonvolatile memory
Storage control is stated in response to the power supply signal of the host and control signal, and alternatively with the volatile memory or the
One nonvolatile memory carries out data access operation；
The semiconductor storage further includes the second nonvolatile memory being connected with the storage control, described
Storage control is saved in the form of power supply status data to second non-volatile memories according to the power supply signal of host
Kernel bypass module is arranged in device between the storage control and host.
As a further improvement of the present invention, second nonvolatile memory is ReRAM, FRAM；Described first is non-
Volatile memory is nand memory, phase transition storage.
As a further improvement of the present invention, further include power management module and be connected thereto spare energy storage device, institute
It states spare energy storage device and is selected from super capacitor or lithium battery, the power management module and the first nonvolatile memory, the
Two nonvolatile memories, volatile memory and storage control provide power supply.
As a further improvement of the present invention, the interface module is based on PCI-e communications protocol or I2C communications protocol with
System bus is in communication with each other.
As a further improvement of the present invention, the capacity of second nonvolatile memory is not less than 1MB.
As a further improvement of the present invention, the storage control is based on fpga chip or asic chip platform, and
It is formed using Verilog VHDL programming technique.
As a further improvement of the present invention, the kernel bypass module is selected from DPDK module, SPDK module or RDMA
Module.
As a further improvement of the present invention, the storage control configures MMAP interface, and passes through the MMAP interface
It is communicated with interface module.
Based on above-mentioned identical invention thought, present invention further teaches a kind of computer systems characterized by comprising place
Manage device, and the semiconductor storage being connected by system bus with host；
The semiconductor storage include volatile memory, the first nonvolatile memory, by interface module with
The storage control of host communication, the storage control and select one in response to the power supply signal and control signal of the host
Ground and the volatile memory or the first nonvolatile memory carry out data access operation；
The semiconductor storage further includes the second nonvolatile memory being connected with the storage control, storage
Controller is saved in the form of power supply status data according to the power supply signal of host to second nonvolatile memory, described
Kernel bypass module is set between storage control and host.
As a further improvement of the present invention, the kernel bypass module is selected from DPDK module, SPDK module or RDMA
Module；The storage control configures MMAP interface, and is communicated by the MMAP interface with interface module；Described first is non-
Volatile memory is nand memory, phase transition storage；Second nonvolatile memory is ReRAM, FRAM.
It compared with prior art, can when computer is in normal shutdown the beneficial effects of the present invention are: in the present invention
Power supply status data are written in the second nonvolatile memory, avoid that electricity is continually written into the first nonvolatile memory
Source status data is realized to improve the service life of the first nonvolatile memory in semiconductor storage significantly
The ephemeral data in memory is saved in abnormal power-down；Meanwhile by the way that kernel bypass module is arranged, the road IO is shortened significantly
Diameter promotes the IOPS of CPU, to improve the storage for the Ceph cluster set up based on the semiconductor storage significantly
Energy.
Detailed description of the invention
Fig. 1 is a kind of structure chart of semiconductor storage of the present invention；
Fig. 2 is a kind of a kind of structure chart of the semiconductor storage of the present invention in variation；
Fig. 3 is a kind of structure chart of computer system of the present invention；
Wherein, the reference numerals are as follows in specification:
100- semiconductor storage；200- computer system；101- controller；The first nonvolatile memory of 102-；
103- volatile memory；104- power management module；The second nonvolatile memory of 105-；106- external power supply；107- master
Machine；109- kernel bypass module；108- interface module；111-MMAP interface；112- system bus；110-CPU (processor)；
118- physical network card (NIC)；130- outer net network.
Specific embodiment
The present invention is described in detail for each embodiment shown in reference to the accompanying drawing, but it should be stated that, these
Embodiment is not limitation of the present invention, those of ordinary skill in the art according to these embodiments made by function, method,
Or equivalent transformation or substitution in structure, all belong to the scope of protection of the present invention within.
Before elaborating each embodiment of the present invention, the portion of techniques term in specification specific embodiment is carried out
Definition.Term " solid storage medium " and " nonvolatile memory " have equivalents.Term " first ", " second " are only used for area
Divide different technologies feature, should not be understood as the concrete restriction to technical solution of the present invention.
Embodiment one:
Join shown in Fig. 1, the present embodiment discloses a kind of semiconductor storage 100, which passes through
System bus 112 is connected with host 107, comprising:
Volatile memory 103, passes through interface module 108 and the communication of host 107 at first nonvolatile memory 102
Storage control 101.Storage control 101 in response to the host 107 power supply signal and control signal, and alternatively and easily
The property lost memory 103 or the first nonvolatile memory 102 carry out data access operation.
In the present embodiment, the semiconductor storage 100 further include be connected with storage control 101 it is second non-volatile
Property memory 105, storage control 10 are saved in the form of power supply status data to institute according to the power supply signal of host 107
The second nonvolatile memory 105 is stated, kernel bypass module 109 is set between storage control 101 and host 107.Specifically,
The kernel bypass module 109 is selected from DPDK module, SPDK module or RDMA module.
DPDK module (Data Plane Development Kit) is run based on linux system, is used for rapid data packet
The function library of processing and driving are gathered, and data processing performance and handling capacity can be greatly improved, and improve data plane application program
Working efficiency.DPDK module has used poll (polling) and non-interrupted has handled data packet.When receiving data packet, warp
The trawl performance (insertion is run in the physical network card in Fig. 3 (NIC) 118) of DPDK module heavy duty will not pass through interrupt notification
CPU, but volatile memory 103 is directly write the data packet, deliver the interface that application layer software is provided by DPDK module
It directly handles, saves the copy time of a large amount of CPU break period and volatile memory 103 in this way.Deliver application layer
Software can carry out data access to the semiconductor storage 100 by API and host 107, and the data access may include number
According to write operation, data read operation, data modification operation, data delete operation or data backup operation.
SPDK module (Storage Performance Development Kit) is non-volatile using first for accelerating
Memory 102 (for example, by using NVMe SSD form) accelerates library as the application software that rear end stores, and the core of the software library is
User space, asynchronous, polling mode NVMe driving.Delay (Latency) can be greatly lowered by configuring the SPDK module,
The IOPS of single CPU core is promoted simultaneously.The rear end storage can be used the revealed one kind of one or more the present embodiment and partly lead
Body storage device 100 forms.
The access of RDMA module (Remote Direct Memory Access) full name remote direct data is exactly to understand
Certainly in network transmission servers' data handle delay and generate.RDMA module is by network the directly incoming calculating of data
The rear end of machine system stores, and the rear end for the computer system that data move quickly into opposite end from a computer system is stored
In, without having any impact to operating system (OS), with eliminate data duplication performed in external rear end storage and
The expense of context switching, thus memory bandwidth and cpu cycle can be liberated for improving application system performance.
In the present embodiment, term " memory " and term " volatile memory 103 " have equivalents, and including DDR2~
The memory of the various specifications such as DDR5.
A kind of revealed semiconductor storage 100 of the present embodiment is configured in computer system 200 (shown in ginseng Fig. 3)
In, and a Ceph cluster is formed by multiple computer systems, by the way that kernel bypass module 109 is arranged, IO is shortened significantly
Path promotes the IOPS of CPU, to improve the Ceph cluster set up based on the semiconductor storage 100 significantly
Storage performance.
Specifically, second nonvolatile memory 105 is ReRAM (resistive random access memory), FRAM is (magnetic
Random access memory).First nonvolatile memory 102 is nand memory, phase transition storage, and most preferably NAND is deposited
Reservoir.The semiconductor storage 100 further includes power management module 104 and is connected thereto spare energy storage device 106, spare
Energy storage device 106 is selected from super capacitor or lithium battery, power management module 104 and the first nonvolatile memory 102, second
Nonvolatile memory 105, volatile memory 103 and storage control 101 provide power supply.It is further preferred that this is spare
Energy storage device 106 can be 2.5V by five operating voltages, and capacitance is 500 farads and is connected in series, to form 12.5V and capacitance
For 100 farads of super capacitor group.
Under normal conditions, i.e., computer system normal power supply when, 220VAC can be passed through by the power management module 104
After ballast, inversion, steady pressure treatment, be converted to the power specifications such as+5.0VDC ,+3.3VDC, with to the first nonvolatile memory
102, the second nonvolatile memory 105, volatile memory 103 and storage control 101 provide power supply, to maintain volatibility
The self-refresh (Self-refresh) of memory 103 with interim storing data, and is executed by processor 110 or other equipment
Read operation and/or write operation.Meanwhile the power management module 104 is also built-in with voltage detecting real-time logic, in terms of detection
Whether the external power supply of calculation machine system is normal.When computer powered-off fault occurs, external power supply will not be dropped from 220VAC immediately
Down to 0, therefore when power management module 104 detects the voltage of external power supply lower than certain range, will call immediately
Spare energy storage device 106 is to the first nonvolatile memory 102, the second nonvolatile memory 105, volatile memory 103
And storage control 101 provides and meets the working power specification of respective specification, thus the under the guidance of storage control 101
One or more data transmission channel arranged side by side is established between one nonvolatile memory 102 and volatile memory 103 (not
Diagram), the first nonvolatile memory 102 is written in the data that volatile memory 103 is temporarily saved.
When power management module 104 monitors that power supply signal VSS, the voltage of VCC are sent out beyond after normal voltage range 90%
Send computer system power-off signal to storage control 101.Storage control 101 receives transmitted by power management module 104
Computer system power-off signal or Power_OK (the two is digital signal).Power supply signal VSS, VCC are the electricity of host 107
Source signal.
When storage control 101 receives power-off signal, by the data backup in volatile memory 103 to first non-
In volatile memory 102；It, will be standby in the first nonvolatile memory 102 when storage control 101 receives Power_OK
The rewriting data of part enters in volatile memory 103, and via serial line interface by processor 110 (shown in ginseng Fig. 3) or host
107 directly access.Host 107, which is construed as processor (CPU) or other, in this application to be sent out by user
Send the platform, device or system of master control order, it might even be possible to be virtual machine or pseudo operation interface, operation interface, may be used also
Think and receives user instructions and by the user interface (UI) of network connection.
Specifically, the control signal in the present embodiment be RAS CAS WE CS CKE ODT；Data-signal be DQ [63:
0],DQS[0:17]；Address signal is A [15:0], BA [2:0].
Signified power supply status data refer to that " power-off signal " described above (or is referred to as " abnormal in the present embodiment
Power-off signal ") and " power up signal " (or referred to as " Power_OK ") it is formed by status data.Pass through recording power
Status data can characterize and be deployed with a kind of revealed computer system 200 of semiconductor storage 100 of the present embodiment
The switching on and shutting down situation and powered-off fault situation of (ginseng Fig. 3 shown in), with only in powered-off fault will in volatile memory 103 it is interim
The data of preservation are written in the first nonvolatile memory 102, and will not face in volatile memory 103 in normal switch machine
The data of Shi Baocun are written in the first nonvolatile memory 102.Since the probability that abnormal power-down occurs in computer system is usual
It is smaller, therefore it is based on the revealed technical solution of the present embodiment, it can effectively prevent in computer system normal switch machine
The generation of power supply status data is continually written in scene to the first nonvolatile memory 102, to effectively extend
The service life of one nonvolatile memory 102, and the storage of the first nonvolatile memory 102 can be also reduced to a certain extent
The consumption in space.
Meanwhile in the present embodiment, the capacity of second nonvolatile memory 105 is not less than 1MB, such as can 128BM
Or smaller specification, to reduce the cost of the second nonvolatile memory 105.
The revealed interface module 108 of the present embodiment is based on PCI-e communications protocol or I2C communications protocol and system bus
112 are in communication with each other, and most preferably PCI-e communications protocol, and transmit data in a serial fashion, the work of PCI-e communications protocol
Mode is a kind of mode for being referred to as " voltage differential transmission ".Two copper wire indicate that logic is accorded with by mutual voltage difference
Number 0 and 1, and highest supports the transmission rate of 100Gbps.Storage control 101 is based on fpga chip or asic chip platform,
And most preferably fpga chip；Storage control 101 is formed using Verilog VHDL programming technique.
Embodiment two:
Join a kind of second of specific embodiment of semiconductor storage 100 of the present invention illustrated in fig. 2.The present embodiment
Compared with embodiment one, the main distinction is a kind of revealed semiconductor storage 100, in the present embodiment, storage
Controller 101 configures MMAP interface 111, and is communicated by MMAP interface 111 with interface module 108.
When computer system collapse extremely or powered-off fault, the data in volatile memory 103 can lose.It is right
In such as database to the very high application program of data coherence request, it is likely to result in havoc.To solve above-mentioned ask
Topic is provided as access common memory for application program, is directly accessed in the present embodiment by setting MMAP interface 111
Logical block in volatile memory 103 improves to bypass operating system page cache mechanism to volatile memory
103 access efficiency, caused by avoiding because of operating system extremely collapse or powered-off fault caused by data in database not
Consensus.In the present embodiment, so-called " application program " is understood to be database, and calculating can be run by also being understood as
Machine code and the computer program with certain function.
Application program can be created the data of structuring in the form of normal file, be read and write, and be deleted.When application program with
When MMP interface 111 maps a file, virtual address (Virtual is distributed in the user's space of the application program first
Address), the mapping relations of file and virtual address are established.Then the file system by running in storage control 101
(file system) is these Virtual Space logical tiles (that is, true physical memory).In this way, each section of virtual address
Just one-to-one relationship is produced with the deviation post of a logical block hereof.This one-to-one and unique corresponding relationship,
It is ultimately used to construct the page table in the sector address space, passes through MMU's (Memory Management Unit, memory management unit)
Address translation feature directly accesses the ability of the semiconductor storage 100 to realize application program in user's space；Especially
, it is that application program in user's space directly accesses the volatile storage in the semiconductor storage 100 in general
Data in device 103.Wherein, the effect of MMU is just responsible for virtual address (Virtual address) and is converted to physical address
(Physical address).Applicant particular, it is found that, by configuring the MMP interface 111 in semiconductor storage 100,
It can improve significantly and bottom is passed through based on the computer system 200 by configuring the semiconductor storage 100 (shown in ginseng Fig. 3)
Layer virtualization is formed by the disk I/O access efficiency of virtual machine Q emu-KVM, especially in the big file of reading, such as more than
When the file of 100MB, there is better real-time.
The technical solution of same section, please join embodiment in semiconductor storage disclosed in the present embodiment and embodiment one
Described in one, details are not described herein.
Embodiment three:
Referring to shown in 3, the present embodiment discloses a kind of computer system for cooperation.A kind of revealed computer of the present embodiment
System may include the revealed a kind of semiconductor of combination of one or more embodiment one or embodiment two or the two
Storage device 100.
The computer system 200, comprising: processor 110, and partly led by what system bus 112 was connected with host 107
Body storage device 100.The semiconductor storage 100 includes volatile memory 103, the first nonvolatile memory 102, leads to
The storage control 101 of interface module 108 and the communication of host 107 is crossed, the storage control 101 is in response to the host 107
Power supply signal and control signal, and alternatively carried out with the volatile memory 103 or the first nonvolatile memory 102
Data access operation.
Semiconductor storage 100 further includes the second nonvolatile memory being connected with the storage control 101
105, storage control 10 is saved in the form of power supply status data according to the power supply signal of host 107 to described second non-volatile
Property memory 105, between the storage control 101 and host 107 be arranged kernel bypass module 109.Kernel bypass module 109
Selected from DPDK module, SPDK module or RDMA module.Storage control 101 configures MMAP interface 111, and passes through the MMAP
Interface 111 is communicated with interface module 108.Specifically, in the present embodiment, which is NAND
Memory, phase transition storage, and preferably nand memory.Second nonvolatile memory 105 is ReRAM, FRAM, and preferred
For FRAM.
In the present embodiment, in computer system 200 at least one 100 carry of semiconductor storage to system bus
112, CPU110 are read out the data in semiconductor storage 100 by system bus 112 and write operation.Meanwhile
118 carry of physical network card (NIC) is mutually communicated to system bus 112, and with outer net network 130.
The technical solution ginseng embodiment one and/or reality that semiconductor storage 100 is relied on disclosed in the present embodiment
It applies shown in example two, details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the module or
The division of unit, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units
Or component can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute
Display or the mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, device or unit
Indirect coupling or communication connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped
Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should
It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
The other embodiments being understood that.
Claims (10)
1. a kind of semiconductor storage (100), the semiconductor storage (100) passes through system bus and host (107)
It is connected characterized by comprising
Volatile memory (103), the first nonvolatile memory (102) are led to by interface module (108) and host (107)
The storage control (101) of news, the storage control (101) are believed in response to the power supply signal of the host (107) and control
Number, and alternatively data access operation is carried out with the volatile memory (103) or the first nonvolatile memory (102)；
The semiconductor storage (100) further includes the second non-volatile memories being connected with the storage control (101)
Device (105), the storage control (10) save according to the power supply signals of host (107), and in the form of power supply status data
To second nonvolatile memory (105), kernel is set between the storage control (101) and host (107) and is bypassed
Module (109).
2. semiconductor storage according to claim 1, which is characterized in that second nonvolatile memory
It (105) is ReRAM, FRAM；First nonvolatile memory (102) is nand memory, phase transition storage.
3. semiconductor storage according to claim 1, which is characterized in that further include power management module (104) with
And spare energy storage device (106) are connected thereto, the spare energy storage device (106) is selected from super capacitor or lithium battery, described
Power management module (104) and the first nonvolatile memory (102), the second nonvolatile memory (105), volatile storage
Device (103) and storage control (101) provide power supply.
4. semiconductor storage according to claim 1, which is characterized in that the interface module (108) is based on PCI-e
Communications protocol or I2C communications protocol is in communication with each other with system bus.
5. semiconductor storage according to claim 1 or 2, which is characterized in that second nonvolatile memory
(105) capacity is not less than 1MB.
6. semiconductor storage according to any one of claim 1 to 4, which is characterized in that the storage control
(101) it perhaps asic chip platform and is formed using Verilog VHDL programming technique based on fpga chip.
7. semiconductor storage according to claim 6, which is characterized in that the kernel bypass module (109) is selected from
DPDK module, SPDK module or RDMA module.
8. semiconductor storage according to claim 6, which is characterized in that storage control (101) configuration
MMAP interface (111), and communicated by the MMAP interface (111) with interface module (108).
9. a kind of computer system (200) characterized by comprising processor, and pass through system bus and host (107)
Connected semiconductor storage (100)；
The semiconductor storage (100) includes volatile memory (103), the first nonvolatile memory (102), passes through
The storage control (101) of interface module (108) and host (107) communication, the storage control (101) is in response to the master
The power supply signal of machine (107) and control signal, and alternatively with the volatile memory (103) or the first non-volatile memories
Device (102) carries out data access operation；
The semiconductor storage (100) further includes the second non-volatile memories being connected with the storage control (101)
Device (105), storage control (10) are saved in the form of power supply status data according to the power supply signal of host (107) to described
Kernel bypass module is arranged in two nonvolatile memories (105) between the storage control (101) and host (107)
(109)。
10. computer system according to claim 9, which is characterized in that the kernel bypass module (109) is selected from DPDK
Module, SPDK module or RDMA module；The storage control (101) configures MMAP interface (111), and passes through the MMAP
Interface (111) is communicated with interface module (108)；First nonvolatile memory (102) is nand memory, phase transformation is deposited
Reservoir；Second nonvolatile memory (105) is ReRAM, FRAM.
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